5-stage pipelined 32-bit MIPS microprocessor in Verilog
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Updated
Apr 3, 2020 - Verilog
5-stage pipelined 32-bit MIPS microprocessor in Verilog
CS F425 Deep Learning course at BITS Pilani (Goa Campus)
This repository holds a list of cool resources for Silica.
Developing a four-legged Quadruped robot 'DIPLOID' with stable walking by reinforced learning on bezier gait and terrain awareness using SLAM technique as a part of long-term project undertaken by Team Robocon. (2019-present)
Repository of problems and solutions of labsheets used for Data Structures and Algorithms (CS F211) in Semester 2, 2020-21 at BITS Pilani - Hyderabad Campus.
A centralized collection of study materials, assignments, slides, and resources for my M.Tech Software Engineering program at BITS Pilani (2022-2024 batch).
Verilog Snippets for partial fulfilment of CS-F342 Computer Architecture,BITS Pilani
MIPS32 Assembly, Sorting Example in MIPS32 Assembly, CS-F342-Computer-Architecture-Lab
Mini-Project for Computer Networks BITS Pilani
see nalanda updates directly on the terminal
Design of an IoT-enabled Hybrid Renewable Energy Powered Smart Grid in MATLAB/Simulink environment.
A repository to encapsulate everything covered in BITS Pilani's Intro to Computer Programming [CS F111] course.
Compiler Project for course at BITS Pilani
DoJMA news app for BITS Pilani K K Birla Goa Campus students
Yet another attempt at CPSIG
Example codes for Linux Device Driver Course
Logic In Computer Science
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