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Make assignments between packed LogicArrays and Logics in generated SystemVerilog avoid a swizzle

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#559 In intel/rohd;

· mkorbel1 opened on Jan 29, 2025

Add WASM compiliation support

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#554 In intel/rohd;

· mkorbel1 opened on Jan 21, 2025

Resolve driver vs. receiver based on usage for certain types of operations

enhancementNew feature or requestNew feature or request

Status: Open.

#553 In intel/rohd;

· mkorbel1 opened on Jan 21, 2025

Omit redundant parentheses in generated SystemVerilog

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#552 In intel/rohd;

· mkorbel1 opened on Jan 21, 2025

Mark bit ranges in swizzles in generated SystemVerilog

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#551 In intel/rohd;

· mkorbel1 opened on Jan 21, 2025

Attaching a packed array port to an unpacked array port of a submodule generates bad SV

bugSomething isn't workingSomething isn't working

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#549 In intel/rohd;

· mkorbel1 opened on Jan 15, 2025

Add optional source annotation in generated outputs

enhancementNew feature or requestNew feature or request

Status: Open.

#547 In intel/rohd;

· mkorbel1 opened on Jan 15, 2025

Mark dangling ports in module instantiations

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#546 In intel/rohd;

· mkorbel1 opened on Jan 15, 2025

Automatic sorting and grouping for generated outputs

enhancementNew feature or requestNew feature or request

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#545 In intel/rohd;

· mkorbel1 opened on Jan 15, 2025

Error when sub-modules are already built is confusing

enhancementNew feature or requestNew feature or request

Status: Open.

#544 In intel/rohd;

· mkorbel1 opened on Jan 15, 2025

Allow swizzles to be receivers of assignments in generated SystemVerilog for nets

enhancementNew feature or requestNew feature or request

Status: Open.

#530 In intel/rohd;

· mkorbel1 opened on Nov 22, 2024

Consts that inferWidth to 0-width generate SystemVerilog with 0-width

bugSomething isn't workingSomething isn't working

help wantedExtra attention is neededExtra attention is needed

Status: Open.

#527 In intel/rohd;

· mkorbel1 opened on Oct 14, 2024