STA stands for Static Timing Analysis. It is a method to verify the timing correctness of a chip. It evaluates the delays of each timing path in a digital circuit incurred when a signal propagates through it. By this delay calculation, it is able to determine whether the chip meets or violates the timing constraints. In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.
In this 5 days workshop we have used open-source sign-off timing analysis tool STA and open-source Sky130 libraries, to perform the day-wise labs. Each day has a specific set of task to be completed under this workshop. Following is the detailed proof of work of labs of each day.
[Objective]: To understand the inputs to openSTA and run script commands.
[Objective]: To understand liberty files, SPEF, timing reports.
pin 'o'
pin 'a'
pin 'b'
I have observed the following differences between the two.
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First is the number of input pins both have.
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Second is the difference in maximum output capacitance.
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Third is the difference of the transition times and delays.
The main difference that I was able to find was in the delays as shown below.
We are performing timing analysis for the circuit shown below.
run.tcl file
runscript
run.tcl file
runscript
(Eco Insertion part)
run.tcl file
runscript
s27.v file
s27_eco.v file
- Kunal Ghosh, Co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd.
- Vikas Sachdeva, Advisor, Tech and VLSI Coach, Trainer and Innovator at vlsideepdive.
Arpit Sharma, B.Tech (2019-23), IPEC, Sahibabad, Delhi-NCR, India
Contact: [email protected], [email protected]