Fully Hard for FPGA without CPU core like Spartan 6 or Cyclone 4, e.t.c. features:
-setting bit (MSB, LSB) and bytes order (Little endian or Big endian);
-adjustable number of extra clocks when some devices need to make internal synchronization while CS is still
active and clock keeps going from clk (Dragster/Awaiba/Cmosis DR-2k-7);

Fully soft SPI with AXI Full interface with CPU.