The SAYAC processor is a Simple Architecture Yet Ample Circuitry. This is a RISCV-like open-source academic processor that was originally designed to support educational processor hardware architecture and implementation.However, the simple and ample architecture of this processor provides increased value enabling the researchers to devise new research directions in design, test, reliability, high-level modeling, and security. SAYAC is a 16-bit processor with a 16-bit address bus and a 16-bit bi-directional data bus. The processor has standard memory accessing handshaking signals, and separate IO read and write lines.
This processor is implemented in VHDL.Two different versions of the processor design are included in the VHDL directory. One is a behavioral (Functional) implementation and the other one is an ASIC implementation. Options to use Radix-4 and Radix-16 multipliers, Radix divider and CLA adders are added to this ASIC design. Also a high-level SystemC model of this processor is provided enabling fast high-level simulations. The ISS directory includes this SystemC-based Instruction Set Simulator. The project is currently going on and more details will be added in future. Copyright (C) 2021 CINI Cybersecurity National Laboratory and University of Teheran.