This project aims to provide a learning platform for RISC-V and Rust.
flowchart LR
hart[HART] --> bus{bus}
bus --> rom(ROM)
bus --> ram(RAM)
bus --> htif(HTIF)
ram --> dt(DTB)
bus --> rtc(RTC)
hart --> csr(CSR)
hart -->|SBI| see[SEE]
see -..-> hart
RAMis shared between one or moreharts via the busROMis shared between one or moreharts via the busRTCis memory mapped and reachable from the busSEEis globalCSRs are perhart(or per core)- The
SEEcan control allharts - The device tree (
DTB) is accessible viaRAM
| Definition | |
|---|---|
| HART | Hardware Thread |
| CSR | Control and Status Registers |
| SBI | Supervisor Binary Interface |
| SEE | Supervisor Execution Environment |
| ISA | Instruction Set Architecture |
| M | Machine Mode |
| XLEN | RISC-V 32 or 64 flavour |
| EEI | Execution Environment Interface |
| ABI | Application Binary Interface |
| RTC | Real Time Clock |
| DTS | Device Tree Source |
| FTD | Flattened Device Tree |
| DTB | Device Tree Blob |
| HTIF | Deprecated Host Device |
| FESVR | RISC-V Frontend Server |
| PLIC | Platform-Level Interrupt Controller |
| AMO | Atomic Memory Operation |
make -C test
cargo test
cargo runcd validation
podman build -t riscvvalidation .
podman run -it -v $PWD:/work:z -v $PWD/../target:/target riscvvalidation --verbose info arch-tests --clone
podman run -it -v $PWD:/work:z -v $PWD/../target:/target riscvvalidationCopyright 2023 Jonathan Buch
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
https://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
- RISC-V ISA Volume 1
- RISC-V ISA Volume 2
- RISC-V Technical Specifications
- RISC-V SBI
- RISC-V ELF psABI
- The RISC-V Microcontroller Profile
- RISC-V Counters (Zinctr)
- RISC-V ACLINT
- RISC-V PLIC
- RISC-V Online Assembler
- DarkRISCV
- RISC-V GNU Toolchain
- OpenHW Group CV32E40S User Manual
- rustsbi
- emuriscv
- Linux Kernel RISC-V architecture
- Misunderstanding RISC-V ecalls and syscalls
- Rust interior mutability
- UART Communications RISC-V OS In Rust
- RISC-V from scratch 3
- The Sodor Processor Collection
- An overview of OpenSBI
- Trivial RISC-V Linux Binary Bootloader
- Rare: Rust A RISC-V Emulator
- Writing a RISC-V Emulator in Rust
- Summit Bootflow
- Baremetal Timer
- RISC-V: A Bare-metal Introduction using C++. Machine Mode Timer
- Demystifying the RISC-V Linux software stack
- 6.S081: Interrupts
- RISC-V Bytes: Introduction to Instruction Formats