Reverse engineer of the hifive1 rev b bootloader since the source has not been released

hIMUdev is a RISC-V powered IMU evaluation board

RISC-V Engine Emulator

Stuff related to RISC-V

HiFive01-RevB is the SiFive's RISC-V based board

Development of some Risc-V drivers for the FE310-G002 (SoC)

Bare Bones OSDev template for the HiFive-1 RISC-V board from SiFive!

Play and learn with the SiFive HiFive1 board featuring a FE310-G000 SoC integrating SiFive's E31 RISC-V core.

A custom development board for the SiFive FE310, a RISC-V microcontroller.

Board files for the sifive/freedom git to support other fpga plattforms

Bare metal programming on the RED-V Thing Plus board (SiFive RISC-V FE310 SoC)

OSdev exploration

Read and write a memory-mapped SiFive system-on-chip UART

SiFive's Freedom e300 for the DECA Max10 FPGA

RISCV port of the Slackware distribution

Archived, please use official SiFive dev/platform

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

RISC-V Debugger

SiFive: development platform for PlatformIO