Demo: https://removeif.github.io/removeif-demo hexo-theme

Blog：https://removeif.github.io source code, modify from hexo-theme-icarus, simple and practical. Archieved !

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

A GUI menu inspired by some CS:GO cheats, notably: GameSense/Skeet (but not an exact copy). Early development.

SystemVerilog Logger

Apache 2.0 licensed copy of the Xilinx Unisim library.

A package with useful functions for calibration and reweighting in survey sampling

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

A simple verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

4-bit CPU written in SystemVerilog

BML Markup Language

Go client for Cassandra Sidecar

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

The event display for SBN at Fermilab

A Z80 verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

A simple module to parse https://icarus-icsd.aegean.gr and https://sef.math.aegean.gr websites to get students marks or send requests to office.

Welcome to my blog

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Simple TUI viewer for VCF files. Verilog simulation visualization tool.

我的Hexo博客