SAP 4 bit PC with in-built ALU

Testing area for exploration!

Solutions to the Nand2Tetris course on coursera.

In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.

Repositório destinado às atividades do módulo 11 do curso de Engenharia da Computação.

x8086 graphical implementation for a 16 bit micro processor

My homework for Technoatom C++ course

VHDL Implementation of MIPS's ALU

A simple arithmetic logic unit (ALU) with System verilog

ALU de 8-bit en Verilog

ALU capable of adding, subtracting, multiplying and calculating the remainder of two signed 3-bits numbers.

Simple Implementation of a basic IAS machine in java (includes a sample input)

Ram,Dual Port Ram using Verilog

Logic gates, simplification of Boolean functions, design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters. For non-electrical and non-computer engineering majors only.

Dataset for simulating Arithmetic Logic Unit

A 32-bits ALU implemented in C language

Projects involving FPGA

64-bit Multiplication ALU

Von Neumann Architecture components design.