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RISC-V
The Open-Standard Instruction Set Architecture
- 3.3k followers
- Zurich, CH
- https://riscv.org
- @risc_v
- [email protected]
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- riscv-control-transfer-records Public
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
riscv/riscv-control-transfer-records’s past year of commit activity - riscv-smmtt Public
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
riscv/riscv-smmtt’s past year of commit activity - riscv-cheri Public
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv/riscv-cheri’s past year of commit activity - riscv-cfi Public
This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
riscv/riscv-cfi’s past year of commit activity
