Build for VeriStand 2024 (#64)

Filter out error which occurs with old driver versions (#58)

Use quarterly display version (#56)

Work around issue with DAQmx devices as the master hardware synchroni…

…zation device (#53)

Work around an initialization ordering issue related to the VeriStand engine's usage of DAQmx.

If a DAQmx module is configured as the chassis master hardware synchronization device, a DAQmx timing source is created prior to the custom device engine being launched. If we connect a new source to the 10MHz clock input at that point, we can cause the PLL to lose phase-lock and the timing source to be torn down, resulting in the primary VeriStand timed loop erroring. This issue doesn't always occur, as the new clock is sometimes "close-enough".

By connecting the clock terminals in ActionVIOnDownload, the chassis lock should be disciplined properly by the time a DAQmx timing source is created. We also connect them again in the engine, in case the original configuration failed (e.g. due to missing remote support) or something else went wrong. Double connecting does not cause any issues.

Create stub files for unsupported targets (#52)

Update CODEOWNERS (#40)

Update test config to support ATS hardware (#33)

* Update Pharlap test config file with host name and card identifier

* Modified device name mismatch error test to not override config with valid card name

* Update Linux x64 test config file with host name and card identifier

* Saved modified test VI for LabVIEW 2015

Build nipkg for 32- and 64-bit (#30)

Update nipkg build information with new name and install path (#27)