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Microarchitecture traces of RISC-V cores, for processing with pipeline-viewer

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hm-riscv/microarchtrace

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About

This is a framework for microarchitecture tracing. It allows instructors and learners to run real world processor cores in a simulation and tracing environment that abstracts from design details and captures the relevant microarchitectural details instead.

It uses pipeline-viewer to visualize the microarchitectural details.

Getting started

Clone the repository and the cores:

git clone --recursive https://github.com/hm-riscv/microarchtrace

Install the Python3 prerequisites:

pip3 install -r requirements.txt

You also need to install Verilator and a build environment.

For each core you can find a quick start and potential lab assignments in their respective folder in cores/.

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Microarchitecture traces of RISC-V cores, for processing with pipeline-viewer

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