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Technology LEF files have incorrect CPERSQDIST

Status: Open.

#30 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· RTimothyEdwards opened on Dec 9, 2022

.spice netlist is messed up due to label placement

Status: Open.

#25 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· AL-255 opened on Nov 25, 2022

Gate level verilog modules are horribly broken and unusable

Status: Open.

#24 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· RTimothyEdwards opened on Nov 20, 2022

Missing Resistance for vias in tech lef

Status: Open.

#19 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· kareefardi opened on Sep 4, 2022

Set up readthedocs pull request rendering

Status: Open.

#13 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Aug 10, 2022

Figure out what is going on with the fill schematic rendering

Status: Open.

#12 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Aug 10, 2022

Figure out how to fix the flip flop schematic rendering

Status: Open.

#11 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Aug 10, 2022

Figure out how to fix the buffers schematic rendering

Status: Open.

#10 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Aug 10, 2022

Add verilog test benches for each of the standard cells.

Status: Open.

#4 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Jul 20, 2022

CI should check that the standard cells pass the GF180MCU DRC rules

Status: Open.

#2 In google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0;

· mithro opened on Jul 20, 2022