Add SystemVerilog filetype

Add SystemVerilog filetype and syntax highlighting: - Create SystemVerilog filedefs file, including all the standard keywords from SystemVerilog-2017 (IEEE Std 1800-2017). - Set it to use the existing Verilog lexer and ctags parser (which already supported both Verilog and SystemVerilog). - Create an initial draft for a ctags mapping for SystemVerilog. The ctags parser is currently underutilized, since classes and other SystemVerilog constructs are tagged but not shown in the Symbols panel. These will be added in a future commit.
geany · Nov 18, 2024 · 4ad9085 · 4ad9085
1 parent c043996
commit 4ad9085
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Showing 6 changed files with 95 additions and 3 deletions.
diff --git a/data/Makefile.am b/data/Makefile.am
@@ -77,6 +77,7 @@ filetypes_dist = \
 	filedefs/filetypes.smalltalk \
 	filedefs/filetypes.sql \
 	filedefs/filetypes.Swift.conf \
+	filedefs/filetypes.SystemVerilog.conf \
 	filedefs/filetypes.TypeScript.conf \
 	filedefs/filetypes.tcl \
 	filedefs/filetypes.txt2tags \

diff --git a/data/filedefs/filetypes.SystemVerilog.conf b/data/filedefs/filetypes.SystemVerilog.conf
@@ -0,0 +1,45 @@
+# For complete documentation of this file, please see Geany's main documentation
+[styling=Verilog]
+
+[keywords]
+# all items must be in one line
+word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof bit break buf bufif0 bufif1 byte case casex casez cell chandle checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign  default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endspecify endsequence endtable endtask enum event eventually expect export extends extern final first_match for force foreach forever fork  forkjoin function generate genvar global highz0 highz1 if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inout input inside instance int integer interconnect interface intersect join join_any join_none large let liblist library local localparam logic longint macromodule matches medium  modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or output package packed parameter pmos posedge primitive priority program property protected pull0 pull1 pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos real realtime ref reg  reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with scalared sequence shortint shortreal showcancelled signed small soft solve specify specparam static string strong strong0 strong1 struct super supply0 supply1 sync_accept_on sync_reject_on table tagged task this throughout  time timeprecision timeunit tran tranif0 tranif1 tri tri0 tri1 triand trior trireg type typedef union unique unique0 unsigned until until_with untyped use uwire var vectored virtual void wait wait_order wand weak weak0 weak1 while wildcard wire with within wor xnor xor
+word2=$finish $exit $stop  $realtime $time $stime  $printtimescale $timeformat  $bitstoreal $bitstoshortreal $itor $signed $cast $realtobits $shortrealtobits $rtoi $unsigned  $bits $typename $isunbounded  $unpacked_dimensions $left $low $increment $dimensions $right $high $size  $clog2 $ln $log10 $exp $sqrt $pow $floor $ceil $sin $cos $tan $asin $acos $atan $atan2 $hypot $sinh $cosh $tanh $asinh $acosh $atanh  $countbits $onehot $isunknown $countones $onehot0  $fatal $warning $error $info  $fatal $warning $error $info  $asserton $assertkill $assertpasson $assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff $assertfailoff $assertvacuousoff  $sampled $fell $changed $past_gclk $fell_gclk $changed_gclk $rising_gclk $steady_gclk $rose $stable $past $rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk  $coverage_control $coverage_get $coverage_save $set_coverage_db_name $coverage_get_max $coverage_merge $get_coverage $load_coverage_db  $random $dist_erlang $dist_normal $dist_t $dist_chi_square $dist_exponential $dist_poisson $dist_uniform  $q_initialize $q_remove $q_exam $q_add $q_full  $async$and$array $async$nand$array $async$or$array $async$nor$array $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane  $system
+word3=
+docComment=
+
+[settings]
+lexer_filetype=Verilog
+tag_parser=SystemVerilog
+
+# default extension used when saving files
+extension=sv
+
+# MIME type
+mime_type=text/x-systemverilog
+
+# these characters define word boundaries when making selections and searching
+# using word matching options
+#wordchars=_$abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
+
+# single comments, like # in this file
+comment_single=//
+# multiline comments
+comment_open=/*
+comment_close=*/
+
+# set to false if a comment character/string should start at column 0 of a line, true uses any
+# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d
+# 		#command_example();
+# setting to false would generate this
+# #		command_example();
+# This setting works only for single line comments
+comment_use_indent=true
+
+# context action command (please see Geany's main documentation for details)
+context_action_cmd=
+
+[indentation]
+#width=4
+# 0 is spaces, 1 is tabs, 2 is tab & spaces
+#type=1
diff --git a/data/filetype_extensions.conf b/data/filetype_extensions.conf
@@ -76,11 +76,12 @@ Sh=*.sh;configure;configure.in;configure.in.in;configure.ac;*.ksh;*.mksh;*.zsh;*
 Smalltalk=*.st;
 SQL=*.sql;
 Swift=*.swift;
+SystemVerilog=*.sv;*.svh;
 Tcl=*.tcl;*.tk;*.wish;*.exp;
 Txt2tags=*.t2t;
 TypeScript=*.ts;*.cts;*.mts;*.tsx;
 Vala=*.vala;*.vapi;
-Verilog=*.v;
+Verilog=*.v;*.vh;
 VHDL=*.vhd;*.vhdl;
 XML=*.xml;*.sgml;*.xsl;*.xslt;*.xsd;*.xhtml;*.xul;*.dtd;*.xtpl;*.mml;*.mathml;
 YAML=*.yaml;*.yml;
@@ -90,7 +91,7 @@ None=*;
 
 # Note: restarting is required after editing groups
 [Groups]
-Programming=Arduino;Clojure;CUDA;Cython;Genie;Groovy;Kotlin;Scala;Swift;
+Programming=Arduino;Clojure;CUDA;Cython;Genie;Groovy;Kotlin;Scala;Swift;SystemVerilog;
 Script=Dockerfile;Graphviz;TypeScript;Meson;
 Markup=
 Misc=JSON;

diff --git a/src/tagmanager/tm_parser.c b/src/tagmanager/tm_parser.c
@@ -788,6 +788,47 @@ static TMParserMapGroup group_VERILOG[] = {
 	{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
 };
 
+static TMParserMapEntry map_SYSVERILOG[] = {
+	// Verilog and SystemVerilog
+	{'c', tm_tag_variable_t},  // constant
+	{'d', tm_tag_variable_t},  // define
+	{'e', tm_tag_typedef_t},   // event
+	{'f', tm_tag_function_t},  // function
+	{'m', tm_tag_class_t},     // module
+	{'n', tm_tag_variable_t},  // net
+	{'p', tm_tag_variable_t},  // port
+	{'r', tm_tag_variable_t},  // register
+	{'t', tm_tag_function_t},  // task
+	{'b', tm_tag_undef_t},     // block
+	{'i', tm_tag_undef_t},     // instance
+	// SystemVerilog only (currently unused)
+	{'A', tm_tag_undef_t},     // assert
+	{'C', tm_tag_undef_t},     // class
+	{'V', tm_tag_undef_t},     // covergroup
+	{'E', tm_tag_undef_t},     // enum
+	{'I', tm_tag_undef_t},     // interface
+	{'M', tm_tag_undef_t},     // modport
+	{'K', tm_tag_undef_t},     // package
+	{'P', tm_tag_undef_t},     // program
+	{'Q', tm_tag_undef_t},     // prototype
+	{'R', tm_tag_undef_t},     // property
+	{'S', tm_tag_undef_t},     // struct
+	{'T', tm_tag_undef_t},     // typedef
+	{'H', tm_tag_undef_t},     // checker
+	{'L', tm_tag_undef_t},     // clocking
+	{'q', tm_tag_undef_t},     // sequence
+	{'w', tm_tag_undef_t},     // member
+	{'l', tm_tag_undef_t},     // ifclass
+	{'O', tm_tag_undef_t},     // constraint
+	{'N', tm_tag_undef_t},     // nettype
+};
+static TMParserMapGroup group_SYSVERILOG[] = {
+	{N_("Events"), TM_ICON_MACRO, tm_tag_typedef_t},
+	{N_("Modules"), TM_ICON_CLASS, tm_tag_class_t},
+	{N_("Functions / Tasks"), TM_ICON_METHOD, tm_tag_function_t},
+	{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
+};
+
 static TMParserMapEntry map_R[] = {
 	{'f', tm_tag_function_t},  // function
 	{'l', tm_tag_other_t},     // library
@@ -1280,6 +1321,7 @@ static TMParserMap parser_map[] = {
 	MAP_ENTRY(LDSCRIPT),
 	MAP_ENTRY(FORTH),
 	MAP_ENTRY(MESON),
+	MAP_ENTRY(SYSVERILOG),
 };
 /* make sure the parser map is consistent and complete */
 G_STATIC_ASSERT(G_N_ELEMENTS(parser_map) == TM_PARSER_COUNT);
@@ -1811,6 +1853,7 @@ gboolean tm_parser_has_full_scope(TMParserType lang)
 		case TM_PARSER_VALA:
 		case TM_PARSER_VHDL:
 		case TM_PARSER_VERILOG:
+		case TM_PARSER_SYSVERILOG:
 		case TM_PARSER_ZEPHIR:
 		case TM_PARSER_AUTOIT:
 			return TRUE;

diff --git a/src/tagmanager/tm_parser.h b/src/tagmanager/tm_parser.h
@@ -144,6 +144,7 @@ enum
 	TM_PARSER_LDSCRIPT,
 	TM_PARSER_FORTH,
 	TM_PARSER_MESON,
+	TM_PARSER_SYSVERILOG,
 	TM_PARSER_COUNT
 };
 

diff --git a/src/tagmanager/tm_parsers.h b/src/tagmanager/tm_parsers.h
@@ -78,6 +78,7 @@
 	OcamlParser, \
 	LdScriptParser, \
 	ForthParser, \
-	MesonParser
+	MesonParser, \
+	SystemVerilogParser
 
 #endif