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1. Solving-SAT-in-FPGA-UCSB Solving-SAT-in-FPGA-UCSB Public

   Creating a hardware solver in Verilog and then uploading to FPGA and connecting to a PC to solve SAT problems.

   Jupyter Notebook 3 4

2. RISCVFall2024 RISCVFall2024 Public

   RISC V Processor RTL code and Cadence Files

   SystemVerilog

3. microwalksat microwalksat Public

   microwalksat

   C 1

4. learnverilog.v learnverilog.v Public

   A verilog file containing all of the verilog syntax and common expressions.

   Verilog 3

5. juniper juniper Public

   Jupyter Notebook

6. learnvhdl.vhd learnvhdl.vhd Public

   All of VHDL syntax

   VHDL