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Please switch from setup-ghdl-ci to setup-ghdl

bugSomething isn't workingSomething isn't working

Status: Open.

#291 In abs-tudelft/fletcher;

· Paebbels opened on Jan 12, 2025

Remove REG_WIDTH from AxiTop

fletchgenFletchgen related issueFletchgen related issue

Status: Open.

#266 In abs-tudelft/fletcher;

· johanpel opened on Jan 11, 2021

Mismatch between bus address width and addresses passed through vhdmmio

bugSomething isn't workingSomething isn't working

fletchgenFletchgen related issueFletchgen related issue

Status: Open.

#243 In abs-tudelft/fletcher;

· johanpel opened on Sep 28, 2020

Use an existing standard for start/stop/reset MMIO control registers

enhancementNew feature or requestNew feature or request

Status: Open.

#193 In abs-tudelft/fletcher;

· jvanstraten opened on Sep 24, 2019

AXI read/write converter broken when slices depth > 0

bugSomething isn't workingSomething isn't working

lang:vhdlVHDL related issueVHDL related issue

Status: Open.

#164 In abs-tudelft/fletcher;

· johanpel opened on Jul 18, 2019

Wrap AxiTop into an AxiTopSim for simulation

enhancementNew feature or requestNew feature or request

fletchgenFletchgen related issueFletchgen related issue

Status: Open.

#135 In abs-tudelft/fletcher;

· johanpel opened on Jun 27, 2019

Prevent ambiguity among Arrow data stream signals

hardwareHardware related issueHardware related issue

Status: Open.

#123 In abs-tudelft/fletcher;

· johanpel opened on Jun 6, 2019

Multi-clock domain support incomplete

enhancementNew feature or requestNew feature or request

hardwareHardware related issueHardware related issue

Status: Open.

#93 In abs-tudelft/fletcher;

· jvanstraten opened on Dec 6, 2018

Arrow implicit null bitmap is not propagated during run time

enhancementNew feature or requestNew feature or request

hardwareHardware related issueHardware related issue

runtimeRuntime related issueRuntime related issue

Status: Open.

#66 In abs-tudelft/fletcher;

· johanpel opened on Oct 15, 2018