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Insights: Xilinx/llvm-aie
Overview
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0 Active issues
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- 3 Merged pull requests
- 0 Open pull requests
- 0 Closed issues
- 0 New issues
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3 Pull requests merged by 1 person
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Implement a mechanism to disable GEP->PHI InstCombiner.
#231 merged
Dec 3, 2024 -
[AIEX] Shift G_CONCAT_VECTORS closer to the user
#234 merged
Nov 28, 2024 -
[AIE2] Enable up-combining for VLD + UNPACK
#241 merged
Nov 27, 2024
9 Unresolved conversations
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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Martien.exhaustiveswp
#242 commented on
Dec 3, 2024 • 16 new comments -
Rename GPR Register in innermost loop body
#245 commented on
Dec 3, 2024 • 13 new comments -
Convert Loop Metadata to Asserts to help Loop rotation
#227 commented on
Dec 3, 2024 • 11 new comments -
Support for allowing direct VEXTRACT to 20-bit registers
#233 commented on
Nov 28, 2024 • 1 new comment -
[AIE2] Fix VMOV instruction itinerary
#239 commented on
Dec 3, 2024 • 1 new comment -
[AIE2] Alias Analysis using AddrSpace Info
#173 commented on
Dec 3, 2024 • 0 new comments -
[AIEX] Delay metalizing of multi-slot until iterative scheduling is converged
#182 commented on
Dec 3, 2024 • 0 new comments -
[AIEX] Reschedule multi-slot instruction for better packing/schedule
#217 commented on
Dec 3, 2024 • 0 new comments -
[AIEX] Use delayed MOV when possible
#223 commented on
Dec 3, 2024 • 0 new comments