Created by Van. June 2017

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
8-Bits for each of the 8 Seven-Segment LEDS. (8x8=64)

(Possible future improvements, let user decide desired bit size of msg/key/try, use sixteen-segment LEDs) -64Bit Suspectible to bruteforce attack. -Seven-Segment difficult to express range of alphabets due to multiple overlaps

Device Details:
 Product Category=General Purpose
 Family=Artix-7
 Sub-Family=Artix-7
 Package=CSG324
Speed Grade=-1
 Part=xc7a100tcsg324-1

--------------------Demonstration--------------------
Top Level Architecture/Psuedocode Sketch:

Data Path Architecture Sketch:

ASM Chart Sketch:

Sample Translation Table for In(Alphabet/Space->Decimal->Binary Input)
Space-> 0 ->00000000
A-> 1 -> 00000001
B-> 2 -> 00000010
C-> 3 -> 00000011
...
X-> 24 -> 00011000
Y-> 25 -> 00011001
Z-> 26 -> 00011010

Translation Chart Sketch:

DEMO: