A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

LLM-Aided FPGA Design for Signal Processing Applications

DaCH: dataflow cache for high-level synthesis.

Advanced multi-band GNSS SDR front-end implementation in an RFSoC integrated circuit. GPL-3.0 license

LLM-Aided FPGA Design Optimization

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Mixing HLS and Backend Versions in Vitis

FPGA Acceleration for the LoFreq variant caller

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

Critical bug in AMD/Xilinx Vitis HLS FFT IP (float, pipelined streaming)

Xilinx Tools Tutorials

Vitis (Vivado) HLS Examples

Valuation of financial derivatives on FPGA with HLS. We introduce a new path pricer for computing the replication error of delta-hedging strategy with monte carlo methods using the Vitis Quantitative Finance Library.

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs

FPGA SpMV (CSR/ELL/COO) with Vitis HLS + Vivado on HyperFPGA. Includes HLS IP, block designs, and host scripts. Replicate any method via SpMV_FinalSourceFiles.

Work on your Vitis HLS project from within VS Code

Radar Signal Processing on Zynq SoCs for Doppler Estimation

An accelerated implementation of the kNN algorithm on the Kria KV260 FPGA