Digital Logic Design

Slaw hawreyan chonn

Flip-Flop and Related Devices

Supas bashin
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R S
Q Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R S
Q Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
0
1
is applied to the S input while the R Q
0 S
remains LOW.
0 R 1
0
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
1
0
Q
0 S
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1
0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 1
0
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 1
0
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 1
0
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 1
0
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 1 SET
0
Q
reset at the same time (invalid). 1R
Logic Symbols
(2)
1S1 The active-LOW S-R latch is
(3) (4) 1Q
(1)
1S2 available as the 74LS279A IC.
1R
(6)
2S It features four internal latches with
(7) 2Q
(5) two having two S inputs. To SET any
2R
(11)
of the latches, the S line is pulsed low.
(12)
3S1
(9) 3Q
It is available in several packages.
3S2
(10) S-R latches are frequently used for
3R
(15) switch debounce circuits as shown:
4S (13)
(14) 4Q
4R
VCC
74LS279A

2 S Q
S
R R Position Position
1 1 to 2 2 to 1
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
D latch
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.
D latch
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.

D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments

1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

Edge-triggered flip-flop logic symbols
Positive edge-triggered S-
R flip-flop
Positive edge-triggered S-
R flip-flop

Truth Table
Edge triggered S-R Flip-Flop output
Positive edge-triggered D
flip-flop
Positive edge triggered D-type Flip-Flop
The J-K flip-flop is more versatile than the D flip flop. In addition to
the clock input, it has two inputs, labeled J and K. When both J and K
= 1, the output changes states (toggles) on the active clock edge (in
this case, the rising edge).
Inputs Outputs
J K CLK Q Q Comments

0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle
Positive edge triggered J-K Flip-Flop in action
Negative edge triggered J-K Flip-Flop in action
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters
(Chapter 8).
D Q

For example, if Q is LOW, Q is CLK CLK

HIGH and the flip-flop will toggle
on the next clock edge. Because the Q
flip-flop only changes on the active
edge, the output will only change
once for each clock pulse.
D flip-flop hardwired for
a toggle mode
Asynchronous preset & clear
inputs
Synchronous inputs are transferred in the
triggering edge of the clock (for example the D or
J-K inputs). Most flip-flops have other inputs that
are asynchronous, meaning they affect the output
independent of the clock.
Two such inputs are
normally labeled preset
(PRE) and clear (CLR).
These inputs are usually
active LOW. A J-K flip flop
with active LOW preset and
CLR is shown.
J-K Flip-Flop with PRESET and CLEAR
Flip-Flop As a Storage device
Principal flip-flop
applications are for
temporary data storage, as
frequency dividers, and in
counters (which are covered
in detail in Chapter 8).
Typically, for data storage
applications, a group of flip-
flops are connected to
parallel data lines and
clocked together. Data is
stored until the next clock
pulse.

Parallel Data Storage

Flip-Flop As a Frequency Divider

For frequency division, it is

simple to use a flip-flop in the
toggle mode or to chain a series of
toggle flip flops to continue to
divide by two.
One flip-flop will divide fin by 2,
two flip-flops will divide fin by 4
(and so on). A side benefit of
frequency division is that the
output has an exact 50% duty
cycle.
JK FF as divide by two.
Flip-Flop As a Frequency Divider

JK FFs as divide by four.

Frequency division
Binary counting sequence
3-bit Binary Counter
The 555 timer
The pulse width is determined by R1C1 and is
approximately tW = 1.1R1C1.
+VCC

(4) (8)
R1
(7) RESET VCC
DISCH
(6) (3)
The trigger is a THRES OUT
negative-going (2) (5) tW = 1.1R1C1
TRIG CONT
pulse. GND
C1 (1)
Example
Determine the pulse width for the circuit
shown.
tW = 1.1R1C1 = 1.1(10 kW)(2.2 mF) = 24.2 ms
+VCC
+15 V

(4) (8)
R1
10 kW (7) RESET VCC
DISCH
(6) (3)
THRES OUT
(2) (5) tW = 1.1R1C1
TRIG CONT
C1 GND
(1)
2.2 mF
Project
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37
References
1. T. Floyd, “Digital Fundamental”, 10th Ed., USA:
PrenticeHall, 2008
2. R.J. Tocci, “Digital Systems: Principles and
Applications”, 10th Ed., USA: Prentice-Hall, 2006
3. W. Kleitz, “Digital Electronics: A Practical
Approach”, 8th Ed., USA: Prentice-Hall, 2007
4. Begnell and Donovan, “Digital Electronics”, 5th
Ed., USA: Delmar Thomson Learning, 2006