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Chapter 5 Internal Memory
William Stallings, Computer Organization and Architecture, 9 th Edition
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Objectives
How are main memory structured?
Whether main memory may cause errors?
How many types of memory?
After studying this chapter, you should be able to:
Present an overview of the principle types of
semiconductor main memory.
Understand the operation of a basic code that can detect
and correct singlebit errors in 8-bit words.
Summarize the properties of contemporary advanced
DRAM organizations.
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Contents
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 Advanced Dram Organization
Semiconductor- Chất bán dẫn (silic, germanium) là vật liệu
trung gian giữa chất dẫn điện và chất cách điện. Chất bán dẫn chỉ
hoạt động như một chất dẫn điện ở một điều kiện nào đó. Chất
bán dẫn được dùng để tạo ra các transistor (transfer-resistor).
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5.1- Semiconductor Main Memory
Organization
Semiconductor Memory Types
Dynamic RAM and Static RAM
Types of ROM
Chip Logic
Chip Packaging
Module Organization
Interleaved Memory
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Organization
Basic element of a semiconductor memory is the
memory cell.
Cell properties:
1-They exhibit two stable (or semistable) states, which
can be used to represent binary 1 and 0.
2- They are capable of being written into (at least once),
to set the state.
3- They are capable of being read to sense the state
Semiconductor Memory Types
All of the memory types that we will explore in this chapter are
random access. That is, individual words of memory are directly
accessed through wired-in addressing logic.
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Dynamic RAM (DRAM)
RAM technology is divided into two technologies:
Dynamic RAM (DRAM)
Static RAM (SRAM)
How Dram cell works? Read by yourself.
DRAM
Made with cells that store data as charge on capacitors (tụ điện)
Presence or absence of charge in a capacitor is interpreted as a binary 1 or
0
Requires periodic charge refreshing to maintain data storage
The term dynamic refers to tendency of the stored charge to leak away,
even with power continuously applied
+ Static RAM
(SRAM)
Digital device that uses the same logic
elements used in the processor
Binary values are stored using
traditional flip-flop logic gate
configurations
Will hold its data as long as power is
supplied to it
SRAM versus DRAM
SRAM
Both volatile: Power must be continuously supplied to the
memory to preserve the bit values
Dynamic cell
Simpler to build, smaller
(smaller cells = more cells per unit area) DRAM
Less expensive
Requires the supporting refresh circuitry
Tend to be favored for large memory requirements
+ Used for main memory
Static
Faster
Used for cache memory (both on and off chip)
+ Read Only Memory (ROM)
Contains
a permanent pattern of data that cannot be
changed or added to
No
power source is required to maintain the bit values in
memory
Dataor program is permanently in main memory and
never needs to be loaded from a secondary storage device
Data is actually wired into the chip as part of the
fabrication process
Disadvantages of this:
No room for error, if one bit is wrong the whole batch of ROMs
must be thrown out
Data insertion step includes a relatively large fixed cost
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Programmable ROM (PROM)
Less expensive alternative
Nonvolatile and may be written into only once
Writing process is performed electrically and may be
performed by supplier or customer at a time later than the
original chip fabrication
Special equipment is required for the writing process
Provides flexibility and convenience
Attractive for high volume production runs
Read-Mostly Memory
Flash
EPROM EEPROM
Memory
Electrically erasable Intermediate between EPROM
Erasable programmable read- programmable read-only memory and EEPROM in both cost and
only memory
functionality
Can be written into at any time
without erasing prior contents
Uses an electrical erasing
Erasure process can be
technology, does not provide byte-
performed repeatedly
level erasure
Combines the advantage of non-
volatility with the flexibility of
being updatable in place
More expensive than PROM but Microchip is organized so that a
it has the advantage of the section of memory cells are erased
multiple update capability More expensive than EPROM in a single action or “flash”
Typical 16 Mb DRAM (4M x 4)
MUltipleXer is a device that selects one of several input
signals and forwards the selected input into a single line
Address lines
Data lines
Chip Packaging
MAR
Figure 5.5
256-KByte
Memory
Organization
+ 1chip: 512*512= 218 bits
=256kb
8 chips 256KB
( 8bits/word)
1MByte Module Organization
Select column
Select row
Data
Enable buffer
E: enable, signal permits the chip operating or not
Interleaved Memory
Composed of a collection of
DRAM chips
Grouped together to form a
memory bank
Each bank is independently
able to service a memory read
or write request
K banks can service K requests
simultaneously, increasing memory
read or write rates by a factor of K
If consecutive words of memory are
stored in different banks, the transfer
of a block of memory is speeded up
+ 5.2- Error Correction
Hard Failure
Permanent physical defect (khuyết tật).
Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or
switch erratically between 0 and 1
Can be caused by:
Harsh (khắc nghiệt) environmental abuse(sự ngược đãi)
Manufacturing defects
Wear (hao mòn)
Soft Error
Random, non-destructive event that alters the contents of one or more memory cells
No permanent damage to memory
Can be caused by:
Power supply problems Alpha particles: Phenomenon in which 2
protons and 2 neutrons bound together into a
Alpha particles particle identical to a helium nucleus (Wiki for
more details).
Error Correcting Code (ECC) Function
No error/Correctable
bits
Read
Write M+K
• No errors are detected. The fetched data bits are sent out.
• An error is detected, and it is possible to correct the error. The data bits plus error
correction bits are fed into a corrector, which produces a corrected set of M bits to
be sent out.
• An error is detected, but it is not possible to correct it. This condition is reported.
Next slide: An example for ECC function.
ECC Function: Examples
• The XOR operation is ussually used in ECC functions
• The most simple data for checking is the original data A copy of
original data is written to memory . 8-bit data: 00001111, ECC
data: 00001111 Memory must be increased to double size
• XORs some bits of M-bit original data to K-bit ECC will decrease
memory size.
• Examples:
8 bits 3 bits: 01010110 101
8 bits 2 bits: 01010110 00
8 bits 1 bits: 01010110 0
- Main memory bank usually includes 9 chips. Why?
+ Hamming Data: 4 bits
1 XOR 1 XOR 1 = 1
Error
Correcting
Code
Richard Hamming at
Bell Laboratories
Parity bit (P) =1 if
number of 1s is odd.
Based on parity bit,
data can be corrected.
01
+ Increase in Word Length with ECC
Data 4 bits (22) At least 3 bit ECC (2+1)
Data 8 bits (23) At least 4 bit ECC (3+1)
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Layout of Data Bits and Check Bits
Check positions: 23 22 21 20
(Algorithm for computing Ci bit is pre-defined)
Check Bit Calculation
Error
ECC write: 0111
ECC read: 0001
0111 XOR 0001 != 0 Error
+ Hamming SEC-DED Code
Single-Error Correcting/Double-Error Detecting
The sequence
shows that if
two errors occur
(Figure 5.11c),
the checking
procedure
goes astray –
chệch hướng (d)
and worsens the
problem by
creating a third
error (e).
To overcome the problem, an eighth bit is added that is set so that the total number of
1s in the diagram is even. The extra parity bit catches the error (f).
Table 5.3
Performance Comparison
DRAM Alternatives
Table 5.3 Performance Comparison of Some DRAM Alternatives
5.3- Advanced DRAM Organization
SDRAM
One of the most critical system bottlenecks when
using high-performance processors is the interface to
main internal memory
DDR-DRAM
The traditional DRAM chip is constrained both by its
internal architecture and by its interface to the
processor’s memory bus
A number of enhancements to the basic DRAM
architecture have been explored: RDRAM
Table 5.3 Performance Comparison of Some DRAM Alternatives
Synchronous DRAM (SDRAM)
One of the most widely used forms of DRAM
Exchanges data with the processor synchronized to an external clock signal
and running at the full speed of the processor/memory bus without imposing
wait states
With synchronous access the DRAM moves data in and out under control of
the system clock
• The processor or other master issues the instruction and address information which
is latched by the DRAM
• The DRAM then responds after a set number of clock cycles
• Meanwhile the master can safely do other tasks while the SDRAM is processing
SDRAM
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SDRAM Pin Assignments
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SDRAM Read Timing
RDRAM Developed by
Rambus
Rambus Dynamic Random Access Memory
Bus delivers address and control
information using an asynchronous
block-oriented protocol Adopted by Intel
Gets a memory request over the
high-speed bus for its Pentium and
Request contains the desired
address, the type of operation, Itanium processors
and the number of bytes in the
operation
Protocol: pre-defined rule
Bus can address up
Has become the
to 320 RDRAM
main competitor to
chips and is rated
SDRAM
at 1.6 GBps
Chips are vertical packages with
all pins on one side
Exchanges data with the
processor over 28 wires no
more than 12 centimeters long
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RDRAM Structure
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Double Data Rate SDRAM
(DDR SDRAM)
SDRAM can only send data once per bus clock cycle
Double-data-rate SDRAM can send data twice per clock cycle, once
on the rising edge of the clock pulse and once on the falling edge
Developed by the JEDEC Solid State Technology Association
(Electronic Industries Alliance’s semiconductor-engineering-
standardization body)
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DDR SDRAM
Read
Timing
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Cache DRAM (CDRAM)
Developed by Mitsubishi
Integrates a small SRAM cache onto a generic DRAM chip
SRAM on the CDRAM can be used in two ways:
It can be used as a true cache consisting of a number of 64-bit lines
Cache mode of the CDRAM is effective for ordinary random access to
memory
Can also be used as a buffer to support the serial access of a block of data
+ Exercises
5.1 What are the key properties of semiconductor memory?
5.2 What are two interpretations of the term random-access memory?
5.3 What is the difference between DRAM and SRAM in terms of application?
5.4 What is the difference between DRAM and SRAM in terms of characteristics such
as speed, size, and cost?
5.5 Explain why one type of RAM is considered to be analog and the other digital.
5.6 What are some applications for ROM?
5.7 What are the differences among EPROM, EEPROM, and flash memory?
5.8 Explain the function of each pin in Figure 5.4b. 182 CHAPTER 5 / INTERNAL
MEMORY
5.9 What is a parity bit?
5.10 How is the syndrome for the Hamming code interpreted?
5.11 How does SDRAM differ from ordinary DRAM?
+ Summary Internal
Memory
Chapter 5
Semiconductor main memory
Hamming code
Organization
DRAM and SRAM Advanced DRAM organization
Types of ROM Synchronous DRAM
Chip logic Rambus DRAM
Chip packaging DDR SDRAM
Module organization Cache DRAM
Interleaved memory
Error correction
Hard failure
Soft error
