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    Microprocessor DMA

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    vivek_may12
    The document discusses Direct Memory Access (DMA) and the 8237 DMA controller chip. It describes how DMA allows high-speed transfer of data between memory and peripherals by bypassing the CPU. The 8237 controller has 4 independent channels that can each transfer 64KB of data. It interfaces with the CPU using HOLD/HLDA signals and can generate addresses and control read/write signals to directly access memory without CPU involvement. Programming involves setting up the transfer parameters in the controller's channel registers before it initiates transfers autonomously in response to device requests.

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    © All Rights Reserved
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    Microprocessor DMA

    Uploaded by

    vivek_may12
    120 views14 pages
    The document discusses Direct Memory Access (DMA) and the 8237 DMA controller chip. It describes how DMA allows high-speed transfer of data between memory and peripherals by bypassing the CPU. The 8237 controller has 4 independent channels that can each transfer 64KB of data. It interfaces with the CPU using HOLD/HLDA signals and can generate addresses and control read/write signals to directly access memory without CPU involvement. Programming involves setting up the transfer parameters in the controller's channel registers before it initiates transfers autonomously in response to device requests.

    Original Description:

    The presentation details about interfacing DMA to 8085 microprocessor.

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    © © All Rights Reserved

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    The document discusses Direct Memory Access (DMA) and the 8237 DMA controller chip. It describes how DMA allows high-speed transfer of data between memory and peripherals by bypassing the CPU. The 8237 controller has 4 independent channels that can each transfer 64KB of data. It interfaces with the CPU using HOLD/HLDA signals and can generate addresses and control read/write signals to directly access memory without CPU involvement. Programming involves setting up the transfer parameters in the controller's channel registers before it initiates transfers autonomously in response to device requests.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    120 views14 pages

    Microprocessor DMA

    Uploaded by

    vivek_may12
    The document discusses Direct Memory Access (DMA) and the 8237 DMA controller chip. It describes how DMA allows high-speed transfer of data between memory and peripherals by bypassing the CPU. The 8237 controller has 4 independent channels that can each transfer 64KB of data. It interfaces with the CPU using HOLD/HLDA signals and can generate addresses and control read/write signals to directly access memory without CPU involvement. Programming involves setting up the transfer parameters in the controller's channel registers before it initiates transfers autonomously in response to device requests.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 14

    Direct Memory Access (DMA)

    8237 DMA Controller


    DMA
    • DMA is an I/O technique used for High-speed data transfer
    – e.g. between system memory and a floppy disk
    • Data transfer through microprocessor using status check I/O
    or interrupt I/O is relatively slow because each instruction
    needs to be fetched and executed.
    • In DMA, MPU releases the control of the buses to DMA
    controller .
    • DMA controller manages data transfer between memory and
    a peripheral and thus bypassing the MPU.
    DMA
    • DMA makes use of two signals on 8085 HOLD and HLDA
    • HOLD:
    – Active high Input signal to 8085 from DMA requesting the use of
    address and data busses.
    – On receiving HOLD request-> MPU completes present M/c cycle -> All
    buses are tristated (high Impedance state) -> relinquish bus -> issue
    Hold Acknowledge (HLDA) signal.
    – MPU regains control of the buses after HOLD goes low.
    • HLDA (Hold Acknowledge):
    – Active high output signal indicating that MPU is relinquishing control
    of the buses.
    DMA
    • DMA first communicates with the MPU as a peripheral and
    subsequently gains control of the buses and plays the role of
    processor for data transfer.
    • To complete data transfer DMA should have
    – Data bus
    – Address bus
    – Read/Write control Signals
    – Control Signals (to switch role as peripheral and master unit)
    8237 DMA Controller
    • 8237 is programmable 40 Pin IC
    • 4 independent channels each capable of transferring 64K byte
    • Discussing on DMA is divided into five sections
    1. DMA Channels and Interfacing
    2. DMA signals
    3. System Interface
    4. Programming
    5. DMA Execution
    1. DMA Channels and Interfacing
    • 8237 has four channels CH0
    to CH3 •
    • Each channel has 2-16 bit
    registers
    – Starting address (16 bit)
    – Count (216 = 64 K) No of bytes
    – 8 such registers for 4 channels
    – A0 – A3 = 0000b CH0 MAR
    – A0 – A3 = 0001b CH0 Count
    • Last 8 registers are used to
    write commands or read
    status
    • Addr of reg range from 00H
    to 0FH using CS signal.
    2. DMA Signals
    • Signals are divided into two
    groups Left (MPU) and right •
    (peripheral)
    • DREQ0-DREQ3 – DMA
    Request: 4x, Input to DMA from
    peripheral to obtain DMA
    services.
    • DACK0-DACK3 – DMA Ackn:
    Output to inform peripheral of
    DMA is granted
    • AEN and ADSTB – Addr
    Enable & Addr Strobe: active
    high, used to latch high order
    addr byte.
    2. DMA Signals
    • Signals are divided into two
    groups Left (MPU) and right •
    (peripheral)
    • MEMR and MEMW –
    Memory read and memory
    write: Read and write from
    memory
    • A0–A3 & A4–A7: A0 – A3 are
    bidirectional – Access registers
    and generate low-order address
    • HRQ and HLDA: Hold Request
    and Hold Acknowledge. HRQ
    output to MPU (HOLD) and MPU
    issues HLDA.
    3. System Interface
    • DMA has 8 address lines.
    • To access 64K bytes, 16
    address lines are required.
    • DMA place low-order byte
    on addr bus high-order byte
    on the data bus and asserts
    AEN (Address Enable) and
    ADSTB signals.
    • Latch high order byte from
    data bus & make 16bit addr
    • After the transfer of first
    byte latch is updated when
    the lower byte generates a
    carry.
    4. Programming 8237
    • To implement the DMA
    transfer 8237 should be •
    configured by writing into
    Control Registers
    1. Write control word (CW) in
    Mode register 0B that select
    channel and transfer type
    2. CW in command register 08 –
    channel priority, enable 8237
    3. Write Starting addr of data
    block in channel MAR.
    4. Write the count of data in
    channel Count reg.
    4. Programming 8237
    • Example:
    •
    1. Disable the DMA controller
    and write initialization
    instructions
    2. Initialize CH3 to transfer 1K
    of byte from the system
    memory to the floppy disk
    assigned to CH3
    4. Programm
    ing 8237 •
    5. DMA Execution
    • Data transfer through DMA – Slave Mode and Master Mode
    • Slave Mode: DMA controller is treated as peripheral
    1. MPU selects the DMA controller through CS
    2. MPU writes the control word in Channel Register and
    Command Register by using control signals IOW and IOR
    3. Output signals of 8237 such as A4 – A7, MEMW & MEMR are
    in tri-state (High Impedance).
    5. DMA Execution
    • Data transfer through DMA – Slave Mode and Master Mode
    • Master Mode: After initialization DMA controller keeps checking for
    DMA request
    1. Peripheral sends high DRQ
    2. On receiving DRQ, HRQ is issued to 8085
    3. 8085 relinquish buses in next m/c cycle and issue HLDA
    4. Receiving HLDA, DMA asserts AEN signal – disables latch 2
    disconnects A0-A7 of the MPU and enables Latch 1. DMA asserts
    ADSTB and places contents of data bus to A15-A8. DMA also
    outputs low order address A7-A0.
    5. Entier addr is available DMA sends DACK to peripheral
    6. DMA completes data transfer by asserting necessary control
    signals (IOR, IOW, MEMR, MEMW) until DACK remain high.
    7. At the end DMA asserts EOP (End of Process) to inform peripheral
    that data transfer is complete.

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