ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

CMOS VLSI LAB MANUAL

Subject Code : 22ECE61
VI SEMESTER (AY 2024-25)
CMOS VLSI LAB MANUAL
Subject Code : 22ECE61
VI SEMESTER (AY 2024-25)

Faculty Incharge: Ms Vinitha Pasanha

Mr Vijay Ganesh P C
Faculty: Ms Savitha J
Ms Harshada S Katge

Lab Instructor: Ms Divya Prasanna

​ ​ ​ ​ ​ ​ ​ ​
Faculty Incharge Dr Dayakshini
HOD ECE
VISION

●​ "To Excel in Electronics and Communication Engineering Education and Research,

focusing on the needs of Industry and Society, with professional ethics"

MISSION

●​ Provide opportunities to deserving students for quality professional education in the

field of Electronics and Communication Engineering.
●​ Design and deliver curricula to meet the changing needs of industry through student
centric learning methodologies to excel in their profession.
●​ Recruit, Nurture and Retain best faculty and technical manpower.
●​ Consolidate the state-of-art infrastructure and equipment for teaching and research
activities.
●​ Promote all round personality development of the students through interaction with
alumni, academia and Industry.
●​ Strengthen the Educational Social Responsibilities of the Institution.
CMOS VLSI LAB PRACTICAL MODULE
A-Exercise (compulsorily to be conducted using Cadence Design Tools):

1.​ Analysis of ID-VGS and ID-VDS Characteristics of an nMOS Transistor.

2.​ Design of a Resistive Load Inverter and its analysis by simulation.
3.​ Design of a CMOS Inverter and Simulation.
4.​ Noise Margin and Delay Analysis of a CMOS Inverter.
5.​ Design and analysis of CMOS Combinational Circuits -NAND, NOR and Complex
Circuits.
6.​ Layout of a CMOS Inverter.
7.​ Layout of Combinational Circuits.
8.​ Sizing of Combinational Circuits to meet the requirements of a minimum sized
CMOS.
9.​ Verification of Capacitance of a MOS Transistor by simulation.
Analysis of Body Effect on a MOS Transistor.
10.​Analysis of a Pass Transistor and Transmission Gate Logic.
11.​Design and analysis of CMOS D-Flipflop.

B-Open Ended Experiments:

1.​ Design of a Schmitt Trigger

Course Outcomes

Bloom’s Target
CO No. Course Outcomes (COs) Taxonom Attainment
y Level Level
Apply the basic principles of MOS transistors to
22ECE61.1 understand the fabrication process and design the L3 2
layout of CMOS integrated circuits.
22ECE61.2 Analyze the working of a CMOS inverter and L3 2
implement CMOS combinational logic circuits
22ECE61.3 Design CMOS sequential circuits by analysing the L3 2
impact of interconnects and delay effects.
Design and Analyse CMOS combinational circuits
22ECE61.4 and layouts using Electronic Device Automation L3 2
Tools
Evaluate interconnect parameters, delay estimation
22ECE61.5 techniques, and transistor sizing strategies to L3 2
optimize circuit performance using EDA tools.
Design reliable and power-efficient digital circuits
22ECE61.6 using CMOS logic techniques while considering L4 2
real-world constraints.
Experiment No 1: Analysis of ID-VGS and ID-VDS Characteristics of an nMOS
Transistor.
Aim:
Analyse the operation of a NMOS transistor with given specifications, completing the
design flow mentioned below
a) Draw the schematic and verify the following: DC Analysis to plot
​ i. ID-VGS Characteristics
​ ii. ID-VDS Characteristics

Tools required: Cadence, Virtuoso

Procedure:
1.​ Before starting to work on a design, create a Workspace (Folder) for the project individually.

Figure -1.1: Workspace Creation

2.​ Double click on the Student folder and right click and select the option “New Folder”. Rename
the folder with your USN.
Figure -1.2: Name the folder
3.​ Inside the USN folder. Right-click “Open in terminal”.

Figure -1.3: Open in Terminal

4.​ Type the commands:

csh
source /home/install/cshrc
virtuoso
The Virtuoso Log window will open as shown below.

Figure -1.4: Command Interpreter Window (CIW)

●​ In the above window , create your own library by following the steps–Tools→Library
Manager→File→New→Library
●​ In the “New Library” window that opens up, fill in your library name (e.g.: Vgs_Vds), and then click
on the option– ‘Attach to an existing technology library’
●​
Figure -1.5: New library Creation

●​ Choose gpdk180

Figure -1.6: Technology library→gpdk180

●​ The library Manager window appears as shown below and the following selection need to be made to
move to draw schematic. File → New → Cellview (make sure to select the library file created before
choosing).
Figure -1.7: File→New→Cell View
●​ The library file selection window appears as shown below. Make the view as schematic and click
OK.

Figure -1.8: New file creation

●​ The schematic editor window appears as shown below:

Figure -1.9: Virtuoso Schematic editor

●​ Select “Create → Instance” as in Figure 1.10 (or) use the bind key ‘I’ on the keyboard

Figure -1.10: Virtuoso Schematic editor

●​ The “Add Instance” form can be seen as shown in Figure 1.10.

Table – 1: Length and Width of NMOS Transistor
Library Name Cell Name Properties

gpdk180 nmos length, L=180nm, width, WN=2um

●​ Type the parameters and click on ‘Hide’. Device can be seen as shown in the figure1.11 .Make a
leftmouse click to place it on the Schematic Editor.

Figure -1.11: Instance after left mouse click

The remaining devices to be included on the Schematic and its properties are given below in
Table - 2.
Table – 2: Vdc and Gnd pproperties

Library name Cell Name Properties

analogLib Vdc DC voltage = 1.8 V

analogLib Gnd

Figure -1.12: Instantiating vdc

Figure -1.13: Instantiating gnd

Each of the components can be placed by clicking the left mouse button as shown below.

Figure -1.14: All components placed on schematic editor

●​ For connecting the pins and the terminals, click on “Create → Wire” from the top menu (or) use
the bind key ‘W’ (or) the icon from the top menu as shown in Figure.
●​ Use the left mouse click to start / complete the wire from one terminal / pin to another, or click
the bind key ‘S’ on the keyboard to automatically take a connection from the terminal when
approached by the cursor during wire mode.

●​ The final schematic is as shown below in figure 1.15.

Figure -1.15: Complete schematic of NMOS transistor

●​ It is mandatory to save the design before we move ahead to the Simulation and there are two
options, “Save” and “Check and Save”.“Save” option saves the design as it is and “Check and
Save” option checks for discontinuities like floating net or terminal and provides the “error” or
“warning” messages accordingly and then save the design.
●​ To simulate the design and perform the DC Analysis for the NMOS transistor, click on “Launch
→ ADE L” from the top menu of the Test Schematic Cell view .
●​ The “ADE L” window pops up as shown in Figure 1.16
Figure -1.16: ADE L window

●​ To select the analysis required to be performed on the Test Circuit, select “Analyses → Choose”
from the top menu in the ADE L window as shown in Figure.
●​ The “Choose Analyses – ADE L” window pops up as shown in Figure 1.17.

.
Figure -1.17: Analyses→ Choose
●​ To set up a “DC Analysis”, select “dc” and enable “Save DC Operating Point” as shown in Figure
1.18 .

Figure – 1.18: Select “dc”

●​ Enable “Component Parameter”, click on “Select Component” as shown in Figure 1.19 .

Figure – 1.19: Enable “Component parameter”

●​ Select the “vdc”(input) source from the Test Schematic as shown in Figure 1.20 . Since we want
to plot the variation of ID with respect to change in input voltage VGS.

Figure – 1.20: Enable “Component parameter”

●​ Select “DC Voltage” from the list of parameters as shown in the “Select Component Parameter”
window and click on “OK” as shown in Figure 1.20 .
●​ From the “Sweep Range” option, select “Start-Stop” and mention the “Start” value as “0” and
“Stop” value as “1.8”, click on “Apply” and click on “OK” as shown in the Figure 1.21.
Figure – 1.21: Mention the Sweep Range

●​ To select the outputs to be plotted, choose Outputs →To be plotted → Select on Design.
●​ The schematic circuit will appear to choose the Inputs and outputs.
●​ Select the Output Node (Drain terminal) of the NMOS as shown in Figure 1.22. The selected
Node will be listed under “Outputs” in the “ADE L” window as shown in Figure 1.23 . Click on
“OK”.
Figure – 1.22: Select the node

Figure – 1.23: Outputs in ADE L window

●​To run the simulation, click on “Simulation → Netlist and Run” from ADE L window or Click the
icon indicated by arrow as shown in Figure 1.24.

Figure – 1.24: Simulation→Netlist and Run

●​ The simulated waveform can be seen on the “Virtuoso Visualization and Analysis XL” window
as shown in Figure 1.25.
Figure – 1.25: Simulated waveform (ID_VGS)
●​ Repeat the steps from “Choosing Analyses” and now select the “DC Component” as the vdc
connected to the drain terminal to check the variation of ID with respect to change in VDS.
●​ Observe the waveforms on the “Virtuoso Visualization and Analysis XL” window as shown in
Figure 1.26.
Figure – 1.26: Simulated waveform (ID_VDS)
●​ For performing the simulation in steps for different VGS and VDS values, we can follow the
procedure as follows.
●​ Click on the input ”vdc”, Press Q to edit the component parameter. Instead of giving a fixed value
we can give “DC Voltage” as VGS.
●​ Similarly for output “vdc”,”DC Voltage” can be VDS as shown in figure 1.27.
Figure – 1.27: Fixing Vdc voltages as VGS and VDS

●​ Go to Launch → ADE L, Now select Component as “VGS” in DC analysis in order to plot VGS
on the x axis.
●​ Go to Variables → Copy from Cellview. The variables get copied under the tab Design variables
as shown in figure 1.28.
Figure – 1.28: Variables→ Copy from Cellview
●​ Enter the values for both VGS and VDS as 1.8.

Figure – 1.29: Assign VGS and VDS as 1.8

●​ Go to Tools→Parametric Analysis.
●​ Add variable as VGS from the drop down.
●​ Give the range as Start Point is 0 and End Point is 1.8.
●​ Step Mode: Auto.
●​ Total steps:5
●​ Press the green button to “Run the Simulation”.
●​ The simulated ID-VDS characteristics will appear as shown in the figure 1.30.

Figure – 1.30: ID-VDS Characteristics

●​ Repeat the steps by selecting the Component parameter as “VGS” in DC analysis in order
to plot VGS on the x axis.
●​ The simulated ID-VGS characteristics will appear as shown in the figure 1.31.
Figure – 1.31:ID-VGS Characteristics

Observation:
1.​ Identify the threshold voltage in the circuit.
2.​ Change the values of W/L of the transistor and observe the variation in current.
3.​ Identify and note down different regions of operation.
4.​ What is the maximum value of ID observed in the saturation region for a specific gate voltage?
5.​ Based on the above observations, for a digital circuit identify the ideal operating regions?
Experiment 2: Design of a Resistive Load Inverter and its analysis by simulation.
there observable shifts i n the
Aim: Analyse the operation of a Resistive load inverter with given specifications, completing
the design flow mentioned below
a) Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis
​

Figure – 2.1:Resistive Load Inverter Schematic

Procedure
1. Use a load resistor Rload=1kΩ.
2. Input is applied in the form of vpulse inorder to observe the transient response. Parameters for
vpulse and vdc are given Table 3:

Table 3: Properties of Vdc and Vpulse

Library name Cell Name Properties

analogLib Vdc DC voltage = 1.8 V

analogLib Vpulse Voltage 1 = 0 V, Voltage 2 = 1.8 V, Period = 20n s, Rise time

= 1n s, Fall time = 1n s, Pulse width = 10n s
​ 3. To set up a “Transient Analysis”, select “tran”, mention the “Stop Time” (for example: 100n),
select “Accuracy Defaults” (for example: moderate), click on “Apply” and click on “OK” as shown in
Figure 2.2.

Figure – 2.2: Transient analyses parameters

4. The transient response and DC response is in the figure 2.3 and figure 2.4 respectively.
hhhuuu
Figure – 2.3: Transient response

Figure – 2.4: DC response

Observation:
1.​ Note the values of IDS for changing resistance values between (100 Ω to 1.5 K Ω).
2.​ Why the output voltage is not reaching logic 0 (0V)?
3.​ Based on the above observation what is the ideal value of resistor RonL for inverter. Justify
Experiment 3: Design of a CMOS Inverter and Simulation.
Aim:
Design an Inverter with given specifications, completing the design flow mentioned below
a) Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis
Tools required: Cadence, Virtuoso

Procedure:
●​ Create a folder and right click on “Open in terminal”. Type the commands as follows:
csh
source /home/install/cshrc
virtuoso
●​ The Virtuoso Log window will open as shown below.

Figure – 3.1: Command Interpreter Window

●​ In the above window of figure 8, create your own library by following the steps–Tools→Library
Manager→File→New→Library
●​ In the “New Library” window that opens up, fill in your library name (e.g.: mylib), and then click on
the option– ‘Attach to an existing technology library’

Figure – 3.2: File→New→Library

●​ Choose gpdk180

Figure – 3.3: Attach library to Technology library

●​ The library Manager window appears as shown below and the following selection need to be made to
move to draw schematic. File → New → Cellview (make sure to select the library file created before
choosing).

Figure – 3.4: Library Manager window

Figure – 3.5: File → New → Cellview
●​ The library file selection window appears as shown below. Make the view as schematic and click
OK.

Figure – 3.6: New File

●​ The schematic editor window appears as shown below:
Figure – 3.7:Virtuoso Schematic editor
●​ Select “Create → Instance” as in Figure (or) use the bind key ‘I’ on the keyboard

Figure – 3.8:Virtuoso Schematic editor

●​ The “Add Instance” form can be seen as shown in Figure 3.8.

Table – 1: Length and Width of NMOS and PMOS Transistors

Library Name Cell Name Properties

gpdk180 nmos length, L=180nm, width, WN=1um

gpdk180 pmos length, L=180nm, width, WP=2um

●​ Type the parameters and click on ‘Hide’. Device can be seen as shown in the figure 3.9

Figure – 3.9: Create after selection

●​ Make a left mouse click to place it on the Schematic Editor. The device after placement on the
Schematic Editor can be seen as shown in Figure 3.10 . Similarly, other components can be
instantiated.

Figure – 3.10: Instance after left mouse click

●​ To include pins to the schematic, select “Create → Pin” from the top menu (or) use the bind key
‘P’ (or) use the icon from the top menu as shown in Figure 3.11.
Figure – 3.11: Create → Pin

●​ The “Create Pin” window pops up as shown in Figure 3.12.

Figure – 3.12: Create Pin window

●​ Name the pins by separating them with “space”, choose its direction and click on “Hide” as
shown in Figures below.

Figure – 3.13(a): Naming the input pins. Figure – 3.13(b): Naming the output pins.
●​ The pins are visualized on the Schematic Editor as shown in Figure 3.14.

Figure – 3.14: Pins after left mouse click on “Hide”

●​ Place the pins on the Schematic Editor using a left mouse click and the pins after placement can
be visualized as shown in Figure 3.15 .

Figure – 3.15: Pins before and after placement

●​ Use the bind key “R” to rotate the pins and it can be done either before or after Pin Placement.
The direction of the pins before and after rotation are shown in Figure – 3.16.

Figure – 3.16: Pins before and after rotation

●​ The Schematic Editor window after pin placement is shown in Figure –3.17 .

Figure – 3.17: Schematic editor after pin placement

●​ For connecting the pins and the terminals, click on “Create → Wire” from the top menu (or) use
the bind key ‘W’ (or) the icon from the top menu as shown in Figure –3.18 .

Figure – 3.18: Create → Wire

●​ Use the left mouse click to start / complete the wire from one terminal / pin to another, or click
the bind key ‘S’ on the keyboard to automatically take a connection from the terminal when
approached by the cursor during wire mode.

Figure – 3.19: The final schematic of inverter

●​ It is mandatory to save the design before we move ahead to the Simulation and there are two
options, “Save” and “Check and Save” as in Figure –3.20

Figure – 3.20: “Check and Save” and “Save” option

●​ “Save” option saves the design as it is and “Check and Save” option checks for discontinuities
like floating net or terminal and provides the “error” or “warning” messages accordingly and then
save the design. Sample message can be seen in the “Command Interpreter Window” as shown in
Figure – 3.21.

Figure –3.21 : Message after selecting “Check and Save”

●​ A Symbol view is very important in a design process to make use of a Schematic in a hierarchy.
To create a symbol, select “Create → Cellview → From Cellview” from the top menu as shown
in Figure – 3.22.

Figure –3.22 :Create → Cellview → From Cellview

Verify the Library Name, Cell Name, From View Name, To View Name, etc., as shown in Figure –3.23
and Click on “OK”.

Figure –3.23 : “Cell view from Cell view” window

●​ The “Symbol Generation Options” window can be seen as shown in Figure – .

●​ The pin location on the symbol can be fixed using the options Left Pins, Right Pins, Top Pins and
Bottom Pins. Assign the pins and click on ‘OK’ as shown in Figure –3.25.
Figure –3.24 : “Symbol Generation Options” window

Figure – 3.25: “Symbol Generation Options” window

●​ The “Virtuoso Symbol Editor” window pops up with a default symbol based on the Pin
assignment as shown in Figure –3.26. Check and save the symbol.

Figure –3.26 : “Virtuoso Symbol Editor” window with default symbol

●​ The Test Circuit can be created using the symbol created. To create a test circuit, create a “New
Cell view” with a different “Cell Name” as shown in Figure – 3.27.
Figure –3.27 : New Cell view for Test Circuit
●​ Use the “Add Instance” option, select the respective Library, Cell and View as in Figure – 3.28 to
instantiate the symbol.

Figure – 3.28: Symbol Instantiation for the Test Circuit

●​ The remaining devices to be included on the Schematic and its properties are given below in
Table - 4.
Table – 4: Properties of vdc, vpulse, cap and gnd
Library name Cell Name Properties

analogLib Vdc DC voltage = 1.8 V

analogLib Vpulse Voltage 1 = 0 V, Voltage 2 = 1.8 V, Period = 20n s, Delay time

= 10n s, Rise time = 1p s, Fall time = 1p s, Pulse width = 10n s

analogLib Gnd

Figure – 3.29: Instantiating “vdc”

The screenshot of the device properties for the instances vdc, vpulse and gnd are shown in Figure
– 3.29, Figure –3.30 and Figure – 3.31 . The complete Test Schematic after wiring is shown in
Figure – 3.32.
●​ The complete circuit after instantiating all the devices and interconnections is shown in
Figure–3.32 . Check and save the test bench schematic for simulation
Figure – 3.30: Instantiating “vpulse”
Figure – 3.31: Instantiating “gnd”

Figure –3.32 : Complete Test Schematic

●​ To simulate the design and perform the DC Analysis and Transient Analysis for the CMOS
Inverter, click on “Launch → ADE L” from the top menu of the Test Schematic Cell view as
shown in Figure – 1.47.

Figure –3.33 : Launch → ADE L

●​ The “ADE L” window pops up as shown in Figure –3.34 .

Figure –3.34 : ADE L window

●​ To select the analysis required to be performed on the Test Circuit, select “Analyses → Choose”
from the top menu in the ADE L window as shown in Figure – .
●​ The “Choose Analyses – ADE L” window pops up as shown in Figure –3.35 .

Figure –3.35 : Analyses → Choose

Figure –3.36 : “Choosing Analyses” ADE L window
●​ To set up a “Transient Analysis”, select “tran”, mention the “Stop Time” (for example: 100n),
select “Accuracy Defaults” (for example: moderate), click on “Apply” and click on “OK” as
shown in Figure –3.37 .

Figure –3.37 : Setup for “Transient analyses”

●​ The selected analysis and the arguments can be seen under the “Analyses” tab in the ADE L
window as shown in Figure –.
●​ To set up a “DC Analysis”, select “dc” and enable “Save DC Operating Point” as shown in Figure
– 3.38.

Figure –3.38: Select “dc”

●​ Enable “Component Parameter”, click on “Select Component” as shown in Figure – 3.39.
●​ Select the “vpulse” source from the Test Schematic as shown in Figure – 3.40.
Figure –3.39: Select “dc”

Figure –3.40: Select “dc”

●​ Select “DC Voltage” from the list of parameters as shown in the “Select Component Parameter”
window and click on “OK” as shown in Figure – 3.41.
Figure –3.41:Enable “Component Parameter”
●​ From the “Sweep Range” option, select “Start-Stop” and mention the “Start” value as “0” and
“Stop” value as “1.8”, click on “Apply” and click on “OK” as shown in the Figure – 3.42.
Figure – 3.42: Mention the Sweep Range
●​ To select the outputs to be plotted, choose Outputs →To be plotted → Select on Design.
●​ The test bench circuit will be appeared to choose the Inputs and outputs.
●​ Select the Input Net “IN” and the Output Net “OUT” as shown in Figure – 3.43. The selected
Nets will be listed under “Outputs” in the “ADE L” window as shown in Figure – 3.44. The
currents at the Nodes can also be observed by clicking on the drain node for NMOS and PMOS
transistor. Click on “OK”.
Figure – 3.43: Select the Net “IN” and Net “Out”

Figure – 3.44: “Outputs” in ADE L window

●​To run the simulation, click on “Simulation → Netlist and Run” from ADE L window or Click the
icon indicated by arrow as shown in Figure –3.45.
Figure – 3.45: Simulation → Netlist and Run
●​ The simulated waveforms can be seen on the “Virtuoso Visualization and Analysis XL” window as
shown in Figure – 3.46.

Figure – 3.46: Simulated Waveforms

●​ The Input and Output Signals can be split up by selecting “Graph → Split All Strips” as in Figure
3.47

Figure – 3.47: Graph → Split All Strips

●​ To save the current ADE L state, click on “Session → Save State” as shown in Figure – 3.48.

Figure – 3.48: Session → Save State

●​ The “Saving State – ADE L” window pops up. Select the “Save State Option → Cellview” and click on
“OK” as shown in Figure – 3.49.

Figure – 3.49: Saving State

●​ The Test Schematic and the State can be seen in the Library Manager as shown in Figure –3.50.
Figure – 3.50: Test Schematic and Schematic in Library Manager
●​ To open the saved state, click on “Session → Load State” as shown in Figure – 3.51.

Figure – 3.51: Session → Load State

●​ The “Loading State – ADE L” window pops up. Select the “Load State Option → Cellview” and
click on “OK” as shown in Figure –3.52.

Figure – 3.52: “Loading State ADE L” window

●​ The Saved ADE L state is loaded as shown in Figure – 3.53.

Figure – 3.53: Reloaded ADE L State

Figure – 3.54: Transient analyses

Figure – 3.55: DC Analyses

Observation:
1.​ Justify the need of pMOS in the working of inverter.
2.​ What is the maximum current drawn by the inverter. Using Ohms law find the value of
resistor ROn.
3.​ Observe the difference in the values of Ron and RonL.
Experiment 4: Noise Margin and Delay Analysis of a CMOS Inverter
Aim:
Design a Lo skew, Hi Skew and a Normal skew Inverter with given specifications, completing the design
flow mentioned below.
a) Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis

Tools required: Cadence, Virtuoso

Figure – 4.1: Inverter Schematic with different W/L ratio

Specification for NMOS and PMOS are given below:

NMOS PMOS

LO skew L= 180n, W=1u L= 180n, W=0.25*2u

HI skew L= 180n, W=1u L= 180n, W=4*2u

Normal Skew L= 180n, W=1u L= 180n, W=2u

Figure – 4.2: DC Response

Figure – 4.3: Transient Response

Delay Analysis
●​ Select the input & the output waveform of a Normal inverter and Right click → send
to calculator. Visualization & Analysis XL calculator window opens as shown below.

●​ Under the function panel select→delay

For rise to fall delay & fall to rise delay:

Signal 1 Vout Vout

Signal 2 Vin Vin

Threshold value 1 0.9 0.9

Threshold value 2 0.9 0.9

Edge Type 1 rising falling

Edge Type 2 falling rising

Noise Margin:
Using the DC characteristics plotted, Noise Margin may be calculated using the formulas:

NMH=VOH-VIH

NML=VIL-VOL

Observation:
1. What is the Rise time and fall time delay of a CMOS inverter?
2. Calculate the Noise Margins for the following types of CMOS inverters:

a.​ Normal Skewed Inverter

b.​ High-Skewed (Hi-Skew) Inverter

c.​ Low-Skewed (Lo-Skew) Inverter

Experiment 5: Design and analysis of CMOS Combinational Circuits -NAND, NOR
and Complex Circuits.
Aim:
Design a 2 input NAND gate schematic and testbench and verify the: i) Transient Analysis

Schematic for a 2 input NAND gate

Figure – 5.1: Schematic of 2 input NAND gate

Figure – 5.2: Complete Test Schematic of 2 input NAND gate

Figure – 5.3: Transient Analysis of 2 input NAND gate

Exercise:
1.​ Implement a 2 input NOR gate and observe the transient response.
2.​ Implement the logic function using CMOS logic.
Experiment 6: Layout of a CMOS Inverter.
Aim:
Design the layout of a CMOS Inverter and verify the following:
i. Design Rule Check (DRC)
ii. Layout Versus Schematic (LVS)

●​ For preparing the layout of the inverter, all the other windows can be closed, except for
the virtuoso console. In the console, open the schematic of the inverter and click on
Launch → Layout XL. In the Startup Option, click on OK, ensuring the selections as
shown in the figure 6.1

Figure 6.1 Layout initial steps

●​ In the New File option, the tool selects the view as layout by default. Click on OK as shown in
figure 6.2
Figure 6.2: Choosing layout from schematic
●​ The tool opens the LSW and the Layout suite.

Figure 6.3: Layout and schematic window

●​ Maximize the layout suite and click on Connectivity → Generate → All from Source. A
Generate Layout window will open, with default attributes as shown in the figure 6.3 and 6.4
Figure 6.4: Connectivity→Generate →All from source

Figure 6.5:Generate Layout window

●​ Under the tab I/O pins→Create label as “LABEL”.

Figure 6.6: I/O Pins→Create label as “Label”

●​ The layout suite gets updated as shown below

●​ To view the terminals of the devices, click on “Shift + F” and the devices in the Virtuoso
●​ Layout Editor gets updated as shown in Figure 6.6

Figure 6.7: Figure showing NMOS & PMOS

●​ Press “Shift+ F” to see all the layers within the default layout. Hold the “right click” and
move the mouse to zoom a selected portion, and observe the layout carefully. The color
details are – Orange border: n-well, Red border: p-diffusion’s boundary, Yellow border:
n-diffusion’s boundary, Green: diffusion, Rose: polysilicon, Yellow square: contact cut, Blue
metal1.

●​
Figure 6.8: Shift+F
To make all connections visible Go to Connectivity→Incomplete Nets
→Show/Hide all nets

Figure 6.9: Connectivity→Incomplete Nets →Show/Hide all nets

●​ Click on the pmos device and drag it into the PR boundary. The layout can be moved either
vertically or horizontally, not diagonally. During this movement, the tool keeps displaying
the connections of the terminals with the nodes. After placing the pmos device, place the
nmos device below it. If the space is insufficient, the PR boundary can be enlarged, through
the top and the right edges. For this purpose, press “s” and click on the edge of the PR
boundary. (“s” is for stretch, in the layout suite). The selected edge will turn into magenta
color. Now release the finger and move the mouse till the desired area, and click again. Later,
press Esc.

Figure 6.10: Move the PMOS and NMOS into the PR boundary
Right click on PMOS →Click on Properties.
Edit instance properties box will be displayed as shown below

Figure 6.11: Edit Instance Properties

●​ Open the Parameter Tab

●​ Bodytie Type :Detached
●​ Check-in for Top tap for PMOS
●​ Similarly edit Properties for NMOS and detach the body to Bottom tap for NMOS.
Figure 6.12: Bodytie Type→ Detached

Figure 6.13: Bodytie Type→ Detached both PMOS and NMOS

●​ After placing the devices, zoom the space in between the transistors. In the LSW, select Poly.
Now in the layout suite, press “p”, place the mouse at the middle of the gate’s lower contact
of pmos device, and click once. (“p” is for path, in the layout suite). Release the finger and
move the mouse downwards. The poly path will move along with the mouse. Move the
mouse until the gate area of the nmos device gets overlapped. Bring the cursor exactly to the
middle of the path and double click. The poly path between the gates gets realized. The area
can be zoomed further, and the devices can be moved, for the exact overlapping of the
polylayers.

Figure 6.14: Poly to Poly connections

●​ In the LSW, select Metal1. Using the same procedure, draw the paths for “vdd” at the top and
“gnd” at the bottom. Later, using the same metal path, connect the source of pmos device to
“vdd” and that of nmos device to “gnd”. Finally, connect both the drains for the output path.

Figure 6.15: Metal connections

●​ Now, for connecting the input metal pin to the poly path,a via needs to be placed. Hence,
click on P from the keyboard, come close to pin Vin, left click and drag horizontally → Right
click→Via down to poly,Click once and drag and connect it to poly. Press Esc.
●​ Now move to the fourth quadrant where the four blue squares are displayed. Click on one of
them; it will turn into magenta color. Press “q”, and then click on Connectivity, to see its
properties. If it is vdd, drag it and place it on the upper metal path. Later, place the gnd on the
lower path; similarly, place the output pin. Now, place the input pin in front of the poly and
connect through a polypath.
Figure 6.16: Complete Layout of CMOS Inverter

●​ The layout is now complete, its verification can be performed.

●​ Select the technology path clicking on Assura→Technology.
●​ Assura technology lib select window will ne displayed.

Figure 6.17: Select Assura Technology

●​ By double clicking on the 3 dots we can select the path as

install→foundry→analog→180nm
●​ Double click on assura_tech_lib.
●​ The path will be displayed as shown below

Figure 6.18: Select path install→foundry→analog→180nm

●​ In the layout suite, click on Assura → Run DRC. Give the run directory as ./drc” and
technology as gpdk180. Click on OK.

Figure 6.19: Assura → Run DRC

If there are no errors it will display the message “No DRC errors found”

Figure 6.20: No DRC Errors

●​ Verify the output. If there are errors, the tool will highlight those areas in White color..
Correct those errors and rerun DRC.
●​ After the DRC check, click on Assura → Run LVS, and verify the output. Correct the errors.
Figure 6.21: Assura → Run LVS

Figure 6.22: LVS Summary

.
Figure 6.23: Layout of CMOS Inverter
Experiment 7: Layout of Combinational Circuits.
Aim: To draw the layout of a 2-input NAND gate, verify the DRC and check for LVS.

Fig: 7.1 Layout of NAND Gate

Experiment 8 : Analysis of a Pass Transistor and Transmission Gate Logic.
Aim: To Design a Pass transistor and Transmission Gate with given specifications and to draw the
schematic and verify the following: i) Transient Analysis

a)​ Pass Transistor Logic

Fig 8.1: Schematic of Pass Transistor

Fig 8.2: Test Bench Circuit

Design Specifications: Pass Transistor Logic

Vin Vin_N

V1 0 0

V2 1.8 1.8

Period 20n 40n

Pulse Width 10n 20n

Fig 8.3: Output Waveform

Observation:
1.​ Observe the output by connecting the body terminal of NMOS pass transistor to gnd.
b)​ Transmission Gate Logic

Fig 8.4: Schematic of Transmission Gate Logic

Fig 8.5: Test Bench Circuit

Design Specifications: Transmission Gate Logic

Vin Vin_P Vin_N

V1 0 0 0

V2 1.8 1.8 1.8

Period 20n 40n 80n

Pulse Width 10n 20n 40n

Fig 8.4: Output Waveform

Observation:
1.​ Observe the output by connecting the body terminal of NMOS pass transistor to Gnd & PMOS
pass transistor to Vdd.