Quarterly Asic Reliability Report: Nec Electronics Inc. July 1999 TRQ-99-07-330

NEC ELECTRONICS INC.

July 1999 TRQ-99-07-330

QUARTERLY ASIC RELIABILITY REPORT

This report contains reliability data on the following Application-Specific Integrated Circuit families assembled by NEC Electronics Inc. in Roseville, California (fabricated by NEC Japan or NEC Electronics Roseville as specified). BiCMOS-4 CMOS-3 CMOS-4 CMOS-5 CMOS-6 CMOS-6A CB-C9 CB-C9VX/VM UC-II
Prepared & Checked by: Signature on file B. Howell NEC Electronics Inc. R&QC Department
Approved by: Signature on file K. Muranaka NEC Electronics Inc. R&QC Department
Please refer all inquiries to: NEC Electronics Inc. Reliability and Quality Control Department 7501 Foothills Boulevard Roseville, CA 95747 Tel: (916) 786-3900
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors that may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied, or otherwise, is granted under any patents, copyrights, or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making a continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard," "Special," and "Specific." The Specific quality grade applies only to devices developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment, and industrial robots. Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anticrime systems, safety equipment, and medical equipment (not specifically designed for life support). Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, and life-support systems or medical equipment for life support, etc. The quality grade of NEC devices is Standard unless otherwise specified in NEC's data sheets or data books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
NEC Electronics Inc.

Contents
Roseville Manufacturing
Page Failure Rate Prediction Philosophy .............................................................................................. 3 Table 1. Reliability Test Conditions ............................................................................................. 5 Table 2. Pretreatment Conditions for T/H, T/C, and PCT Tests ................................................... 6 Table 3. HTB Life Test Summary and Failure Rate Predictions ........................................................ 7 Table 4. Other Life Test Summaries (HTSL, HHSL, T/H) ................................................................. 12 Table 5. Environmental and Mechanical Test Summaries (T/C, PCT) .............................................. 17 Table 6. Environmental and Mechanical Test Summaries (LI, SD, TS) ............................................ 22 Table 7. Failure Summaries ................................................................................................................. 26 Table 8. CMOS-8L Process Family, Quarterly Reliability Data ......................................................... 27 Table 9. CB-C9 Process Family, Quarterly Reliability Data .............................................................. 27 Table 10. CB-C9VX/VM Process Family, Quarterly Reliability Data ............................................... 28 Table 11. UC-II Process Family, Quarterly Reliability Data .............................................................. 28
NEC Electronics Inc. is dedicated to the QCD principle of providing the highest Quality product at the lowest possible Cost with on-time Delivery to our customers.

This report contains reliability test results of ASIC products subjected to routine Monitor Reliability Testing (MRT) at NEC. The products in this report were assembled in Roseville and fabricated in either Roseville or Japan as specified. They are all representative of NEC's manufacturing processes for ASIC products. This report also contains failure rate predictions, which were calculated using the Arrhenius method shown below.
The temperature contribution of the device's internal power dissipation is significant enough that it cannot be ignored. Therefore, the junction temperatures (Tj1 and Tj2) are used instead of the ambient temperatures (Ta1 and Ta2). If the thermal resistance of the device (junction to ambient) is known, it is possible to calculate the junction temperatures as follows: T j = Ta +( ja Pd) Where: (2)
Failure Rate Prediction Philosophy

When predicting the failure rate at a certain temperature from accelerated life test data, various values of activation energy corresponding to failure mechanisms should be considered. This is done whenever exact causes of failures are known by performing failure analysis. In some cases, however, an average activation energy is assumed in order to accomplish a quick first-order approximation. In the case of ASIC devices, NEC assumes an activation energy of 0.5 eV for such approximations. This value has been assessed from extensive reliability test results and yields a conservative failure rate. Since most semiconductor failures are temperature dependent, the Arrhenius relationship is used to normalize failure rate predictions at a system operation temperature of 55C. The Arrhenius model includes the effects of temperature and activation energy of the failure mechanisms. This model assumes that the degradation of a performance parameter is linear with time. The temperature dependence is taken to be an exponential function that defines the probability of occurrence. The Arrhenius equation for high-temperature stress is given as the following: A(T) = e -Ea ( T j - T j ) 1 2 k ( T j )(T j ) 1 2 (1)
ja = Thermal resistance
Pd = Power dissipation
With this information, we can therefore calculate a temperature acceleration factor. Having now predicted the overall acceleration factor for the high-temperature operating life test, the failure rate can be predicted at a 60% confidence level using the following equation:
L= Where: L
2 105
2T
(3)
Failure rate in %/1000 hours
2 The tabular value of chi-squared

distribution at a given confidence level and calculated degrees of freedom (n = 2f + 2, where f = number of failures) T = Number of equivalent device hours (Number of devices) x (number of test hours) x (acceleration factor)
Where: A(T) Temperature acceleration factor Ea Activation energy Tj1 Junction temperature (in K) at Ta1 = 55C Tj2 Junction temperature (in K) at Ta2 = 125C k Boltzmann's constant -5 = 8.62 x 10 eV/K Exhibit Table: 90% f n
2 value for confidence level of 60% and

0 2 1.83 4.61 1 4 4.04 7.78 2 6 6.21 10.6 3 8 8.35 13.4
C.L. = 60% C.L. = 90%

Exhibit Table: Acceleration factor for different Tj2 / Tj1 with different activation energy Tj2 (C)/Tj1 (C) Acceleration Factor 0.3eV 0.5eV (Typ) 6.47 22.5 4.07 10.4 3.05 6.42 2.32 4.08 1.80 2.66 1.41 1.77 1.12 1.20 10.8 53.2 6.82 24.5 5.12 15.2 3.90 9.66 3.01 6.29 2.36 4.19 1.87 2.85 Example
A sample of 960 devices was subjected to 1000 hours of 125C burn-in at 7.0 volts. One reject was observed. Given that the acceleration factor was calculated to be 34.6 (using Equation 1), what is the failure rate, normalized to 55C, using a confidence level of 60%? Express the failure rate in FIT. Solution For n = 2f + 2 = 2(1) + 2 = 4 X confidence level). Then, L=
2
0.7eV 78.0 26.4 13.5 7.16 3.93 2.22 1.30 261 88.2 45.1 24.0 13.1 7.43 4.33
125/55 125/70 125/80 125/90 125/100 125/110 125/120 150/55 150/70 150/80 150/90 150/100 150/110 150/120
= 4.04 (for 60%
X 2 10 5 X 2 10 5 (% / 1000 hrs) = 2T 2(total device hrs)(accel factor)
(4.04) 10 5 = 0.0061 % / 1000 hrs 2(960)(1000)(34.6)
Therefore, 0.0061%10 9 1000 hrs
FIT = Another method of expressing failures is as FIT (failures in 9 time). One FIT is equal to one failure in 10 hours. Since -5 L is already expressed as %/1000 hours (10 failure/hr), an easy conversion from %/1000 hours to FIT would be to 9 multiply the value of L by 10 . In conclusion, the failure rate of the whole process family is expressed as follows: L(FIT) =
= 61
2 109
2 T
(4)
Where summation T is taken for all reliability tests performed on the process family. Note: Some of the estimated FIT rates are higher than would be expected due to small sample sizes; however, they are expected to lower as reliability monitor data is accumulated.

Table 1. Reliability Test Conditions
The reliability tests performed by NEC consist of high-temperature bias life (HTB), high-temperature storage life (HTSL), highhumidity storage life (HHSL), and high-temperature, high-humidity life (T/H = HHSL + bias). Additionally, various environmental and mechanical tests are performed. The table below shows the conditions of various life tests, environmental tests, and mechanical tests.
Test Item High-temperature bias life
Symbol HTB1 HTB2
MIL-STD 883C Method 1005
Test Conditions TA = 125C TA = 150C VDD = VDD max.
Remarks Note 1
High-temperature storage life
HTSL1 HTSL2 HTSL3 HTSL4
1008
TA = 150C TA = 175C TA = 200C TA = 250C TA = 85C; RH = 85%; VDD = VDD max. Pretreatment as specified in Table 2, if any. TA = 85C; RH = 85% Pretreatment as specified in Table 2, if any. TA = 125C; P = 2.3 atm
Note 1
High-temperature/highhumidity bias life
T/H
Note 1
High-humidity storage life Pressure cooker Temperature cycle Lead fatigue Solderability Soldering heat Temperature cycle Thermal shock Notes: 1. 2. 3. 4.
HHSL PCT T/C LI SD TS 1010 2004 2003 Note 4 1010 1011
Note 1 Note 1 Note 1 Note 2 Note 3
Pretreatment as specified in Table 2, if any. 65C to 150C Pretreatment as specified in Table 2, if any. 90 bends; 3 bends without breaking 230C; 5 sec; rosin base flux 260C; 10 sec; rosin base flux 10 cyc; 1 hr/cyc; 65C to 150C 15 cyc; 10 min/cyc; 0C to 100C
Note 1
Electrical test per data sheet is performed. Devices that exceed the data sheet limits are considered rejects. Broken lead is considered a reject. Less than 95% coverage is considered a reject. MIL-STD-750A, Method 2031.

Table 2. Pretreatment Conditions for T/H, T/C, and PCT Tests
Pretreatment Condition A B C C16 D D16 E !-1 !-2 !-3 Temp Cycling (-65C to 150C, 20 cyc) + Bake (125C, hrs) + Humidity Storage + (30C/70% RH, ! days + 10 hrs) Temp Cycling + Humidity Storage +
Infrared Reflow (230C Peak) Vapor Phase Soldering (215C Peak) Bake (125C, 4 hrs) + IR Bake (125C, 16 hrs) + IR Bake (125C, 4 hrs) + VPS Bake (125C, 16 hrs) + VPS Lead Soldering (260C, 10 sec) Infrared Reflow (240C Peak) 1 time Infrared Reflow (240C Peak) 2 times Infrared Reflow (240C Peak) 3 times
(65C to 150C, 20 cyc)
(85C/85% RH, 72 hrs)
: Bake time ! : Storage time: 2 58 hours 3 82 hours 7 178 hours Example

PCT with pretreatment 2072 = T/C (20 cycles) Bake (20 hours) Humidity Storage (178 hours) IR Reflow (2 times) PCT

Table 3. HTB Life Test Summary and Failure Rate Predictions
This table summarizes the reliability test results of processes extensively used by most NEC ASIC products. The failure rate predictions are based on both 125C and 150C high-temperature bias life test results. Failure rate predictions are shown for the current period of available data and for past periods of cumulative data.
Process Type Process Period Ambient Temp. Number of Devices Accum. Device Hours No. of Failures (Note 1) Accel. Factor (Note 2) Equiv. Device Hours Failure Rate 55C and 60% Confidence Level (Note 3)
3A. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D67070GF Jan 89Jun 97 125C 88 (100-pin QFP) D67030GF Oct 88Jun 97 125C 72 (100-pin QFP) D67010L Jan 89Jun 97 125C 136 (68-pin PLCC) D67010GF Jul 91Jun 97 125C 24 (100-pin QFP) Jan 89Jun 99 125C 320 BiCMOS (cumulative) 3B. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65030L Jan 89Jun 97 125C 236 (68-pin PLCC) 3C. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65030L Jan 89Jun 97 125C 72 (68-pin PLCC) Jan 89Jun 99 125C 308 CMOS-3 (cumulative) 3D. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65013GF Jul 88Jun 97 125C 156 (100-pin QFP) D65022L Jul 88Jun 97 125C 198 (68-pin PLCC) 125C 24 D65024L Apr 89Jun 97 (84-pin PLCC) D65030L Oct 91Jun 97 125C 24 (68-pin PLCC) D65031L Oct 89Jun 97 125C 24 (84-pin PLCC) D65042L Apr 88Jun 97 125C 276 (84-pin PLCC) D65070L Apr 88Jun 97 125C 88 (68-pin PLCC) D65081L Jul 88Jun 97 125C 40 (84-pin PLCC) D65081GF Jul 88Jun 97 125C 48 (100-pin QFP) 3E. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65012L Oct 92Jun 97 125C 48 (64-pin PLCC) D65012GF Jan 93Jun 97 125C 48 (80-pin QFP)
8.8 x 10 7.2 x 10
4 4 5
0 0 0 0 0
47 47 47 47 47 1.5 x 10
7
1.36 x 10 2.4 x 10
4 5
3.20 x 10
0.0061%/1000 = 61 FIT
2.36 x 10
49
7.20 x 10 3.08 x 10
4 5
0 0
49 49 1.5 x 10
7
0.0061%/1000 = 61 FIT
1.56 x 10 1.98 x 10 2.4 x 10 2.4 x 10 2.4 x 10
5 5
0 0 0 0 0 0 0 0 0
13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5
4 4 4 5
2.76 x 10 8.8 x 10 4.0 x 10 4.8 x 10
4 4 4
4.8 x 10 4.8 x 10
4 4
0 0
13.5 13.5

Table 3. HTB Life Test Summary (continued)
Process Type Process Period Ambient Temp. Number of Devices Accum. Device Hours 1.44 x 10 3.12 x 10 4.8 x 10 7.2 x 10
5 5
No. of Failures (Note 1) 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 Accel. Factor (Note 2) 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 4.19 x 10
7
Equiv. Device Hours
Failure Rate 55C and 60% Confidence Level (Note 3)
D65013GF (64-pin QFP) D65013GF (100-pin QFP) D65022L (68-pin PLCC) D65031L (68-pin PLCC) D65031L (84-pin PLCC) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65042L (84-pin PLCC) D65042GF (64-pin QFP) D65042GF (80-pin QFP) D65042GF (100-pin QFP) D65070L (84-pin PLCC) D65081L (84-pin PLCC) D65081GF (100-pin QFP) CMOS-4
Jan 93Sep 98 Apr 91Jun 97 Jan 92Jun 97 Jan 96Mar 98 Jan 93Jun 98 Oct 91Jun 98 Jul 91Jun 97 Jan 92Jun 97 Apr 88Jun 97 Jan 93Jun 97 Jan 93Jun 97 Jan 95Sep 98 Apr 90Jun97 Apr 94Jun 97
125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C
144 312 48 72 168 120 48 72 144 24 48 72 96 120
4 4 5 5
1.68 x 10 1.20 x 10 4.8 x 10 7.1 x 10
4 4 5
1.44 x 10 2.4 x 10 4.8 x 10 9.6 x 10 9.6 x 10 1.2 x 10
4 4 4 4 5 6
Apr 88Jun 99 125C 2462 (cumulative) 3F. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65032L Jan 90Jun 97 125C 168 (84-pin PLCC) D65044L Jan 89Jun 97 125C 264 (84-pin PLCC) D65061GF Jan 90Jun 97 125C 120 (100-pin QFP) D65103L Apr 91Jun 97 125C 24 (68-pin PLCC) 3G. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65016GF Oct 93Jun 97 125C 168 (80-pin QFP) D65016GD (120-pin QFP) D65025L (68-pin PLCC) D65025GF (80-pin QFP) Jan 96Jun 97 Oct 92Jun 97 Jul 91Jun 97 125C 125C 125C 24 144 48
3.10 x 10
0.00742%/1000 = 74 FIT
1.68 x 10 2.64 x 10 1.20 x 10 2.4 x 10
5 5 5
0 0 0 0
13.5 13.5 13.5 13.5
1.68 x 10 2.4 x 10
0 0 0 0
13.5 13.5 13.5 13.5
1.44 x 10 4.8 x 10

Process Type Process Period Ambient Temp. Number of Devices Accum. Device Hours 1.2 x 10 2.4 x 10 2.4 x 10 2.4 x 10
5
No. of Failures (Note 1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Accel. Factor (Note 2) 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 5.00 x 10
7
Equiv. Device Hours
Failure Rate 55C and 60% Confidence Level (Note 3)
D65025GD (160-pin QFP) D65029GF (100-pin QFP) D65029GD (120-pin QFP) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65032GF (100-pin QFP) D65044L (68-pin PLCC) D65044L (84-pin PLCC) D65046GD (120-pin QFP) D65046GD (136-pin QFP) D65046GD (160-pin QFP) D65051GF (120-pin QFP) D65051GF (160-pin QFP) D65061L (68-pin PLCC) D65061GF (100-pin QFP) D65061GD (136-pin QFP) D65062GD (136-pin QFP) D65062GD (160-pin QFP) D65082GD (160-pin QFP) D65103L (68-pin PLCC) D65103GD (160-pin QFP) D65103GD (80-pin QFP) D65180GD (160-pin QFP) CMOS-5
Apr 90Jun 97 Jul 91Jun 97 Jul 92Jun 97 Jan 92Jun 97 Jan 91Dec 97 Oct 91Jun 97 Jul 94Jun 97 Oct 98Dec 98 Jan 92Jun 97 Oct 92Jun 97 Apr 91Mar 98 Jan 96Sep 98 Jul 97Sep 97 Oct 96Sep 98 Jan 90Jun 97 Jan 91Jun 97 Jul 93Jun 97 Apr 93Jun 97 Apr 93Jun 97 Apr 90Jun 98 Jan 93Jun 97 Jul 97Dec 97 Jan 90Jun 97 Jan 89Jun 99 (cumulative)
125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C
120 24 24 24 192 240 48 24 245 168 192 144 24 72 120 240 24 48 24 480 48 48 144 3677
2.16 x 10 2.4 x 10
4.8 x 10 4.0 x 10
2.45 x 10 1.68 x 10 1.92 x 10 1.44 x 10 2.4 x 10
7.2 x 10 1.2 x 10 2.4 x 10 2.4 x 10 4.8 x 10 2.4 x 10
5.04 x 10 4.8 x 10 4.8 x 10
1.44 x 10 3.70 x 10
0.00183%/1000 = 18 FIT

Process Type Process Period Ambient Temp. Number of Devices Accum. Device Hours
No. of Failure (Note 1) Accel. Factor (Note 2) Equiv. Device Hours Failure Rate 55C and 60% Confidence Level (Note 3)
3H. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65622GF Apr 96Jun 97 125C 24 (80-pin QFP) D65632 Sep 97Dec 97 24 125C (100-pin QFP) D65640GF Apr 97Jun 98 125C 96 (80-pin QFP) D65640GF Jan 94Sep 98 125C 264 (100-pin QFP) D65640GD Apr 94Sep 98 125C 316 (120-pin QFP) D65646GF Jul 94Jun 97 125C 48 (100-pin QFP) D65646GD Jul 94Jun 97 125C 24 (136-pin QFP) D65650GF Jul 92Jun 97 125C 72 (80-pin QFP) D65650GF Jul 93Jun 97 125C 48 (100-pin QFP) D65650GD Jan 92Sep 97 125C 384 (160-pin QFP) D65654GF Oct 93Jun 97 125C 96 (100-pin QFP) D65654GD Jan 92Dec 98 125C 264 (160-pin QFP) D65658GD Jan 91Dec 97 125C 216 (160-pin QFP) D65658GD Apr 95Jun 98 125C 120 (208-pin QFP) Nov 90Jun 99 125C 1996 CMOS-6A (cumulative) 3I. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN D65841GJ Mar 96Aug 96 150C 576 (144-pin QFP) 3J. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65832GD Jan 99Jun 99 72 150C (208-pin QFP) Mar 96Jun 99 150C 648 CMOS-8L (cumulative) 3K. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN TEG 1 May 97Sep 97 125C 24 (304-pin QFP) TEG 2 May 97Sep 97 125C 24 (352-pin TBGA)
2.4 x 10 2.4 x 10
4 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 4.49 x 10
7
1.20 x 10 2.64 x 10 3.16 x 10 4.8 x 10 2.4 x 10 7.2 x 10 4.8 x 10
5 5 5
4 4 4 4 5
3.84 x 10 9.6 x 10
4 5 5 5 6
2.44 x 10 2.16 x 10 1.20 x 10 1.99 x 10
0.00204%/1000 = 20 FIT
5.76 x 10
53.2
7.2 x 10
0 0
53.2 53.2 3.45 x 10

7
6.48 x 10
0.00265%/1000 = 27 FIT
4.8 x 10 2.4 x 10
0 0
22.5 22.5
10

Process Type Process Period Ambient Temp. Number of Devices Accum. Device Hours
No. of Failure (Note 1) Accel. Factor (Note 2) Equiv. Device Hours Failure Rate 55C and 60% Confidence Level (Note 3)
3L. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D82174GD Oct 98Dec 98 125C 48 (160-pin QFP) May 97Jun 99 125C 96 CB-C9 (cumulative) 3M. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN TEG 1 Apr 98Jun 98 150C 47 (304-pin QFP) 3N. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D82286S1 Oct 98Dec 98 150C 72 (272-pin PBGA) D82287S1 Jan 99Mar 99 112 150C (272-pin PBGA) 48 125C CB-C9VX/VM Apr 98Jun 99 (cumulative) 150C 125C 231 48
4.8 x 10 1.2 x 10
4 5
0 0
22.5 22.5 2.70 x 10

6
Note 4
4.7 x 10
53.2
7.2 x 10
4 5
0 0 0 0
53.2 53.2 22.5 53.2 22.5 1.34 x 10

7
1.12 x 10 4.8 x 10
4 5
2.31 x 10 4.8 x 10 4.8 x 10 4.8 x 10
0.00684%/1000 = 68 FIT
3O. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D83901S1 Apr 99Jun 99 150C 48 (320-pin PBGA) Apr 99Jun 99 150C 48 UC-II (cumulative) Notes: 1. 2. 3. 4.
4 4
0 0
53.2 53.2 2.55 x 10

6
Note 4
Details of failures are given in Table 7. The acceleration factor was calculated using the Arrhenius mathematical model shown on page 3. FIT was derived from HTB data for all available time periods (devices included in this and all previous ASIC reports issued by NEC Electronics on Japan- and Roseville-made devices). Some of the FIT rates were not calculated due to small sample sizes. In these cases, the FIT rates would not be meaningful. NEC expects a FIT rate of less than 100 for ASIC device types (target not to exceed 150).
11

Table 4. Other Life Test Summaries (HTSL, HHSL, T/H)
This table summarizes the reliability test results of the different process types during 150C storage and 85C/85% RH storage and bias tests. The data is summarized for the current period of available data and for past periods of cumulative data.
Process Type Process Period Qty D67070GF (100-pin QFP) D67030GF (100-pin QFP) D67010L (68-pin PLCC) D67010GF (100-pin QFP) BiCMOS Jan 89Jun 97 Oct 88Jun 97 Jan 89Jun 97 Jul 91Jun 97 Jan 89Jun 99 (cumulative) Jan 89Jun 97 80 60 120 20 280 HTSL Failures Hours 168 0 0 0 0 0 500 0 0 0 0 0 1000 0 0 0 0 0 Qty 0 0 0 0 0 HHSL Failures Hours 168 500 1000 Qty 64 72 136 24 296 T/H Failures Hours 168 0 0 0 0 0 500 0 0 0 0 0 1000 0 0 0 0 0
4A. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE
4B. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65030L (68-pin PLCC) D65030L (68-pin PLCC) CMOS-3 200 0 0 0 0 235 0 0 0
4C. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Jul 90Jun 97 Jan 89Jun 99 (cumulative) Jul 88Jun 97 Jul 88Jun 97 Apr 89Jun 97 Oct 91Jun 97 Oct 89Jun 97 Apr 88Jun 97 Apr 88Jun 97 Jul 88Jun 97 60 260 0 0 0 0 0 0 0 0 72 307 0 0 0 0 0 0
4D. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65013GF (100-pin QFP) D65022L (68-pin PLCC) D65024L (84-pin PLCC) D65030L (68-pin PLCC) D65031L (84-pin PLCC) D65042L (84-pin PLCC) D65070L (68-pin PLCC) D65081GF (100-pin QFP) D65012L (68-pin PLCC) D65012L (80-pin QFP) 140 182 20 20 20 240 80 20 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 206 24 24 24 276 87 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4E. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Oct 92Jun 97 Jan 93Jun 97 40 40 0 0 0 0 0 0 0 0 48 48 0 0 0 0 0 0
Note: Details of failures are given in Table 7.
12

Process Type D65013GF (64-pin QFP) D65013GF (100-pin QFP) D65022L (68-pin PLCC) D65031L (68-pin PLCC) D65031L (84-pin PLCC) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65042L (84-pin PLCC) D65042GF (64-pin QFP) D65042GF (80-pin QFP) D65042GF (100-pin QFP) D65070L (84-pin PLCC) D65081L (84-pin PLCC) D65081GF (100-pin QFP) CMOS-4 Process Period Qty Jan 93Sep 98 Apr 91Jun 97 Jan 92Jun 97 Feb 96Mar 98 Apr 95Jun 98 Oct 91Jun 98 Jul 91Jun 97 Jan 92Jun 97 Apr 88Jun 97 Jan 93Jun 97 Jan 93Jun 97 Jan 95Sep 98 Apr 90Jun 97 Apr 94Jun 97 Jan 89Jun 99 (cumulative) Jan 90Jun 97 Jan 89Jun 97 Jan 90Jun 97 Apr 91Jun 97 120 240 40 60 140 100 40 80 120 20 40 60 80 100 2042 HTSL Failures Hours 168 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qty 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HHSL Failures Hours 168 500 1000 Qty 144 288 48 72 168 120 48 96 144 24 24 72 96 120 2377 T/H Failures Hours 168 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4. Other Life Test Summaries (HTSL, HHSL, T/H) (continued)
4F. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65032L (84-pin PLCC) D65044L (84-pin PLCC) D65061GF (100-pin QFP) D65103L (68-pin PLCC) D65016GF (80-pin QFP) D65016GD (120-pin QFP) 140 220 100 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 168 184 120 24 0 0 0 0 0 0 0 0 1 0 0 0
4G. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Oct 93Jun 97 Jan 96Jun 97 120 20 0 0 0 0 0 0 125 25 0 0 0 0 0 0 144 24 0 0 0 0 1 0
13

Process Type D65025L (68-pin PLCC) D65025GF (80-pin QFP) D65025GD (160-pin QFP) D65029GF (100-pin QFP) D65029GD (120-pin QFP) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65032G (100-pin QFP) D65044L (68-pin PLCC) D65044L (84-pin PLCC) D65046GD (120-pin QFP) D65046GD (136-pin QFP) D65046GD (160-pin QFP) D65051GD (120-pin QFP) D65051GD (160-pin QFP) D65061L (68-pin PLCC) D65061GF (100-pin QFP) D65061GD (136-pin QFP) D65062GD (136-pin QFP) D65062GD (160-pin QFP) D65081L (84-pin PLCC) D65082GD (160-pin QFP) D65103L (68-pin PLCC) Process Period Qty Oct 92Jun 97 Jul 95Jun 97 Apr 90Jun 97 Jul 92Jun 97 Jul 92Jun 97 Jan 92Jun 97 Jan 91Dec 97 Oct 91Jun 97 Jul 94Jun 97 Oct 98Dec 98 Jan 92Jun 97 Oct 92Jun 97 Apr 91Mar 98 Jan 96Sep 98 Jul 97Sep 97 Apr 97Sep 98 Jan 90Jun 97 Jan 92Jun 97 Jul 93Jun 97 Apr 93Jun 97 Oct 92Jun 97 Apr 93Jun 97 Apr 90Jun 98 100 40 120 20 20 20 1420 200 40 20 180 140 160 120 20 40 100 180 20 40 20 20 440 HTSL Failures Hours 168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qty 150 50 100 25 25 25 200 250 50 25 220 150 200 150 25 50 150 250 25 50 25 25 450
HHSL Failures Hours 168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qty 144 48 96 24 24 24 192 240 48 24 216 164 192 144 24 48 120 240 24 48 24 24 432 T/H Failures Hours 168 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
14

Process Type D65103GD (80-pin QFP) D65103GD (160-pin QFP) D65180GD (160-pin QFP) CMOS-5 Process Period Qty Jul 97 Dec 97 Jan 93Jun 97 Jan 90Jun 97 Jan 88Jun 99 (cumulative) Apr 96Jun 97 Sep 97Dec 97 Apr 97Jun 98 Jan 95Sep 98 Apr 94Sep 98 Jul 94Jun 97 Jul 95Jun 97 Jul 92Jun 97 Jul 93Jun 97 Jan 92Sep 97 Oct 93Jun 97 Jan 92Dec 98 Jan 91Dec 97 Apr 95Jun 98 Jan 88Jun 99 (cumulative) 40 40 120 3040 0 0 0 0 HTSL Failures Hours 168 500 0 0 0 0 1000 0 0 0 0 Qty 50 50 150 3070
HHSL Failures Hours 168 0 0 0 0 500 0 0 0 0 1000 0 0 0 0 Qty 48 48 144 3468 T/H Failures Hours 168 0 0 0 2 500 0 0 0 0 1000 0 0 0 3
4H. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65622GF (100-pin QFP) D65632 (100-pin QFP) D65640GF (80-pin QFP) D65640GF (100-pin QFP) D65640GD (120-pin QFP) D65646GF (100-pin QFP) D65646GD (136-pin QFP) D65650GF (80-pin QFP) D65650GF (100-pin QFP) D65650GD (160-pin QFP) D65654GF (100-pin QFP) D65654GD (160-pin QFP) D65658GD (160-pin QFP) D65658GD (208-pin QFP) CMOS-6, 6A 20 20 80 180 260 40 20 60 40 320 80 220 179 100 1619 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 25 100 225 320 50 25 75 50 400 100 275 225 100 1994 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 24 24 96 216 312 48 24 72 48 384 96 264 216 120 1944 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
4I. FABRICATED IN ROSEVILLE, ASSEMBLED D65841GJ Mar 96Jan 97 0 (144-pin QFP) D65848GN Mar 96Jan 97 0 (240-pin TAB QFP) D65895GL Mar 96Dec 96 0 (304-pin QFP FP) Note: Details of failures are given in Table 7.
IN JAPAN 0 0 0 264 264 240 0 0 0 0 0 0 0 0 0
15

Process Type D65895S1 (352-pin PBGA) Process Period Qty Mar 96Dec 96 0 HTSL Failures Hours 168 500 1000 Qty 0
HHSL Failures Hours 168 500 1000 Qty 240 T/H Failures Hours 168 0 500 0 1000 0
4J. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65832GD Jan 99Jun 99 60 0 0 (208-pin QFP) CMOS-8L Mar 96Jun 99 (cumulative) 60 0 0
0 0
0 0
72 1080
0 0
0 0
0 0
4K. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN TEG 1 May 97-Sep 97 20 0 0 (304-pin QFP) TEG 2 May 97-Sep 97 24 0 0 (352-pin TBGA)
0 0
0 0
24 24
0 0
0 0
0 0
4L. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D82174GD Jan 99Mar 99 0 (160-pin QFP) May 97Jun 99 CB-C9 44 0 0 0 (cumulative) 4M. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D82286S1 Oct 98Dec 98 0 (272-pin PBGA) D82287S1 Jan 99Mar 99 20 0 0 0 (272-pin PBGA) Oct 98Jun 99 CB-C9VX/VM 20 0 0 0 (cumulative) 4N. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D83901S1 Apr 99Jun 99 0 (320-pin PBGA) Apr 99Jun 99 UC-II 0 (cumulative) Note: Details of failures are given in Table 7.
0 0
48 96
0 0
0 0
0 0
0 0 0
144 72 216
0 0 0
0 0 0
0 0 0
0 0
48 48
0 0
0 0
0 0
16
Table 5. Environmental and Mechanical Test Summaries (T/C, PCT)

This table summarizes the environmental and mechanical test results of the different process types. The data is summarized for the current period and for past periods of cumulative data.
Process Type Process Period Qty D67070GF (100-pin QFP) D67030GF (100-pin QFP) D67010L (68-pin PLCC) D67010GF (80-pin QFP) BiCMOS Jan 89Jun 97 Oct 88Jun 97 Jan 89Jun 97 Jul 91Jun 97 Oct 88Jun 99 (cumulative) Jan 89Jun 97 90 72 166 25 353 T/C Failures Cycles 100 0 0 0 0 0 300 0 0 0 0 0 Qty 60 60 40 20 180 PCT Failures Hours 96 0 0 0 0 0 192 0 0 0 0 0
5A. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE
5B. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65030L (68-pin PLCC) D65030L (68-pin PLCC) CMOS-3 219 0 0 0 -
5C. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Jan 89Jun 97 Jan 89Jun 99 (cumulative) Jul 88Jun 97 Jul 88Jun 97 Apr 89Jun 97 Oct 91Jun 97 Oct 89Jun 97 Apr 88Jun 97 Apr 88Jun 97 Jul 88Jun 97 Jul 88Jun 97 75 294 0 0 0 0 0 0 -
5D. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65013GF (100-pin QFP) D65022L (68-pin PLCC) D65024L (84-pin PLCC) D65030L (68-pin PLCC) D65031L (84-pin PLCC) D65042L (84-pin PLCC) D65070L (68-pin PLCC) D65081L (84-pin PLCC) D65081GF (100-pin QFP) D65012L (68-pin PLCC) D65012GF (80-pin QFP) D65013GF (64-pin QFP) 158 130 25 25 25 280 65 20 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 -
5E. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Oct 92Jun 97 Jan 92Jun 97 Jan 93Sep 98 50 50 150 0 0 0 0 0 0 40 40 120 0 0 0 0 0 0
17

Process Type D65013GF (100-pin QFP) D65022L (68-pin PLCC) D65031L (68-pin PLCC) D65031L (84-pin PLCC) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65042L (84-pin PLCC) D65042GF (64-pin QFP) D65042GF (80-pin QFP) D65042GF (100-pin QFP) D65070L (84-pin PLCC) D65081L (84-pin PLCC) D65081GF (100-pin QFP) CMOS-4 Process Period Qty Apr 91Jun 97 Jan 92Jun 97 Feb 96Mar 98 Apr 95Jun 98 Oct 91Jun 98 Jul 91Jun 97 Jan 92Jun 97 Apr 88Jun 97 Jan 92Jun 97 Jan 93Jun 97 Jan 95Sep 98 Apr 90Jun 97 Apr 94Jun 97 Apr 88Jun 99 (cumulative) Jan 90Jun 97 Jan 89Jun 97 Jan 90Jun 97 Apr 91Jun 97 300 50 75 175 125 50 75 150 25 50 75 100 125 2401 T/C Failures Cycles 100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 300 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Qty 180 40 60 140 100 40 60 0 20 40 60 80 100 1120
PCT Failures Hours 96 0 0 0 8 1 0 0 0 2 0 0 0 11 192 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5. Environmental and Mechanical Test Summaries (T/C, PCT) (continued)
5F. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65032L (84-pin PLCC) D65044L (84-pin PLCC) D65061GF (100-pin QFP) D65103L (68-pin PLCC) D65016GF (80-pin QFP) D65016GD (120-pin QFP) D65025L (68-pin PLCC) D65025GF (80-pin QFP) D65025GD (160-pin QFP) 175 275 120 25 0 0 0 0 0 0 0 0 0 0 0 0 -
5G. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Oct 93Jun 97 Jan 96Jun 97 Oct 92Jun 97 Oct 93Jun 97 Apr 90Jun 97 150 25 144 50 120 1 0 0 0 0 0 0 0 0 0 120 20 80 40 0 0 0 0 0 0 0 0 0 -
18

Process Type D65029GF (100-pin QFP) D65029GD (120-pin QFP) D65031GF (100-pin QFP) D65032L (84-pin PLCC) D65032GF (100-pin QFP) D65044L (68-pin PLCC) D65044L (84-pin PLCC) D65046GD (120-pin QFP) D65046GD (136-pin QFP) D65046GD (160-pin QFP) D65051GD (120-pin QFP) D65051GD (160-pin QFP) D65061L (68-pin PLCC) D65061GF (100-pin QFP) D65061GD (136-pin QFP) D65062GD (136-pin QFP) D65062GD (160-pin QFP) D65081L (84-pin PLCC) D65082GD (160-pin QFP) D65103L (68-pin PLCC) D65103GF (80-pin QFP) D65103GF (160-pin QFP) D65180GF (160-pin QFP) Process Period Qty Jul 91Jun 97 Jul 92Jun 97 Jan 92Jun 97 Jan 91Dec 97 Oct 91Jun 97 Jul 94Jun 97 Oct 98Dec 98 Jan 92Jun 97 Oct 92Jun 97 Apr 91Mar 98 Jan 96Sep 98 Jul 97Sep 97 Oct 96Sep 98 Jan 90Jun 97 Jan 91Jun 97 Jul 93Jun 97 Apr 93Jun 97 Oct 92Jun 97 Apr 93Jun 97 Apr 90Jun 98 Jul 97Dec 97 Jan 93Jun 97 Jan 90Jun 97 25 25 25 200 250 50 25 250 150 200 150 25 75 120 225 25 50 25 25 496 50 50 120 T/C Failures Cycles 100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 300 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 2 0 0 0 Qty 20 20 20 80 180 40 20 120 140 60 120 20 60 100 120 20 40 20 20 300 40 40 80
PCT Failures Hours 96 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 192 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0
19

Process Type CMOS-5 Process Period Qty Jul 88Jun 99 (cumulative) Apr 96Jun 96 Sep 97Dec 97 Apr 97Jun 98 Jan 94Sep 98 Apr 94Sep 98 Jul 94Jun 97 Jul 95Jun 97 Jul 91Jun 97 Jul 93Jun 97 Jan 92Sep 97 Oct 93Jun 97 Jan 92Dec 98 Jan 91Dec 97 Apr 95Jun 98 Jul 91Jun 99 (cumulative) 3720 T/C Failures Cycles 100 3 300 4 Qty 1940
PCT Failures Hours 96 2 192 3
5H. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65622GF (80-pin QFP) D65632 (100-pin QFP) D65640GF (80-pin QFP) D65640GF (100-pin QFP) D65640GD (120-pin QFP) D65646GF (100-pin QFP) D65646GD (136-pin QFP) D65650GF (80-pin QFP) D65650GF (100-pin QFP) D65650GD (160-pin QFP) D65654GF (100-pin QFP) D65654GD (160-pin QFP) D65658GD (160-pin QFP) D65658GD (208-pin QFP) CMOS-6, 6A 25 25 100 300 275 50 25 75 50 375 100 270 225 125 2020 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 20 20 80 200 220 40 20 70 40 320 80 220 160 100 1590 0 0 0 1 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5I. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN D65841GJ Mar 96Jan 97 250 0 (144-pin QFP) D65848GN Mar 96Jan 97 125 0 (240-pin TAB QFP) D65895GL Mar 96Dec 96 150 0 (304-pin QFP FP) D65895S1 Mar 96Dec 96 100 0 (352-pin PBGA) 5J. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Jan 99Jun 99 D65832GD 150 0 (208-pin QFP)
0 0 0 0
240 120 144 72
0 0 0 0
0 0 0 0
60
20

Process Type CMOS-8L Process Period Qty Mar 96Jun 99 (cumulative) May 97Sep 97 May 97Sep 97 775 T/C Failures Cycles 100 0 300 0 Qty 636
PCT Failures Hours 96 0 192 0
5K. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN TEG 1 (304-pin QFP) TEG 2 (352-pin TBGA) 25 25 0 0 0 0 20 0 0 0 -
5L. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Jan 99Mar 99 D82174GD 50 0 (160-pin QFP) CB-C9 May 97Jun 99 (cumulative) Apr 98-Jun 98 100 0
0 0
40 60
0 0
0 0
5M. FABRICATED IN ROSEVILLE, ASSEMBLED IN JAPAN TEG 1 (304-pin QFP) D82286S1 (272-pin PBGA) D82287S1 (272-pin PBGA) CB-C9VX/VM 25 0 0 0 -
5N. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE Oct 98Dec 98 Jan 99Mar 99 Apr 98Jun 99 (cumulative) Apr 99Jun 99 Apr 99Jun 99 (cumulative) 231 25 281 0 0 0 0 0 0 231 20 251 0 0 0 0 0 0
5O. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D83901S1 (320-pin PBGA) UC-II 154 154 0 0 0 0 52 52 0 0 0 0
21
Table 6. Environmental and Mechanical Test Summaries (LI, SD, TS)

This table summarizes the environmental and mechanical test results of the different process types. The data is summarized for the current period and for past periods of cumulative data.
Process Process LI Type Period Qty No. of Fail 6A. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D67010L Jan 89Jun 97 0 (68-pin PLCC) D67010GF Jul 91Jun 97 0 (80-pin QFP) BICMOS Jan 89Jun 99 0 (cumulative) 6B. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65013GF Jul 88Jun 97 0 (100-pin QFP) D65022L Jul 88Jun 97 0 (68-pin PLCC) D65030L Oct 91Jun 97 0 (68-pin PLCC) D65031L Oct 89Jun 97 0 (84-pin PLCC) D65042L Apr 88Jun 97 0 (84-pin PLCC) D65070L Apr 88Jun 97 0 (68-pin PLCC) D65081L Jul 88Jun 97 0 (84-pin PLCC) 6C. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65012L Oct 92Jun 97 0 (64-pin PLCC) D65012GF Jan 92Jun 97 10 0 (80-pin QFP) D65013GF Jan 93Dec 97 0 (64-pin QFP) D65013GF Apr 91Sep 98 55 0 (100-pin QFP) D65022L Jan 92Jun 97 0 (64-pin PLCC) D65031 Sep 97Mar 98 0 (68-pin PLCC) D65031L Apr 95Jun 98 0 (84-pin PLCC) D65031GF Oct 91Jun 98 20 0 (100-pin QFP) D65032L Jul 91Jun 97 0 (84-pin PLCC) Qty 0 0 0 SD No. of Fail Qty 82 18 100 TS No. of Fail 0 0 0
0 0 0 0 0 0 0
76 58 18 18 138 48 10
0 0 0 0 0 0 0
5 10 10 55 5 10 40 25 5
0 0 0 0 0 0 0 0 0
18 36 0 180 18 0 126 72 54
0 0 0 0 0 0 0
22

Process Type D65042L (84-pin PLCC) D65042GF (80-pin QFP) D65042GF (100-pin QFP) D65070L (84-pin PLCC) D65081L (84-pin PLCC) D65081GF (100-pin QFP) CMOS-4 Process Period Jan 92Jun 97 Jan 93Jun 97 Jan 93Jun 97 Jan 95Sep 98 Apr 90Jun 97 Apr 94Jun 97 LI Qty 0 5 5 0 0 10 No. of Fail 0 0 0 Qty 10 5 5 15 10 10 225
SD No. of Fail 0 0 0 0 0 0 0 TS No. of Fail 1 0 0 0 0 0 1
Table 6. Environmental and Mechanical Test Summaries (LI, SD, TS) (continued)
Qty 36 18 36 36 54 72 1140
Apr 88Jun 99 105 0 (cumulative) 6D. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE D65032L Jan 90Jun 97 0 (84-pin PLCC) D65044L Jan 89Jun 97 0 (84-pin PLCC) D65103L Apr 91Jun 97 0 (68-pin PLCC) 6E. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65016GF Oct 93Jun 97 20 0 (80-pin QFP) D65016GD Jan 96Jun 97 5 0 (120-pin QFP) D65025L Oct 92Jun 97 0 (68-pin PLCC) D65025GF Jul 95Jun 97 10 0 (80-pin QFP) D65029GF Jul 91Jun 97 5 0 (100-pin QFP) D65031GF Jan 92Jun 97 5 0 (100-pin QFP) D65032L Jan 91Dec 97 0 (84-pin PLCC) D65044L Jul 94Jun 97 0 (68-pin PLCC) D65044L Oct 98Dec 98 0 (84-pin PLCC) D65046GD Jan 92Jun 97 40 0 (120-pin QFP)
0 0 0
126 72 18
0 0 0
20 4 15 10 5 5 20 0 5 40
0 0 0 0 0 0 0 0 0
90 18 90 36 18 18 108 36 0 126
0 0 0 0 0 0 0 0 0
23

Process Type D65046GD (136-pin QFP) D65046GD (160-pin QFP) D65051GD (120-pin QFP) D65061L (68-pin PLCC) D65061GF (100-pin QFP) D65061GD (136-pin QFP) D65062GD (136-pin QFP) D65062GD (160-pin QFP) D65082GD (160-pin QFP) D65103L (68-pin PLCC) D65103GD (80-pin QFP) D65103GD (160-pin QFP) D65180GD (160-pin QFP) CMOS-5 Process Period Oct 92Jun 97 Apr 91Mar 98 Jan 96Sep 98 Oct 96Sep 98 Jan 90Jun 97 Jan 91Jun 97 Jul 93Jun 97 Apr 93Jun 97 Apr 93Jun 97 Apr 90Jun 98 Jul 97Dec 97 Jan 93Jun 97 Jan 90Jun 97 LI Qty 35 10 25 0 5 50 5 10 5 0 5 5 5 No. of Fail 0 0 0 0 0 0 0 0 0 0 0 Qty 35 15 25 5 5 50 5 10 5 45 10 5 5 349
SD No. of Fail 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS No. of Fail 0 0 0 0 0 0 0 0 0 0 1 0 0 1
Qty 126 120 54 36 18 180 18 36 18 216 18 36 54 1710
Jul 88Jun 99 245 0 (cumulative) 6F. FABRICATED IN ROSEVILLE, ASSEMBLED IN ROSEVILLE D65622GF Apr 96Jun 97 5 0 (80-pin QFP) D65632 Sep 97Dec 97 0 (100-pin QFP) D65640GF Apr 97Jun 98 10 0 (80-pin QFP) D65640GF Jan 94Sep 98 40 0 (100-pin QFP) D65640GD Apr 92Sep 98 50 0 (120-pin QFP) D65646GF Jul 94Jun 97 10 0 (100-pin QFP) D65646GD Jul 95Jun 97 5 0 (136-pin QFP)
5 5 15 40 60 10 5
0 0 0 0 0 0 0
18 0 36 144 162 36 18
0 0 0 0 0 0
24

Process Type D65650GF (80-pin QFP) D65650GF (100-pin QFP) D65650GD (160-pin QFP) D65654GF (100-pin QFP) D65654GD (160-pin QFP) D65658GD (160-pin QFP) D65658GD (208-pin QFP) CMOS-6, 6A Process Period Jul 91Jun 97 Jul 93Jun 97 Jan 92Sep 97 Oct 93Jun 97 Jan 92Dec 98 Jan 91Dec 97 Apr 95Jun 97 Jul 88Jun 99 (cumulative) LI Qty 15 10 45 20 40 30 15 295 No. of Fail 0 0 0 0 0 0 0 0 Qty 15 10 45 20 39 35 25 329
SD No. of Fail 0 0 0 0 0 0 0 0 TS No. of Fail 0 0 0 0 0 0 0 0
Qty 54 36 234 72 126 108 108 1152
25

Table 7. Failure Summaries
CMOS-4
Test Item HTSL HTSL HTB T/H T/C HTB TS HTSL PCT PCT Duration 168 hrs 168 hrs 168 hrs 168 hrs 300 cyc 1000 hrs 15 cyc 168 hrs 96 hrs 96 hrs Period Jul 88Oct 88 Jul 88Oct 88 Jul 91Sep 91 Jan 93Apr 93 Apr 88Jun 88 Apr 96Jun 96 Apr 96Jun 96 Jul 96Sep 96 Oct 96Dec 96 Apr 97Jun 97
Failure 1 Functional Failure 1 Functional Failure 1 Functional Failure 1 Functional Failure 1 Functional Failure 1 Functional Failure 1 DC Failure 1 Functional Failure 1 DC Failure 7 Functional, 1 DC Failures
CMOS-5
Test Item T/H T/H T/H T/H T/C T/C T/C T/C PCT T/C PCT TS Duration 1000 hrs 1000 hrs 168 hrs 1000 hrs 300 cyc 300 cyc 300 cyc 100 cyc 192 hrs 100 cyc 96 hrs 15 cyc Period Jan 91Apr 91 Oct 95Dec 95 Jul 93Sep 93 Jul 92Sep 92 Jan 92Mar 92 Jan 94Mar 94 Jan 93Mar 93 Oct 96Dec 96 Oct 96Dec 96 Oct 96Dec 96 Apr 97Jun 97 Jul 97Sep 97 Failure 1 DC Failure 1 DC Failure 1 DC Failure 1 DC Failure 2 DC Failures 1 Functional Failure 1 Functional Failure 1 DC Failure 1 DC Failure 1 DC Failure 1 DC Failure 1 DC Failure
CMOS-6, 6A
Test Item HTSL PCT HHSL PCT T/C T/H T/H Duration 168 hrs 96 hrs 1000 hrs 96 hrs 300 cyc 1000 hrs 168 hrs Period Jul 92Sep 92 Oct 93Dec 93 Jan 93Apr 93 Jul 96Sep 96 Oct 96Dec 96 Oct 96Dec 96 Apr 97Jun 97 Failure 1 DC Failure 1 Functional Failure 1 Functional Failure 1 DC Failure 1 Functional Failure 1 DC Failure 1 Functional Failure
26
Table 8. CMOS-8L Process Family, Quarterly Reliability Data (Jan - Jun 99)
The following device types in all package types are covered in the CMOS-8L process family:
HTB Failures (Hours) 168 500 0 0 HTSL Failures (Hours) 168 500 0 0
Device Type D65832GD (208-pin QFP)
Time Period Jan 99Jun 99
Qty 72
1000 0
Qty 60
1000 0
Qty 60
PCT Failures (Hours) 96 192 0 0
Qty 150
T/C Failures (Cycles) 100 300 0 0
Qty 72
T/H Failures (Hours) 168 500 0 0
1000 0
Table 9. CB-C9 Process Family, Quarterly Reliability Data (Jan - Mar 99)
The following device types in all package types are covered in the CB-C9 process family:
HTB Failures (Hours) 168 500 HTSL Failures (Hours) 168 500 -
Time Period Jan 99Mar 99
Qty 0
1000 -
Qty 0
1000 -
Time Period Jan 99Mar 99
Qty 40
Qty 50
Qty 48
1000 0
27
Table 10. CB-C9VX/VM Process Family, Quarterly Reliability Data (Jan - Jun 99)
The following device types in all package types are covered in the CB-C9VX/VM process family:
HTB Failures (Hours) 168 500 0 0 HTSL Failures (Hours) 168 500 0 0
Device Type D82287S1 (272-pin PBGA)
Qty 160
1000 0
Qty 20
1000 0
Qty 20
Qty 25
Qty 72
1000 0
Table 11. UC-II Process Family, Quarterly Reliability Data (Apr - Jun 99)
The following device types in all package types are covered in the UC-II process family:
HTB Failures (Hours) 168 500 0 0 HTSL Failures (Hours) 168 500 -
Time Period Apr 99Jun 99
Qty 48
1000 0
Qty 0
1000 -
Time Period Apr 99Jun 99
Qty 52
Qty 154
Qty 48
1000 0
28

Quarterly Asic Reliability Report: Nec Electronics Inc. July 1999 TRQ-99-07-330

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NEC ELECTRONICS INC.

July 1999 TRQ-99-07-330

QUARTERLY ASIC RELIABILITY REPORT

NEC Electronics Inc.

NEC Electronics Inc.

Failure Rate Prediction Philosophy

Failure rate in %/1000 hours

2 The tabular value of chi-squared

2 value for confidence level of 60% and

C.L. = 60% C.L. = 90%

NEC Electronics Inc.

= 4.04 (for 60%

X 2 10 5 X 2 10 5 (% / 1000 hrs) = 2T 2(total device hrs)(accel factor)

(4.04) 10 5 = 0.0061 % / 1000 hrs 2(960)(1000)(34.6)

Therefore, 0.0061%10 9 1000 hrs

NEC Electronics Inc.

Test Item High-temperature bias life

Symbol HTB1 HTB2

MIL-STD 883C Method 1005

Test Conditions TA = 125C TA = 150C VDD = VDD max.

High-temperature storage life

HTSL1 HTSL2 HTSL3 HTSL4

High-temperature/highhumidity bias life

HHSL PCT T/C LI SD TS 1010 2004 2003 Note 4 1010 1011

Note 1 Note 1 Note 1 Note 2 Note 3

NEC Electronics Inc.

(65C to 150C, 20 cyc)

(85C/85% RH, 72 hrs)

: Bake time ! : Storage time: 2 58 hours 3 82 hours 7 178 hours Example

NEC Electronics Inc.

1.56 x 10 1.98 x 10 2.4 x 10 2.4 x 10 2.4 x 10

13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5 13.5

2.76 x 10 8.8 x 10 4.0 x 10 4.8 x 10

NEC Electronics Inc.

Equiv. Device Hours

Failure Rate 55C and 60% Confidence Level (Note 3)

144 312 48 72 168 120 48 72 144 24 48 72 96 120

1.68 x 10 1.20 x 10 4.8 x 10 7.1 x 10

1.44 x 10 2.4 x 10 4.8 x 10 9.6 x 10 9.6 x 10 1.2 x 10

1.68 x 10 2.64 x 10 1.20 x 10 2.4 x 10

13.5 13.5 13.5 13.5

13.5 13.5 13.5 13.5

NEC Electronics Inc.

Equiv. Device Hours

Failure Rate 55C and 60% Confidence Level (Note 3)

2.45 x 10 1.68 x 10 1.92 x 10 1.44 x 10 2.4 x 10

7.2 x 10 1.2 x 10 2.4 x 10 2.4 x 10 4.8 x 10 2.4 x 10

5.04 x 10 4.8 x 10 4.8 x 10

NEC Electronics Inc.

1.20 x 10 2.64 x 10 3.16 x 10 4.8 x 10 2.4 x 10 7.2 x 10 4.8 x 10

2.44 x 10 2.16 x 10 1.20 x 10 1.99 x 10

53.2 53.2 3.45 x 10

NEC Electronics Inc.

22.5 22.5 2.70 x 10

53.2 53.2 22.5 53.2 22.5 1.34 x 10

2.31 x 10 4.8 x 10 4.8 x 10 4.8 x 10

53.2 53.2 2.55 x 10

NEC Electronics Inc.

4A. FABRICATED IN JAPAN, ASSEMBLED IN ROSEVILLE