Texas Instruments TMS320 is a blanket name for a series of digital signal processors (DSPs) from Texas Instruments.

It was introduced on April 8, 1983 through the TMS32010 processor, which was then the fastest DSP on the market. The processor is available in many different variants, some with fixed-point arithmetic and some with floating point arithmetic. The floating point DSP TMS320C3x, which exploits delayed branch logic, has as many as three delay slots. The flexibility of this line of processors has led to it being used not merely as a co-processor for digital signal processing but also as a main CPU. Newer implementations support standard IEEE JTAG control for boundary scan and/or in-circuit debugging. The original TMS32010 and its subsequent variants is an example of a CPU with a Modified Harvard architecture, which features separate address spaces for instruction and data memory but the ability to read data values from instruction memory. The TMS32010 featured a fast multiply-andaccumulate useful in both DSP applications as well as transformations used in computer graphics. The graphics controller card for the Apollo Computer DN570 Workstation, released in 1985, was based on the TMS32010 and could transform 20,000 2D vectors/second.

TMS320C1x, the first generation 16-bit fixed-point DSPs. All processors in these series are code

compatible with the TMS32010 TMS32010, the very first processor in the first series introduced in 1983, using external TMS320M10, the same processor but with an internal ROM of 3KB TMS320C10, TMS320C15 etc. TMS320VC33 memory

TMS320C3x, floating point

TMS320C4x, floating point TMS320C8x, multiprocessor chip

TMS320C80 MVP (multimedia video processor) has a 32 bit floating-point "master

processor" and four 32-bit fixed-point "parallel processors". In many ways the Cell microprocessor followed this design approach.

The transputer was a pioneering microprocessor architecture of the 1980s, featuring integrated memory and serial communication links, intended for parallel computing. It was designed and produced by Inmos, a British semiconductor company based in Bristol.[1] For some time in the late 1980s many considered the transputer to be the next great design for the future of computing. While Inmos and the transputer did not ultimately live up to this expectation, the

transputer architecture was highly influential in provoking new ideas in computer architecture, several of which have re-emerged in different forms in modern systems.

Design
The transputer (the name deriving from transistor and computer[2]) was the first general purpose microprocessor designed specifically to be used in parallel computing systems. The goal was to produce a family of chips ranging in power and cost that could be wired together to form a complete parallel computer. The name was selected to indicate the role the individual transputers would play: numbers of them would be used as basic building blocks, just as transistors had earlier. Originally the plan was to make the transputer cost only a few dollars per unit. Inmos saw them being used for practically everything, from operating as the main CPU for a computer to acting as a channel controller for disk drives in the same machine. Spare cycles on any of these transputers could be used for other tasks, greatly increasing the overall performance of the machines. Even a single transputer would have all the circuitry needed to work by itself, a feature more commonly associated with microcontrollers. The intention was to allow transputers to be connected together as easily as possible, without the requirement for a complex bus (or motherboard). Power and a simple clock signal had to be supplied, but little else: RAM, a RAM controller, bus support and even an RTOS were all built in. [edit]Architecture The original transputer used a very simple and rather unique architecture to achieve a high performance in a small area. It used microcode as the principal method of controlling the data path but unlike other designs of the time, many instructions took only a single cycle to execute. Instruction opcodes were used as the entry points to the microcode ROM and the outputs from the ROM were fed directly to the data path. For multi-cycle instructions, while the data path was performing the first cycle, the microcode decoded four possible options for the second cycle. The decision as to which of these options would actually be used could be made near the end of the first cycle. This allowed for very fast operation while keeping the architecture generic. [3] The clock speed of 20 MHz was quite high for the era and the designers were very concerned about the practicalities of distributing a clock signal of this speed on a board. A lower external clock of 5 MHz was used and this was multiplied up to the required internal frequency using a phase-locked loop (PLL). The internal clock actually had four non-overlapping phases and designers were free to use whichever combination of these they wanted so it could be argued that the transputer actually ran at 80 MHz. Dynamic logic was used in many parts of the design to reduce area and increase speed. Unfortunately, these techniques are difficult to combine with automatic test pattern generation scan testing so they fell out of favour for later designs.

LAB 1
a1-a4

MUX
b1-b4 (2-to-1)

output(a1-a4/b1-b4)

sel Figure. 1 Objective: Code the behavior of a 2-to-1 MUX in VHDL. Logic: A multiplexer or a data selector is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. In figure 1, we see two input lines and one output line each of four bits wide. The selection of a particular input line is controlled by a set of control/selection lines (sel). Generally, there are 2n input lines and n selection lines. sel 0 1 Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( --First set of inputs a1,a2,a3,a4 :in std_logic;--a1 is MSB --Second set of inputs b1,b2,b3,b4 :in std_logic;--b1 is MSB --Selection line sel :in std_logic; --Output from the MUX output :out std_logic_vector(1 to 4) ); end entity mux; architecture Behavioral of mux is begin Multiplex: process(sel) begin if(sel='0') then output(4)<=a4; output(3)<=a3; output(2)<=a2; output(1)<=a1; else output a1-a4 b1-b4 Operation:

end if; end process Multiplex; end Behavioral;

LAB 2

(MSB) a3 00' carry_prop3 carry_gen3 b3 a2 carry_prop2 carry_gen2 b2 a1

(LSB) b1 carry_prop1 carry_gen1

carry3 output(4) output(3) Figure. 2

carry2 output(2)

carry1 output(1)

Objective: Code the behavior of 3 bit carry look-ahead adder in VHDL. Logic: Refer to Course Reader. The terms Gi, Pi, Ci, and Si used in the reader has been represented here as carry_geni, carry_propi, carryi, and output(i) respectively. Operation: The carry look-ahead adder depicted in figure 2 is in relation with the behavioral description given below Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adder_lookahead is Port( a1,a2,a3 :in std_logic;--a3 is MSB b1,b2,b3 :in std_logic;--b3 is MSB output :out std_logic_vector(4 downto 1) --Sum ); end entity; architecture Behavioral of adder_lookahead is signal carry_prop1,carry_prop2,carry_prop3 signal carry_gen1,carry_gen2,carry_gen3 signal carry1,carry2,carry3 begin process(a3,a2,a1,b3,b2,b1) begin carry_prop1<=a1 xor b1; carry_gen1<=a1 and b1; carry_prop2<=a2 xor b2; carry_gen2<=a2 and b2; carry_prop3<=a3 xor b3; carry_gen3<=a3 and b3; end process; :std_logic; :std_logic; :std_logic;

process(carry_prop1,carry_gen1) begin carry1<=carry_gen1 or (carry_prop1 and '0'); output(1)<=carry_prop1 xor '0'; end process; process(carry1)

begin carry2<=carry_gen2 or (carry_prop2 and carry1); output(2)<=carry_prop2 xor carry1; end process; process(carry2) begin

end process; process( begin )

--hint: carry from the previous stage would form the MSB of the sum [output(4)]

end process; end Behavioral;

LAB 3
0 0,1 1 1 0 1 0 0 1

Figure. 3 Objective: Code the behavior of the state machine described above in VHDL. This type of state machine is called

Logic: The state machine described above has five states. The final state (S5) is reached when the pattern 1001 is observed in the input stream. Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity state_machine is Port ( input output_state cclk reset accept_input ); end entity state_machine; architecture Behavioral of state_machine is type STATE_TYPE is (S1,S2,S3,S4,S5); signal STATE,NEXTSTATE : STATE_TYPE ; begin machine: process (input,accept_input,STATE) begin NEXTSTATE <= STATE ; case STATE is when S1 => if accept_input='1' then if input='0' then NEXTSTATE<=S1; else NEXTSTATE<=S2; end if; end if; :in std_logic; :out std_logic_vector(2 downto 0); :in std_logic; --CLOCK :in std_logic; :in std_logic

when S2

=> if accept_input='1' then if input='0' then NEXTSTATE<=S3; else NEXTSTATE<=S2; end if; end if;

when S3

=> if accept_input='1' then if input='0' then NEXTSTATE<=S4; else NEXTSTATE<=S2; end if; end if;

when S4

=>

when S5

=>

end case ; end process machine ; output_state <= "001" when STATE=S1 else "010" when STATE=S2 else "011" when STATE=S3 else "100" when STATE=S4 else "101" when STATE=S5; Reg: process (cclk,reset) begin if reset='1' then STATE <= S1 ; elsif cclk'event and cclk='1' then STATE <= NEXTSTATE ; end if ; end process Reg; end Behavioral ;

LAB 4
clk

count_value

COUNTER
(4-bit binary up/down)

output

select_up_down

reset Figure. 4

Objective: Code the behavior of a 4-bit binary up/down counter in VHDL. Logic: A counter is a combinational circuit that tallies or counts the number of input pulses (clk). Counters are fundamental components of digital systems. Digital counters are used in wide variety of applications, including pulse counting, frequency division, time measurement, control, and other timing operations. Figure 4, depicts an up/down configurable 4-bit binary counter. The maximum count or the minimum count value can be set for up count or down count respectively Operation:

select_up_down 1 0

operation Count-up Count-down

count_value X (max count) X(min count)

count -sequence counts up from 0000 to X counts down from 1111 to X

X- Any 4-bit binary combination Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is Port ( count_value select_up_down output clk reset ); end entity counter; :in std_logic_vector(3 downto 0);--Max or Min value :in std_logic; --'1' is up counter :out std_logic_vector(3 downto 0); :in std_logic;--CLOCK :in std_logic

architecture Behavioral of counter is signal count :std_logic_vector(3 downto 0):= 0000;--Initialization begin process(clk) begin if(clk='1'and clk'event) then if (reset='1') then count<=(others=>'0'); elsif(select_up_down='1') then --count UP if(count=count_value) then count<=(others=>'0'); else count<=count+1; end if; else--count DOWN if(count=count_value) then count<=(others=>'1'); else count<=count-1;

end if; end if; end if; end process; output<=count; end Behavioral;

Question) This signal assignment statement can be placed only after the process? Answer) a. Yes. As count is being modified inside the process, this signal assignment statement has to be after the execution of the process. b. No, location of any signal assignment statement (that are outside the process) does not
matter as VHDL is event driven.

LAB 5
clk reset

input1-input4

4-bit Shift
Register
reg(1)-reg(4) 1

output(1)-output(4)

input_accept

siso or sipo or piso or piso Figure. 5 Objective: Code the behavior of a 4-bit shift register in VHDL. Logic: Shift registers are used in digital systems for temporary information storage and for data manipulation or transfer. There are two ways to shift (store) data into a register i.e. serial or parallel, and similarly two ways to shift data out of the register. The following are the four basic modes of operation: MSB serial data input
Shift register (4 bits)

serial data output

serial data input

Shift register (4 bits)

parallel data outputs LSB

a. serial in-serial out (siso)

b. serial in-parallel out (sipo)

MSB parallel data inputs outputs LSB c. parallel in-serial out (piso)
Shift register (4 bits)

MSB serial data output parallel data inputs LSB

MSB parallel data LSB

d. parallel in-parallel out (pipo)

a. Serial in-Serial out: In this type of shift register, data is stored into the register one bit at a time (serial) and taken out serially too. b. Serial in-Parallel out: Here data is stored serially into the register and is taken out collectively at one shot (parallel). c. Parallel in-Serial out: In this case entire data is stored into the register in one shot and is taken out serially. d. Parallel in- Parallel out: Data is stored into the register at one go and is taken out collectively at one shot too. Operation:

Selection If siso=1 if sipo=1 If piso=1 If pipo=1

Operation Serial in-Serial out Serial in-Parallel out Parallel in-Serial out Parallel in-Parallel out

Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register is Port ( input1,input2,input3,input4 :in std_logic;--input 1 is MSB reg :inout std_logic_vector(1 to 4); output :inout std_logic_vector(1 to 4); input_accept :in std_logic; siso :in std_logic; sipo :in std_logic; piso :in std_logic; pipo :in std_logic; reset :in std_logic; clk : in std_logic ); end shift_register; architecture Behavioral of shift_register is signal count:std_logic_vector(2 downto 0):="000"; begin SHIFT_REG: process(clk) begin if clk'event and clk='1' then --Serial in-Serial out if siso='1' then if(reset='1') then count<="000"; reg<="0000"; output<="0000"; end if;--reset

if input_accept='1' then --Start serial in if count="000" then count<=count+1; reg<=input4 & "000";--(others=>'0'); elsif count="001" then count<=count+1; reg<=input3 & reg(1 to 3); elsif count="010" then count<=count+1; reg<=input2 & reg(1 to 3); elsif count="011" then count<=count+1; reg<=input1 & reg(1 to 3); ----Start serial out elsif count="100" then count<=count+1; output<=reg(4) & "000";--(others=>'0'); reg<='0' & reg(1 to 3);

elsif count="101" then count<=count+1; output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); elsif count="110" then output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); else output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); end if; end if;--input_accept ---Serial in-Parallel out elsif sipo='1' then if(reset='1') then count<="000"; reg<="0000"; output<="0000"; end if;--reset if input_accept='1' then --Start serial in if count="000" then count<=count+1; reg<=input4 & "000";--(others=>'0');

elsif count="001" then count<=count+1; reg<=input3 & reg(1 to 3); elsif count="010" then count<=count+1; reg<=input2 & reg(1 to 3); elsif count="011" then count<=count+1; reg<=input1 & reg(1 to 3); --Start parallel out else output<=reg; reg<="0000"; end if; end if;--input_accept

--Parallel in-Serial out elsif piso='1' then if(reset='1') then count<="000"; output<="0000"; reg<="0000"; end if;--reset if input_accept='1' then --Start parallel in if count="000" then count<=count+1; reg<=input1 & input2 & input3 & input4; ---Start serial out elsif count="001" then count<=count+1; output<=reg(4) & "000";--(others=>'0'); reg<='0' & reg(1 to 3); elsif count="010" then count<=count+1; output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); elsif count="011" then count<=count+1; output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); else

output<=reg(4) & output(1 to 3); reg<='0' & reg(1 to 3); end if; end if;--input_accept --Parallel in-Parallel out elsif pipo='1' then if(reset='1') then count<="000"; output<="0000"; reg<="0000"; end if;

if input_accept='1' then --Start parallel in if count="000" then count<=count+1; reg<=input1 & input2 & input3 & input4; else --Start parallel out output<=reg; reg<="0000"; end if; end if;--input_accept; end if;--end of select1,select2,select3,select4 end if;-- clk end process SHIFT_REG; end Behavioral;