Simatic S5: System Manual CPU 100/102/103

SIMATIC S5

S5-100U
Programmable Controller

System Manual
CPU 100/102/103

EWA 4NEB 812 6120-02a

STEP ® SINEC ® and SIMATIC ® are registered trademarks of Siemens AG.
LINESTRA® is a registered trademark of the OSRAM Company. IBM® is a
registered trademark of the International Business Machines Corporation.
Copyright© Siemens AG 1992

Subject to change without prior notice.
The reproduction, transmission or use of this document or its contents is not

permitted without express written authority. Offenders will be liable for
damages. All rights, including rights created by patent grant or registration of a
utility model or design, are reserved.
EWA 4NEB 812 6120-02

Index
Addressing
Appendices
Introduction
EWA 4NEB 812 6120-02

Module Spectrum
Function Modules
STEP 5 Operations
Technical Description
Installation Guidelines
Introduction to STEP 5
Analog Value Processing

Start-Up and Program Tests
The SIMATIC S5 System Family
Diagnostics and Troubleshooting
Integrated Blocks and Their Functions
Interrupt Processing, for CPU 103 Version 8MA02 and Higher
Connecting the S5-100U to SINEC L1, for CPU 102 and Higher
The Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher
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A/B/C
S5-100U Contents
Contents
Page
How to Use This Manual .............................................
1 The SIMATIC S5 System Family .................................. 1 - 1
2 Technical Description ......................................... 2 - 1
2.1 Programmable Controller Design ............................. 2 - 1
2.2 Principle of Operation for the Programmable Controller . . . . . . . . . . . . . . 2 - 3

2.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2.2.2 Mode of Operation for the External I/O Bus . . . . . . . . . . . . . . . . . . . . . . 2 - 6
3 Installation Guidelines ......................................... 3 - 1
3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.1.1 Assembling a Tier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3.1.2 Multi-Tier Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5
3.1.3 Cabinet Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3.1.4 Vertical Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3.2 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in ...... 3 - 9
3.2.2 Connecting the Power Supply to the S5-100U . . . . . . . . . . . . . . . . . . . . 3 - 12
3.2.3 Connecting Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
3.2.4 Connecting the Digital Input/Output Module . . . . . . . . . . . . . . . . . . . . . . 3 - 18
3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.3.1 Electrical Configuration for the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20
3.3.2 Electrical Configuration with External I/Os . . . . . . . . . . . . . . . . . . . . . . . 3 - 21
3.3.3 Non-Floating and Floating Configurations . . . . . . . . . . . . . . . . . . . . . . . . 3 - 25
3.4 Wiring Arrangement, Shielding, and Measures to

Guard against Electromagnetic Interference . . . . . . . . . . . . . . . . . . . . . . 3 - 29
3.4.1 Wiring Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 29
3.4.2 Shielding of Devices and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
3.4.3 Measures to Guard against Electromagnetic Interference . . . . . . . . . . . . 3 - 32
3.5 Protective Devices and Insulation Monitoring Devices . . . . . . . . . . . . . . . 3 - 36
EWA 4NEB 812 6120-02 v

Contents S5-100U
Page
4 Start-Up and Program Tests ..................................... 4 - 1
4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4.1.1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1
4.1.3 Performing an Overall Reset on the Programmable Controller . . . . . . . . . 4 - 2
4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4.2.1 Suggestions for Configuring and Installing the Product . . . . . . . . . . . . . . 4 - 3
4.2.2 Procedures for Starting Up the Programmable Controller . . . . . . . . . . . . 4 - 4
4.3 Loading the Program into the Programmable Controller . . . . . . . . . . . . . . 4 - 5
4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7

4.4.1 Backing Up the Program on a Memory Submodule ................ 4 - 7
4.4.2 Function of the Back-Up Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8
4.5 Program-Dependent Signal Status Display “STATUS” .............. 4 - 8
4.6 Direct Signal Status Display “STATUS VAR” ..................... 4 - 9
4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher ............... 4 - 10
4.8 Forcing Variables, “FORCE VAR” ............................ 4 - 10
4.9 Search Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11
4.10 Program Check, for CPU 103 and Higher ....................... 4 - 11
5 Diagnostics and Troubleshooting ................................ 5 - 1
5.1 Indication of Errors by LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2.1 “ISTACK” Analysis Function ................................ 5 - 1
5.2.2 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5.2.3 Errors during Program Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6
5.2.4 Explanation of the Mnemonics Used in “ISTACK” ................. 5 - 7
5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9

5.3.1 Locating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9
5.3.2 Tracing the Program with the “BSTACK” Function . . . . . . . . . . . . . . . . . 5 - 12
5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
5.6 The Last Resort ......................................... 5 - 15
vi EWA 4NEB 812 6120-02

S5-100U Contents
Page
6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.2 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4
6.3 Analog Modules ......................................... 6 - 5
6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . . . . . . 6 - 6

6.4.1 Output Modules with Error Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 6
6.4.2 Digital Input/Output Module, 16 Inputs, 16 Outputs, 24 V DC
for All CPUs Version 8MA02 and Higher and
for CPU 102, Version 8MA01, Revision 5 and Higher . . . . . . . . . . . . . . . 6 - 7
6.4.3 Function Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6.5 The Structure of Process Image Input and Output Tables . . . . . . . . . . . . 6 - 8

6.5.1 Accessing the Process Image Input Table (PII) . . . . . . . . . . . . . . . . . . . 6 - 10
6.5.2 Accessing the Process Image Output Table (PIQ) . . . . . . . . . . . . . . . . . 6 - 11
6.6 Interrupt Process Images Tables and Time-Controlled Program

Processing in OB13 for CPU 103, Version 8MA02 and Higher . . . . . . . . . 6 - 12
6.6.1 Accessing the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12
6.6.2 Accessing the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
6.7 RAM Address Assignments ................................. 6 - 15
7 Introduction to STEP 5 ......................................... 7 - 1
7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.1.1 Methods of Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1
7.1.2 Operand Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.1.3 Circuit Diagram Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2.1 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4
7.2.2 Structured Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5
7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3.1 Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7.3.2 Program Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.3 Sequence Blocks, for CPU 103 and Higher ..................... 7 - 11
7.3.4 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.5 Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

7.4.1 Program Processing with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7.4.2 START-UP Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7.4.3 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7.4.4 Time-Controlled Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 28
EWA 4NEB 812 6120-02 vii

Contents S5-100U
Page
7.4.5 Interrupt-Driven Program Processing, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 29
7.5 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30

7.5.1 Changing Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.2 Changing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.3 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.6 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 31
8 STEP 5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1
8.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

8.1.1 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.1.2 Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8.1.3 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8.1.4 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8.1.5 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8.1.6 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8.1.7 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8.1.8 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8.1.9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
8.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8.2.1 Load Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . 8 - 40
8.2.2 Enable Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . 8 - 41
8.2.3 Bit Test Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . 8 - 42
8.2.4 Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8.2.5 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8.2.6 Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8.2.7 Decrement/Increment, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 8 - 52
8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher . . . . . . 8 - 53
8.2.9 “DO” Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . 8 - 54
8.2.10 Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8.2.11 Substitution Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . 8 - 58
8.3 System Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . 8 - 64

8.3.1 Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.2 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.3 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8.3.4 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 68
8.4 Condition Code Generation ................................. 8 - 69
8.5 Sample Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71

8.5.1 Momentary-Contact Relay/Edge Evaluation . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.2 Binary Scaler/Binary Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.3 Clock/Clock-Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 73
viii EWA 4NEB 812 6120-02

S5-100U Contents
Page
9 Integrated Blocks and Their Functions ............................. 9 - 1
9.1 Assigning Internal Functions to DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.1 Configuration and Default Settings for DB1 . . . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.2 Setting the Address for the Parameter Error Code in DB1 . . . . . . . . . . . . 9 - 2
9.1.3 Assigning Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.4 Rules for Setting Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.5 How to Recognize and Correct Parameter Errors . . . . . . . . . . . . . . . . . . 9 - 6
9.1.6 Transferring DB1 Parameters to the Programmable Controller . . . . . . . . . 9 - 9
9.1.7 Reference Guide for Setting Parameters in DB1 .................. 9 - 10
9.1.8 Defining System Characteristics in DB1 . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
9.2 Integrated Function Blocks,

9.2.1 Code Converter : B4 - FB240 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9.2.2 Code Converter : 16 - FB241 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9.2.3 Multiplier : 16 - FB242 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.4 Divider : 16 - FB243 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.5 Analog Value Conditioning Modules FB250 and FB251 . . . . . . . . . . . . . . 9 - 14
9.3 Integrated Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14

9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher .............. 9 - 14
9.3.2 Battery Failure OB34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14
9.3.3 OB251 PID Algorithm,
10 Interrupt Processing, for CPU 103 Version 8MA02 and Higher .......... 10 - 1
10.1 Interrupt Processing with OB2, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10.2 Calculating Interrupt Reaction Times . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
11 Analog Value Processing ...................................... 11 - 1
11.1 Analog Input Modules .................................... 11 - 1
11.2 Connecting Current and Voltage Sensors to Analog

Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11.2.1 Voltage Measurement with Isolated or
Non-Isolated Thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11.2.2 Two-Wire Connection of Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . 11 - 3
11.2.3 Two-Wire Connection of Current Sensors . . . . . . . . . . . . . . . . . . . . . . 11 - 4
11.2.4 Connection of Two-Wire and Four-Wire Transducers . . . . . . . . . . . . . . 11 - 4
11.2.5 Connection of Resistance Thermometers . . . . . . . . . . . . . . . . . . . . . . 11 - 6
11.3 Start-Up of Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7
11.4 Analog Value Representation of Analog Input Modules ............. 11 - 11
EWA 4NEB 812 6120-02 ix

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11.5 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.5.1 Connection of Loads to Analog Output Modules . . . . . . . . . . . . . . . . . . 11 - 19
11.5.2 Analog Value Representation of Analog Output Modules . . . . . . . . . . . . 11 - 20
11.6 Analog Value Conversion: Function Blocks FB250 and FB251 . . . . . . . . 11 - 22

11.6.1 Reading in and Scaling an Analog Value - FB250 - . . . . . . . . . . . . . . . . 11 - 22
11.6.2 Outputting of Analog Values - FB251 - . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
12 The Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher ... 12 - 1
12.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 1
12.2 Setting Parameters in DB1, for CPU 103 Version 8MA03

and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.1 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.2 Reading the Current Clock Time and the Current Date . . . . . . . . . . . . . 12 - 3
12.2.3 DB1 Parameters Used for the Integral Real-Time Clock . . . . . . . . . . . . 12 - 4
12.3 Programming the Integral Real-Time Clock in DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . . . . 12 - 5
12.3.1 Setting the Clock in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 5
12.3.2 Setting the Prompt Time in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6
12.3.3 Setting the Operating Hours Counter in DB1 . . . . . . . . . . . . . . . . . . . . 12 - 7
12.3.4 Entering the Clock Time Correction Factor in DB1 . . . . . . . . . . . . . . . . 12 - 7
12.4 Structure of the Clock Data Area ............................ 12 - 8
12.5 Structure of the Status Word and How to Scan It ................. 12 - 12
12.6 Setting Parameters for the Clock Data Area and the Status Word
in the System Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 15
12.7 Programming the Integral Real-Time Clock in the

User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.1 Reading and Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.2 Programming the Prompt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 25
12.7.3 Programming the Operating Hours Counter . . . . . . . . . . . . . . . . . . . . . 12 - 30
12.7.4 Entering the Clock Time Correction Factor . . . . . . . . . . . . . . . . . . . . . 12 - 35
x EWA 4NEB 812 6120-02

S5-100U Contents
Page
13 Connecting the S5-100U to SINEC L1, for CPU 102 and Higher ......... 13 - 1
13.1 Connecting the Programmable Controllers to the

L1 Bus Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2 Setting Parameters in the Programmable Controller

for Exchanging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2.1 How to Program in a Function Block, for CPU 102 and Higher ....... 13 - 2
13.2.2 Setting Parameters in DB1, for CPU 103 and Higher . . . . . . . . . . . . . . 13 - 5
13.3 Coordinating Data Exchange in the Control Program . . . . . . . . . . . . . . . 13 - 7

13.3.1 Sending Data ......................................... 13 - 8
13.3.2 Receiving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 9
13.3.3 Programming the Messages in a Function Block . . . . . . . . . . . . . . . . . 13 - 11
14 Module Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 1
14.1 General Technical Specifications ............................ 14 - 1
14.2 Power Supply Modules ................................... 14 - 2
14.3 Central Processing Units ................................. 14 - 4
14.4 Bus Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 7
14.5 Interface Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 11
14.6 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 13

14.6.1 Digital Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 13
14.6.2 Digital Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 22
14.6.3 Digital Input/Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 32
14.7 Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 34

14.7.1 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 34
14.7.2 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 52
15 Function Modules ........................................... 15 - 1
15.1 Comparator Module 2×1 to 20 mA/0.5 to 10 V .................. 15 - 1
15.2 Timer Module 2×0.3 to 300 s .............................. 15 - 4
15.3 Simulator Module ....................................... 15 - 7
15.4 Diagnostic Module ...................................... 15 - 9
EWA 4NEB 812 6120-02 xi

Contents S5-100U
Page
15.5 Counter Module 2×0 to 500 Hz ............................. 15 - 12
15.6 Counter Module 25/500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 17

15.6.1 Installation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 20
15.6.2 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 25
15.6.3 Functional Description of the Counter Mode .................... 15 - 27
15.6.4 Functional Description of the Position Decoder . . . . . . . . . . . . . . . . . . 15 - 29
15.6.5 Entering New Setpoints for the Counter and
Position Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 38
15.6.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 39
15.7 Closed-Loop Control Module IP 262 . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 41
15.8 Positioning Module IP 266 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 45
15.9 Stepper Motor Control Module IP 267 ........................ 15 - 49
15.10 Communications Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 52

15.10.1 Printer Communications Module CP 521 . . . . . . . . . . . . . . . . . . . . . . 15 - 52
15.10.2 Communications Module CP 521 BASIC . . . . . . . . . . . . . . . . . . . . . . 15 - 55
Appendices
A Operations List, Machine Code, and List of Abbreviations .............. A - 1
A.1 Operations List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1

A.1.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1
A.1.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 8
A.1.3 System Operations, for CPU 102 and Higher . . . . . . . . . . . . . . . . . . . . . A - 13
A.1.4 Evaluation of CC 1 and CC 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 14
A.2 Machine Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 15

A.3 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 18
B Dimension Drawings .......................................... B - 1
C Active and Passive Faults in Automation Equipment .................. C - 1
D Information for Ordering Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D - 1
E Reference Materials ........................................... E - 1
F Siemens Addresses Worldwide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F - 1
Index
xii EWA 4NEB 812 6120-02

S5-100U How to Use This System Manual
How to Use This System Manual

The S5-100U is a programmable controller for lower and intermediate performance ranges. It meets
all the requirements for a modern programmable controller. To use this controller optimally, you
need detailed information.
In this system manual we have attempted to present this information as completely and as well
organized as possible. Certain information is repeated in various chapters so that you do not have
to leaf through the manual to find what you need.
This How to Use This System Manual section gives you information that will make it easier for you
to find what you need. This section explains how the manual is organized.
Contents of This System Manual

• Hardware Description (Chapters 1, 2, and 3)
These chapters describe the controllers: how they fit into the SIMATIC® S5 family of
programmable controllers, how they function, and how you install them.
• Start-Up Information (Chapters 4, 5, and 6)
These chapters summarize the information you need to start up your programmable controller.
These chapters describe how the hardware and software influence each other.
• The Programming Language of the Programmable Controllers (Chapters 7, 8, and 9)
These chapters describe the structure, operations, and structuring aids of the STEP® 5 pro-
gramming language.
• Functions of the Programmable Controllers (Chapters 10, 11, 12, 13)
Each of these chapters contains a complete description of a particular function, from wiring to
programming. Subjects include analog value processing, counter and interrupt inputs, integral
clock, and the programmable controller as a SINEC® L1 slave.
• Module Spectrum (Chapters 14 and 15)
These chapters contain information about all the currently available S5-100U modules that you
can use to expand your controller. Chapter 15, Function Modules, includes the modules that
require an extensive description (i. e., more than just technical specifications).
• Overviews (Appendices)
In these chapters you will find not only a complete list of operations but also dimension
drawings, a description of errors that may occur during operation of the programmable controller,
maintenance and repair procedures, a list of accessories, and reference literature about
programmable controllers.
You will find correction pages at the end of the system manual. Use them to indicate any
corrections, additions, or suggestions for improvement you might have. Send these suggestions to
us. They will help us to improve the next edition of this system manual.
EWA 4NEB 812 6120-02 xiii

How to Use This System Manual S5-100U
Conventions
This system manual is organized in menu form to make it easier for you to find information. This
means the following:
• Each chapter is marked with printed tabs.
• At the front of the system manual is an overview page that lists the title of each chapter.
Following this page, you will find a table of contents.
• At the beginning of each chapter is a table of contents for that chapter. Each chapter has three
level headings that are numbered. The fourth level heading is not numbered but appears in
boldface type.
• Pages, figures, and tables are numbered separately for each chapter. On the back of the table
of contents for each chapter you will find a list of the figures and tables that appear in that
chapter.
This system manual employs the following specific structuring devices:

• Specific terms have characteristic abbreviations (e. g., programmer is PG).
Appendix A contains a list of abbreviations.
• Footnotes are marked with a raised number (e. g., “1”) or a raised asterisk (“ * ”). You will find
the corresponding explanations in the lower margin of the page or under a figure or table if the
footnote appears in one of these.
• Lists are designated with bullets (• as in this particular listing) or with hyphens (-).
• Cross references are indicated as follows: (see section 7.3.2). There are no references to
specific page numbers.
• Dimensions in drawings are indicated in millimeters and inches.
• Value ranges are indicated as follows: 17 to 21 or 17-21.
• Especially important information appears in framed boxes such as the following:
Warning
You will find definitions for the terms “Warning,” “Danger,” “Caution,” and “Note” in the Safety-
Related Guidelines for the User at the end of the introduction.
xiv EWA 4NEB 812 6120-02

S5-100U How to Use This System Manual
Changes Made to the Second Edition of the S5-100U System Manual

(Order Number: 6ES5 998-0UB22)
S5-100U System Manual (Order Number 6ES5 998-0UB23) has been completely revised:
• The format was adapted to the other system manuals in the SIMATIC S5 family.
• The contents were updated and reorganized.
Some of the functions of CPU 103 have been expanded:

• The default settings (default parameters) for DB1 have been integrated into CPU 103
version 8MA03. This feature makes it easier for you to use the internal CPU functions.
The following chapters were included or completely revised in the system manual:
- Chapter 9 “Integrated Blocks and Their Functions”
- Chapter 12 “Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher”
- Chapter 13 “Connecting the S5-100U to SINEC L1, for CPU 102 and Higher”
The S5-100U system has been expanded to include an additional module:

• The “Communications Module CP 521 BASIC” is described in section 15.10.2.
Training
Siemens offers a wide range of training courses for SIMATIC S5 users. Contact your Siemens
representative for more information.
EWA 4NEB 812 6120-02 xv

How to Use This System Manual S5-100U
Safety-Related Guidelines for the User
This document provides the information required for the intended use of the particular product. The
documentation is written for technically qualified personnel.
Qualified personnel as referred to in the safety guidelines in this document as well as on the product
itself are defined as follows.
• System planning and design engineers who are familiar with the safety concepts of automation
equipment.
• Operating personnel who have been trained to work with automation equipment and are
conversant with the contents of the document in as far as it is connected with the actual
operation of the plant.
• Commissioning and service personnel who are trained to repair such automation equipment and
who are authorized to energize, de-energize, clear, ground, and tag circuits, equipment, and
systems in accordance with established safety practice.
Danger Notices
The notices and guidelines that follow are intended to ensure personal safety, as well as protect the
products and connected equipment against damage.
The safety notices and warnings for protection against loss of life (the users or service personnel) or
for protection against damage to property are highlighted in this document by the terms and
pictograms defined here. The terms used in this document and marked on the equipment itself have
the following significance.
Danger Warning
indicates that death, severe personal injury indicates that death, severe personal injury or
or substantial property damage will result if substantial property damage can result if
proper precautions are not taken. proper precautions are not taken.
Caution Note
indicates that minor personal injury or contains important information about the
property damage can result if proper product, its operation or a part of the doc-
precautions are not taken. ument to which special attention is drawn.
Proper Usage
Warning
• The equipment/system or the system components may only be used for the
applications described in the catalog or the technical description, and only in
combination with the equipment, components, and devices of other manu-
facturers as far as this is recommended or permitted by Siemens.
• The product will function correctly and safely only if it is transported, stored, set
up, and installed as intended, and operated and maintained with care.
xvi EWA 4NEB 812 6120-02

1 The SIMATIC S5 System Family
EWA 4NEB 812 6120-02

Figures
1-1 Members of the SIMATIC S5 System Family ...................... 1 - 1
EWA 4NEB 812 6120-02

S5-1OOU The S/MATIC S5 System Family
1 The SIMATIC S5 System Family
The programmable controllers (PLCS) in the SIMATIC S5 family offer economical solutions to simple
control tasks and to complex computer functions.
Figure 1-1. Members of the SIMATIC S5 System Family
The S5-1 OOU programmable controller is one of the smallest and most economical of the program-
mable controllers in the SIMATIC S5 family. The S5-1 OOU is especially suited for small automation
tasks. It is economical to use these programmable controllers if you want to replace more than five
control relays.
— EWA 4NEB 8126120-02 1-1

The SIMATIC S5 System Family S5-100U
The S5-100U has the following features:
• Modular Design
Depending on the CPU you use, the S5-100U allows you to have a maximum of 256 digital
inputs and outputs. It is suitable for machine control and for process automation and monitoring
on a medium scale. The S5-100U allows a broad expansion capability with various types of
modules to adapt optimally to a control task.
• Rugged, Lightweight Design

All of the modules you can use with the S5-100U are block-type modules that are small, rugged,
and easy to use. The modules operate without fans. None of these modules has electro-
magnetically sensitive electronics. The modules are plugged into bus units and screwed tightly
so that they are vibration-proof.
The bus units snap onto a standard mounting rail. You can configure the S5-100U in one or
more tiers and configure it vertically or horizontally. The S5-100U offers such a wide range of
configuration possibilities that you can use it in rough and difficult operating conditions.
• Simple Programming
The programming language is STEP 5 and its comprehensive operations set. It provides three
different methods of representation, - four, if you have a CPU 103 or higher.
You can use any of the U series programmers to program your S5-100U, or you can load
programs from memory submodules.
1-2 EWA 4NEB 812 6120-02

2 Technical Description
2.1 Programmable Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1
2.2 Principle of Operation for the Programmable Controller . . . . . . . . . 2 - 3

2.2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2.2.2 Mode of Operation for the External I/O Bus . . . . . . . . . . . . . . . . . 2 - 6
EWA 4NEB 812 6120-02

Figures
2-1 The S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1

2-2 Functional Units of the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2-3 Example of an Arithmetic Logic Unit’s Mode of Operation ............ 2 - 5
2-4 Accumulator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5
2-5 Structure of the External I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6
2-6 Data Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 7
Tables
2-1 Retentive and Non-Retentive Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5

2-2 Number of Bits per Module in the Shift Register . . . . . . . . . . . . . . . . . . . . 2 - 8
EWA 4NEB 812 6120-02

S5-1OOU Technical Description
2 Technical Description
This chapter describes the design and principle of operation for the S5-1OOU programmable
controller and its accessories.
2.1 Programmable Controller Design

The S5-1OOU belongs to the SIMATIC S5 range of programmable controllers. The S5-1 OOU
consists of various functional units (modules) that you can combine according to the task you want
to perform.
L
-. - . -,—I ne
— -,- . n-, ,
33-I uuu
I-lgure z-l.
0 Power supply module (PS 930)

This module is required if 24 V DC is not available for the CPU.
@ Central processing unit (CPU)

The CPU scans the control program. In the event of a power failure, a backup battery located in
the battery compartment saves the memory contents (9).
The control program can be stored in a memory submodule (7). The CPU has a serial port (8),
and you can connect a programmer, an operator panel, or a SINEC L1 bus to it.
EWA 4NEB 8126120-02 2-1

Technical Description S5-100U
Input/output modules
Input/output modules transfer information between the CPU and such process peripherals as
sensors, actuators, and transducers. You can use the following types of input/output modules
with your S5-100U:
• Digital input modules and digital output modules (4, 8, and 16/16 channel)
- Use these modules for simple control tasks involving signal states “0” and “1” only.
• Analog input modules and analog output modules
- Use these modules to record and generate such variable quantities as currents and
voltages.
• Timer module
- Use this module to set various times without having to change the program.
• Counter module
- Use this module to count pulses up to 500 Hz. You can input comparison values without
having to change the program.
• High-speed counter/position detection module
- Use the high-speed counter to record high-speed counter pulses of 25/500 kHz. You can
use this module for position detection in a positioning task.
• Comparator module
- This module makes it possible for you to monitor preset comparison values, such as for
current and voltage.
• Simulator module
- Use this module to generate digital input signals or to display digital output signals.
• Diagnostic module
- Use this module to check the function of the I/O bus.
• Communications module (CP)
- Use this module to output message texts with the date and clock time to a connected
printer. You can also use this module to connect to external systems.
• Intelligent I/O module (IP)
- Use these intelligent input/output modules for such special tasks as temperature control
and positioning tasks.
Bus units with terminal blocks (Crimp-snap-in or SIGUT, screw type)

Use bus units to connect the CPU to input/output modules. You can plug two input/output
modules into a single bus unit.
Interface modules (IM)

Use these modules to assemble your S5-100U in a multi-tier configuration.
Standard mounting rail

Mount your programmable controller on the standard mounting rail.
2-2 EWA 4NEB 812 6120-02

S5-100U Technical Description
2.2 Principle of Operation for the Programmable Controller
The remainder of this chapter explains how your S5-100U processes your program.
2.2.1 Functional Units
CPU
Process Interrupt
Program Timers Counters Flags I/O image process System
memory tables I/O image data
tables*
RAM
ROM
Memory
(operating submodule
system)
Processor
ALU Serial
(ACCU 1 and 2,
port
bit-ACCU (RLO))
I/O bus
Digital Analog
modules: modules: Function
- input - input modules
- output - output
I/O modules
* Beginning with CPU 103, version 8MA02
Figure 2-2. Functional Units of the S5-100U
EWA 4NEB 812 6120-02 2-3

Program Memory (EPROM/EEPROM)

In order to safely store the control program outside of your S5-100U, you must store it on an
EPROM or EEPROM memory submodule (see section 4.4).
Programs that are available on a memory submodule (EPROM or EEPROM) can be copied to the
internal program memory (see section 4.3). This internal program memory is a reserved area of the
CPU's internal RAM memory.
The internal RAM memory has the following characteristics:

• The memory contents can be changed quickly.
• Memory contents are lost when there is a supply voltage failure and there is no battery backup.
Operating System (ROM)

The operating system contains system programs that determine how the user program is executed,
how inputs and outputs are managed, how the memory is divided, and how data is managed.
The operating system is fixed and cannot be changed.
Process Image Tables (PII, PIQ)

Signal states of input and output modules are stored in the CPU in “process image tables”. Process
image tables are reserved areas in the RAM of the CPU.
Input and output modules have the following separate image tables:
• Process image input table (PII)
• Process image output table (PIQ)
Serial Interface
You can connect programmers, operator panels, and monitors to the serial port (cable connector).
You can use the serial port to connect your S5-100U as a slave to the SINEC L1 local area network.
Timers, Counters, Flags

The CPU has timers, counters, and flags available internally that the control program can use.
The program can set, delete, start, and stop the timers and counters. The time and count values are
stored in reserved areas of the RAM memory.
There is another area in the RAM memory where information such as intermediate results can be
stored as flags. You can address the flags by bits, bytes, or words.
If battery backup is available, then some of the flags and counters remain in the internal RAM
memory even if the supply voltage fails or your S5-100U is switched off. These flags and counters
are retentive.
2-4 EWA 4NEB 812 6120-02

Table 2-1 gives information about the number and retentive characteristics (the internal memory
contents are retained/are not retained) of these timers, counters, and flags.
Table 2-1. Retentive and Non-Retentive Operands
Retentive Non-Retentive
Operand
CPU 100 to 103 CPU 100 CPU 102 CPU 103
Flags 0.0 to 63.7 64.0 to 127.7 64.0 to 127.7 64.0 to 255.7
Counters 0 to 7 8 to 15 8 to 31 8 to 127
Timers 0 to 15 0 to 31 0 to 127
Arithmetic Unit
The arithmetic unit (ALU) consists of two accumulators, ACCU 1 and 2. The accumulators can
process byte and word operations.
Load Process Transfer

information information information
from the PII. in ACCU 1 and ACCU 2. to the PIQ.
Figure 2-3. Example of an Arithmetic Logic Unit’s Mode of Operation
Accumulator Design
ACCU 2 ACCU 1
15 8 7 0 15 8 7 0
High byte Low byte High byte Low byte
Figure 2-4. Accumulator Design
Processor
According to the control program, the processor calls statements in the program memory in
sequence and executes them. It processes the information from the PII and takes into consideration
the values of internal timers and counters as well as the signal states of internal flags.
External I/O Bus

The I/O bus is the electrical connection for all signals that are exchanged between the CPU and the
S5-100U modules in a programmable controller.
EWA 4NEB 812 6120-02 2-5

2.2.2 Mode of Operation for the External I/O Bus
The S5-100U has a serial bus for the transfer of data between the CPU and the I/O modules. This
serial bus has the following characteristics:
• The modular design permits optimal adaptation to the particular control task.
• No addresses have to be set on the I/O modules.
• A terminating resistor connector is not required.
• Direct access to individual modules is not possible.
A number of shift registers moves the data (Figure 2-5).
Four data bits and one check bit for bus monitoring are assigned to each slot in the bus unit. All
modules requiring more than four data bits have their own shift register and therefore do not have to
use the shift register of the particular slot.
Slot number Data ring bus
CPU
0 1 2 3
5 Bits
Shift register
of a slot
Shift register of an
8-channel digital module n x 5 Bits
or of an analog module n=2, 4, 6 to 16
Figure 2-5. Structure of the External I/O Bus
2-6 EWA 4NEB 812 6120-02

Data Cycle
Prior to a program scan, the external I/O bus transfers current information from the input modules to
the process image input table (PII). At the same time, information contained in the process image
output table (PIQ) is transferred to the output modules.
Data cycle
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Shift Program scanning Shift

data data
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Time axis
Transfer data from the shift register to
the output modules.
Load data from the input

modules into the shift register.
Figure 2-6. Data Cycle
Interrupt Data Cycle, for CPU 103 version 8MA02 and higher
There is an interrupt input data cycle prior to each time-controlled or interrupt-driven program scan.
Before a time-controlled program scan, current information about the input modules is read into the
interrupt PII. Before an interrupt-driven program scan, interrupt inputs on slots 0 and 1 only are read
into the interrupt PII.
Following a time-controlled program scan, there is not an interrupt output data cycle until data has
been moved into the interrupt PIQ via a transfer operation (see section 8.1.3).
Information is output from the interrupt PIQ to the output modules during an interrupt output data
cycle. The PIQ is updated.
EWA 4NEB 812 6120-02 2-7

Length of the Shift Register

The total length of the shift register is obtained from the sum of the data bits of all plugged-in
modules and of the empty slots. The check bit is not counted.
You must know the length of the shift register to be able to determine the data cycle time. Data
cycle time is 25 µs x number of data bits.
Table 2-2. Number of Bits per Module in the Shift Register
Plugged-in Module Number of Data Bits
Diagnostic module or vacant slot 4
4-channel digital input and output modules 4
500 Hz comparator module, 500 Hz timer module, 4

500 Hz counter module
25 KHz counter module 32
8-channel digital input and output modules 8
Digital input and output module, 16 inputs/16 outputs 16
Simulator module 8
Analog modules for each activated channel 16*
CP 521, IP 262, IP 266, IP 267 64
Refer to the individual manuals for information on other modules.
* This does not apply to the 466-8MC11 analog input module (8 data bits).
The CPU specifies the maximum length of the shift register in a particular configuration.
• CPU 100: 256 data bits, 128 (max.) of these from analog modules
Note
If the maximum expansion allowed is exceeded, the S5-100U goes into the STOP mode.
The “PEU” bit (I/O not ready) is set in the ISTACK.
2-8 EWA 4NEB 812 6120-02

Examples:
a) CPU 100: This CPU lets you operate six digital modules (8-channel) and two analog modules
(4-channel):
[6 x 8+2 x (4 x 16)]=48+128<256
b) CPU 100: This CPU does not let you use three digital modules (8-channel) with three analog
modules (4-channel) because the maximum permissible number of analog data bits
would be exceeded:
[3 x 8+3 x (4 x 16)]=24+192<256
c) CPU 102: This CPU lets you operate seven digital modules (8-channel) and four analog
modules (4-channel):
[7 x 8+4 x (4 x 16)]=56+256<480
d) CPU 102: This CPU does not let you use 20 digital modules (8-channel) with 5 analog
modules (4-channel) because the maximum permissible number of analog data bits
would be exceeded:
[20 x 8+5 x (4 x 16)]=160+320=480
e) CPU 103: This CPU lets you operate 24 digital modules (8-channel) and eight analog modules
(4-channel):
[24 x 8+8 x (4 x 16)]=192+512=704
f) CPU 103: This CPU does not let you use 31 digital modules (8-channel) with four analog
modules (2-channel) because the maximum permissible number of slots would be
exceeded:
[31 x 8+4 x (2 x 16)]=248+128<704
EWA 4NEB 812 6120-02 2-9

3 Installation Guidelines
3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.1.1 Assembling a Tier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
3.1.2 Multi-Tier Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5
3.1.3 Cabinet Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3.1.4 Vertical Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3.2 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in . . 3 - 9
3.2.2 Connecting the Power Supply to the S5-100U . . . . . . . . . . . . . . . 3 - 12
3.2.3 Connecting Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
3.2.4 Connecting the Digital Input/Output Module . . . . . . . . . . . . . . . . . 3 - 18
3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.3.1 Electrical Configuration for the S5-100U . . . . . . . . . . . . . . . . . . . . 3 - 20
3.3.2 Electrical Configuration with External I/Os . . . . . . . . . . . . . . . . . . . 3 - 21
3.3.3 Non-Floating and Floating Configurations . . . . . . . . . . . . . . . . . . . 3 - 25
3.4 Wiring Arrangement, Shielding, and Measures to . . . . . . . . . . . . . 3 - 29

Guard against Electromagnetic Interference
3.4.1 Wiring Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 29
3.4.2 Shielding of Devices and Cables . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
3.4.3 Measures to Guard against Electromagnetic Interference . . . . . . . . 3 - 32
3.5 Protective Devices and Insulation Monitoring Devices .......... 3 - 36
EWA 4NEB 812 6120-02

Figures
3-1 Mounting the PS 930 Power Supply Module . . . . . . . . . . . . . . . . . . . . . . . 3 - 2

3-2 Removing Bus Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3
3-3 Coding System to Prevent an Inadvertent Interchange of Modules . . . . . . . . 3 - 4
3-4 Interconnecting Tiers with Interface Modules (6ES5 316-8MA12) ........ 3 - 5
3-5 Multi-Tier Configuration in a Cabinet with the
IM 316 Interface Module (6ES5 316-8MA12) . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
3-6 Cabinet Mounting with a Series of Devices . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3-7 Vertically Mounting a Programmable Controller . . . . . . . . . . . . . . . . . . . . . . 3 - 8
3-8 SIGUT/Screw-Type Connection Method . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
3-9 Mounting the Crimp Snap-in Terminal ........................... 3 - 10
3-10 Disconnecting a Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11
3-11 Connecting a Power Supply Module and a CPU . . . . . . . . . . . . . . . . . . . . . 3 - 12
3-12 Two-Wire Connection of a Sensor to Channel 2 . . . . . . . . . . . . . . . . . . . . . 3 - 14
3-13 Two-Wire Connection of a Lamp to Channel 3 . . . . . . . . . . . . . . . . . . . . . . 3 - 15
3-14 Connecting a Sensor to Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 16
3-15 Connecting a Lamp to Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 17
3-16 Front View of the Digital I/O Module with a Crimp Snap-In Connector
(simplified view and not true to scale) ........................... 3 - 18
3-17 Connecting a Sensor and a Load to Digital Input/Output Module 482 . . . . . . 3 - 19
3-18 Configuration Possibility: S5-100U with 115/230 V AC Power Supply
for Programmable Controller, Sensors, and Actuators . . . . . . . . . . . . . . . . . 3 - 22
3-19 Configuration Possibility: S5-100U with 24 V DC Power Supply (with Safe
Electrical Isolation According to DIN VDE 0160) for Programmable
Controller, Sensors, and Actuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 23
3-20 Non-Grounded Operation; 24 V DC Power Supply (with Safe Electrical Iso-
lation According to DIN VDE 0160) for Programmable Controller and I/Os . . . 3 - 24
3-21 Example: Non-Floating Connection of I/Os to the S5-100U . . . . . . . . . . . . . 3 - 25
3-22 Simplified Representation of a Non-Floating I/O Connection . . . . . . . . . . . . 3 - 26
3-23 Simplified Representation of a Galvanically Isolated Connection
of the I/Os to the S5-100U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 27
3-24 A Simplified Representation of a Floating I/O Connection . . . . . . . . . . . . . . 3 - 28
3-25 Layout of the Interference-Suppression Capacitors . . . . . . . . . . . . . . . . . . . 3 - 33
3-26 RC Circuits for Coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 34
3-27 How to Reduce Noise Interference Caused by Fluorescent Lamps
in a Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 35
3-28 Layout of Elements to Protect against Lightning . . . . . . . . . . . . . . . . . . . . . 3 - 37
Tables
3-1 Installing, Removing, and Changing S5-100U Components . . . . . . . . . . . . 3 - 1

3-2 Connecting the Load Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 13
EWA 4NEB 812 6120-02

S5-100U Installation Guidelines
3 Installation Guidelines
3.1 Installing S5-100U Components
Except for the I/O module, all of the S5-100U components are mounted on standard mounting rails
in accordance with DIN EN 50022-35x15. Mount the rails on a metal plate to obtain the same
reference potential.
Bus units with a SIGUT/screw-type, or crimp snap-in connection method have different heights.
If you install, remove, or change any parts of your S5-100U system, your system must be in the
state indicated in Table 3-1.
Table 3-1. Installing, Removing, and Changing S5-100U Components

Installing, Removing, and S5-100U S5-100U Load
Changing: Power Status Operating Mode Voltage
I/O modules X STOP OFF
Bus units Power OFF X X

Interface modules
Power supply X X
CPU power supply
voltage OFF
X=not relevant
3.1.1 Assembling a Tier

You need the following components to configure the S5-100U:
• Power supply module
• Central processing unit
• Bus units
• I/O modules
If you do not have a 24 V DC power supply, you must have a power supply module.
Mount the first module on the extreme left end of the standard mounting rail. Add other modules to
the right of the first module.
EWA 4NEB 812 6120-02 3-1

Installation Guidelines S5-1OOU
Mounting the PS 930 Power Supply Module

—
The backplane design makes it easy to attach this module to the standard mounting rail.
1. Hook the module onto the standard mounting rail.

2. Swing the module back until the slide snaps into place (see Figure 3-l).
Figure 3-1. Mounting the PS 930 Power Supply Module
Removing the PS 930 Power Supply Module

1. Turn off the 115 V1230 V AC power supply.
2. Remove the connections between the CPU and the power supply module.
3. Use a screwdriver to press down on the slide on the bottom of the module.
4. Swing the module up and out of the standard mounting rail.
Mounting the Central Processing Unit

Follow the same procedure you used to mount the PS 930 power supply module (see Figure 3-1).
1. Hook the CPU onto the rail and to the right of the power supply module.
2. Swing the CPU back until the slide snaps into place.
3-2 EWA 4NEB 8126120-02

S5-1OOU Installation Guidelines
Removing the CPU

1. Remove the 1/0 module located at slot “0”.
2. Pull the connection (ribbon cable) between the CPU and the first bus unit.
3. Pull the connections between the CPU and the power supply module.
4. Use a screwdriver to press down on the slide on the bottom of the module
Mounting Bus Units

3
Use the same procedures to mount the bus unit that you used to mount both the power supply
module and the CPU. Hooks are located on the sides of each bus unit. These hooks are used to
connect bus units to each other and to connect bus units to the CPU.
Connecting Bus Units to Each Other or to the CPU

—
1. Pull the ribbon cable connector located on the top left of the bus unit out of its holder.
2. Plug the connector either into the receptacle located on the right side of the CPU or into the
receptacle of the adjacent bus unit located on the left (see Figure 3-2).
Removing Bus Units

1. Pull the connections to the neighboring bus units or to the CPU.
2. Use a screwdriver to press down on the slide.
Figure 3-2. Removing Bus Units
EWA 4PIEB 8126120-02 3-3

—
Installation Guidelines S5- Ioou
Plugging input and Output Modules into the Bus Units

—
Before you plug in an input or output module, you must set the bus unit’s coding element to match
the module type.
Setting the Coding Element

An identification number is printed on the front plate of every 1’0 module. Depending on the
particular module type, the number is between two and eight. There is a white mechanical coding
key located on the back of each module. The position of the coding key is determined by the
module type and cannot be changed. The bus unit has a mating component for each key, a white
rotating coding element or “lock” (see Figure 3-3).
Use a screwdriver to set the “lock” on the bus unit to the corresponding 1/0 module code number.
Figure 3-3. Coding System to Prevent an Inadvertent Interchange of Modules
The 6ES5 788-8MA11 simulator module does not have a coding key. You can plug in this simulator
module in place of any module.
Attaching 1/0 Modules

1. Hook the module onto the top of the bus unit.
2. Swing the module down onto the bus unit.
3. Press the module down firmly.
4. Tighten the hold-down screw on the front of the module to attach the module to the bus unit.
Removing l/O Modules

Remove the hold-down screw and swing the module up and out of the bus unit.
3-4 EWA 4NEB 8126120-02

3.1.2 Multi-Tier Expansion

-.
If it is not possible to have all of the modules located on one tier, you can expand the configuration
up to four tiers. You may use a maximum of 16 bus units. It does not matter how many bus units
are mounted on a tier. You need one interface module per tier to interconnect the tiers.
Install an interface module as you would install a bus unit. You must connect each interface module
to the last bus unit via the ribbon cable.
Use the IM 315 interface module for two-tier configurations. The IM 315 consists of two modules
permanently connected to each other via a 0.5-m (20-in. ) cable.
Use the IM 316 interface modules for multi-tier configurations. Use the 712-8 connecting cable to
connect the IM 316 interface modules (Order No. 6ES5 712-8...).
The standard mounting rails must have a common reference potential if they are mounted in
different cabinets.
Figure 3-4. Interconnecting Tiers with Interface Modules (6ES5 316-8 MA12)
EWA 4NEB 8126120-02 3-5

Installation Guidelines S5-100U
Installing an Interface Module

1. Hook the interface module to the standard mounting rail.
2. Swing the interface module back until the slide on the bottom snaps into place on the rail.
3. Use the ribbon cable to connect the module to the last bus unit.
4. Use connecting cable 712-8 to join the two interface modules.
5. Connect the cable to the “out” socket on the programmable controller tier and to the “in” socket
on the expansion tier.
6. Securely screw the connecting cable plugs in place. Use two screws for each connecting cable
plug.
Removing an Interface Module

1. Only for the IM 316: Remove the hold-down screws from the plugs and remove the connecting
cable.
2. Remove the connecting ribbon cable from the adjacent bus unit.
3. Use a screwdriver to press down on the slide located on the bottom of the interface module.
3-6 EWA 4NEB 812 6120-02

3.1.3 Cabinet Mounting
Make sure that the S5-100U, the power supply, and all modules are well grounded. Mount the
S5-100U on a metal plate to help prevent noise. There should be electrical continuity between the
grounded enclosure and the mounting rails. Make sure that the system is bonded to earth.
You can use the 8LW system or the 8LX system mounting plates (see Catalog NV 21).
Adequate ventilation and heat dissipation are important to the proper operation of the system. You
must have at least 210 mm (8.3 in.) between each mounting rail (see Figures in Appendix B) for
proper ventilation.
Always locate the power supply and the CPU on the lowest tier to ensure better heat dissipation.
To measure cabinet ventilation, define the total heat loss by calculating the sum of all typical heat
losses (see Catalog ST 52.1).
IM 316 interface module

Metal plate
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CPU
Figure 3-5. Multi-Tier Configuration in a Cabinet with the IM 316 Interface

Module (6ES5 316-8MA12)
EWA 4NEB 812 6120-02 3-7

Wiring devices
and/or cable duct
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Figure 3-6. Cabinet Mounting with a Series of Devices
3.1.4 Vertical Mounting

You can also mount the standard mounting rails vertically and then attach the modules one over the
other. Because heat dissipation by convection is less effective in this case, the maximum ambient
temperature allowed is 40 °C (104 °F).
Use the same minimum clearances for a vertical configuration as for a horizontal configuration.
You must install a clamp (see Catalog SA 2) on the lower end of the programmable controller tier to
hold the modules mechanically in position.
PLC
Clamp
Figure 3-7. Vertically Mounting a Programmable Controller
3-8 EWA 4NEB 812 6120-02

3.2 Wiring
3.2.1 Connection Methods: Screw-Type Terminals and Crimp Snap-in
SIGUT Screw-Type Terminal

When using screw-type terminals, you can clamp two cables per terminal. It is best to use a
3.5-mm screwdriver to tighten the screws.
Permissible cable cross-sections are:

• A stranded conductor with a core end sleeve: 2 x 0.5 to 1.5 mm2
• A solid conductor: 2 x 0.5 to 2.5 mm2
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M3 screw
Wire clamp
Cables
Figure 3-8. SIGUT/Screw-Type Connection Method
EWA 4NEB 812 6120-02 3-9

Installation Guidelines S5-IOOU
Crimp Snap-in Terminals

Bus units using the crimp snap-in connection method have the same height as the CPU.
You can connect stranded conductors with a cross-section of 0.5 to 1.5-mmL to these terminals.
Connecting the Contact to the Terminal Block

Refer to Figure 3-9 and perform the following steps to connect the contact to the terminal block.
1. Remove the module that is plugged into the bus unit.
2. Use a screwdriver to press down on the terminal block (1).
3. Swing the terminal block up. The rear side is now visible (2).
4. Push the contact into the desired opening until the locating spring engages.
Caution: The spring must point into the slot.
5. Pull lightly on the cable to make certain that the contact is properly engaged.
6. Swing the terminal block back into its original position.

7. Press up on the terminal block until it snaps into position.
—-.
“.. ~”’
Figure 3-9. Mounting the Crimp Snap-in Terminal
3-1o EWA 4NEB 8126120-02

Disconnecting a Terminal
1. Position the terminal block as is shown in Figure 3-10.
2. Insert the extraction tool into the slot beside the terminal so that you can compress the barb.
3. Position the cable in the groove on the extraction tool and pull out both the tool and the cable.
4. Realign the deformed barb so that you can use the terminal again.
Figure 3-10. Disconnecting a Terminal
EWA 4NEB 8126120-02 3-11

Installation Guidelines S5-1OOU
3.2.2 Connecting the Power Supply to the S5-1OOU

Power Supply Module
1. Set the voltage selector to the supply voltage you are using.
2. Swing up the protective cover.
3. Connect the supply cable to terminals Ll, N and+( see Figure 3-1 1),
4. Close the protective cover.
Figure 3-11. Connecting a Power Supply Module and a CPU
CPU
1. Connect the L + and M terminals of the PS 931 power supply module to the corresponding
terminals on the CPU (see Figure 3-23).
2. Connect the ~ terminal of the CPU to the standard mounting rail.
3-12 EWA 4NEB 8126120-02

3.2.3 Connecting Digital Modules
All I/O modules are plugged into bus units. Connect the I/O modules to the terminal blocks of the
bus units. The connections illustrated in this section are of the screw terminal type (SIGUT
connection method).
You can also use the crimp snap-in connection method described in section 3.2.1. In both cases,
the terminal assignments are marked on the terminal blocks.
The assignments listed in Table 3-2 always apply for connecting the load voltage.
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Table 3-2. Connecting the Load Voltage
Load Voltage Terminal 1 Terminal 2
24 V DC L+ M
115/230 V AC L1 N
Note
For digital outputs, energy is temporarily stored in an internal capacitor for about
100 ms after the L+ supply is switched off.
Please note that this energy may be sufficient to activate low-rating loads (e.g., pulse
valves) for a triggered output.
EWA 4NEB 812 6120-02 3-13

Connecting Four-Channel Digital Modules

All of these modules are designed for a two-wire connection. You can therefore wire directly to the
sensor or output field device. An external distribution block is not required.
The four channels of a module are numbered from .0 through .3. (Numbers .4 through .7 are only
significant for the ET 100 distributed I/O system.) Each channel has a pair of terminals on the ter-
minal block.
The terminal assignments and the connection diagram are printed on the front plate of the module.
Connecting Four-Channel Input Modules

Example: Connecting a sensor to channel 2 (address I 3.2) on the input module in slot 3
(see Figure 3-12)
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2
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DIGITAL INPUT
4 x 24 - 60 V DC
6ES5 430-8MB11
1 2 3 4 5 6
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Figure 3-12. Two-Wire Connection of a Sensor to Channel 2
3-14 EWA 4NEB 812 6120-02

S5-100U
1
2
3
F
.7
.3
.6
.2
.5
.1
.4
.0
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EWA 4NEB 812 6120-02

aaaaa aaaaa aaaaa aaaaa
4
5
8
7
6
5
4
3
2
1
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9
6ES5 440-8MA21
4 x 24 V DC/2 A
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6
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M
L+
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DIGITAL OUTPUT
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(see Figure 3-13)

Connecting Four-Channel Output Modules
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Figure 3-13. Two-Wire Connection of a Lamp to Channel 3

8
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Example: Connecting a lamp to channel 3 (address Q 1.3) on the output module in slot 1
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3-15
Connecting Eight-Channel Digital Modules

These modules do not have a two-wire connection. You therefore need an external distribution
block.
The eight channels of a module are numbered from .0 through .7. One terminal on the terminal
block is assigned to each channel. The terminal assignment and the connection diagram are printed
on the front plate of the module.
Connecting Eight-Channel Input Modules

The sensors must be connected to terminal 1 via the L+ terminal block.
Example: Connecting a sensor to channel 4 (address I 3.4) on an input module in slot 3

(see Figure 3-14)
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8 x 24 V DC L+ M
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Figure 3-14. Connecting a Sensor to Channel 4
3-16 EWA 4NEB 812 6120-02

S5-100U
1 2
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.7
.6
.5
.4
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.2
.1
.0
3
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EWA 4NEB 812 6120-02

4
9
7
8
5
6
3
4
2
1
10
5
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6ES5 441-8MA11
8 x 24 V DC/0.5 A
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(see Figure 3-15)

Connecting Eight-Channel Output Modules
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5
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Figure 3-15. Connecting a Lamp to Channel 6

6
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apply to the digital output module 8× 5 to 24 V DC/0.1 A (see section 14.6.2).

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7
aaaaaaaa
M Terminal
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8
aaaaaaaa
aaaaaaaa
9
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aaaa
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10
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aaaaaaaa
The actuators must be connected to terminal 2 via the M (negative) terminal block. This does not
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Lamp
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3-17
Example: Connecting a lamp to channel 6 (address output Q 5.6) on an output module in slot 5
3.2.4 Connecting the Digital Input/Output Module

Use only slots 0 through 7 when you plug the module into the bus unit. Use a 40-pin cable
connector with a screw-type connection or crimp snap-in connection for wiring. The module does
not have a two-wire connection. You must therefore use an external distribution block.
Every channel is assigned a terminal on the 40-pin connector. The channel numbers are printed on
the front plate.
The 16 channels on the input side (IN) are numbered from n.0 through n.7 and from n+1.0 through
n+1.7. The 16 channels on the output side (OUT) are numbered from n.0 through n.7 and from
n+1.0 through n+1.7. “n” is the start address of the slot. Slot 0, for example, has the start
address of n=64 (see chapter 6).
OUT IN
aaaaaaaa
aaaa
L+ 1 b 1 L+
n+1 n+1
.0 2 2 .0
.1 3 3 .1
.2 4 4 .2
.3 0,1 A 5 5 .3
.4 6 6 .4
.5 7 7 .5
.6 8 8 .6
.7 9 9 .7
M 10 10 NC
n L+ 11 11
n NC
.0 12 12 .0
.1 13 13 .1
.2 14 14 .2
.3 0,5 A
15 15 .3
.4 16 16 .4
.5 17 17 .5
.6 18 18 .6
.7 19 19 .7
M 20 20 M
40-pin crimp
snap-in connector
Figure 3-16. Front View of the Digital I/O Module with a Crimp Snap-In Connector
(simplified view and not true to scale)
3-18 EWA 4NEB 812 6120-02

Example: The start address for the modules is 6.0. Inputs and outputs have the same address.
A sensor is to be connected to input I 6.4 and a lamp to output Q 7.3.
Figure 3-17 illustrates the wiring on the front connector.
OUT IN
L+ L+
1 1
2 2
3 3
A 7.3 4 4
5 5
6 6
7 7
8 8
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aaaaa
M 9 9
10 10
11 11
12 12
13 13
14 14
15 15 E 6.4
16 16
17 17
18 18
19 19 M
20 20
L+ Lamp
M M
Sensor
L+
M Terminal
L+Terminal
Figure 3-17. Connecting a Sensor and a Load to Digital Input/Output Module 482
Note
Chapter 11 describes how to connect analog modules.
EWA 4NEB 812 6120-02 3-19

3.3 Electrical Configuration
3.3.1 Electrical Configuration for the S5-100U

Power Supply
The entire control for the S5-100U consists of the following separate electrical circuits:
• Control circuit for the S5-100U (24 V DC)
• Control circuit for the sensors (24 V DC)
• Load circuit for the actuators (24 V DC or 115/230 V AC)
Control Circuit
The power source for the control circuit supplies the CPU, the bus units, the programmer interface,
and the internal control circuits for the I/O modules. When the incoming supply is 24 V DC/1 A, the
PS 931 power supply module provides an internal supply of +9 V up to a total of 1 A current input
to the I/O modules. The grounding spring on the CPU forces the control circuit to be connected to
the standard mounting rail. The grounding spring must also be protected from interference. The
grounding spring must be grounded.
Load Circuit
The power source for the load circuit supplies the actuators of the process peripherals.
It is suggested that you use one of the following for a 24 V DC power supply:
• The PS 931 power supply module (see Appendix D)
• A Siemens load power supply from the 6EV1 series (see Appendix D)
If you use load power supplies other than the recommended ones, make certain that the load
voltage is in the range of 20 to 30 V (including ripple).
Note
If you use a switched-mode power supply unit to supply floating analog modules and
BEROs, then this supply must be filtered through a network.
You can connect several mutually independent load circuits adjacent to each other on a single
programmable controller. These connections can either be non-floating or floating (see
section 3.3.3).
3-20 EWA 4NEB 812 6120-02

3.3.2 Electrical Configuration with External I/Os
Figures 3-18, 3-19, and 3-20 display different configuration possibilities. Pay attention to the
following points when you design your configuration. The numbers appearing in parentheses in the
following points refer to the numbers in Figures 3-18 to 3-20.
• You must have a main switch (1) in accordance with VDE 0100 for your S5-100U, the sensors,
and the actuators.
• You do not need an additional fuse (2) to connect your S5-100U and the load circuit to power if
your radial lines are a maximum of 3 meters (9.84 feet) long and are inherently earth-fault proof
and short-circuit proof.
• You need a load power supply (3) for 24 V DC load circuits.
- You need a back-up capacitor (rating: 200 µF per 1 A of load current) if you have non-
stabilized load power supplies.
• If you have AC load circuits with more than five actuating coils, galvanic isolation via a
transformer (4) is recommended.
• You should ground the load circuit at one end. Provide a removable connection (5) to the
ground conductor on the load power supply (terminal M) or on the isolating transformer.
- You must provide earth-fault monitoring for any non-grounded load circuits.
• You must separately fuse (6 and 7) the load voltage for sensor circuits and for actuator circuits.
• You must connect the standard mounting rail of the S5-100U to the ground conductor through a
capacitor (8, to suppress high-frequency noise) for a non-grounded configuration.
• You must have a low-resistance connection between the standard mounting rail and the
cabinet’s chassis ground (10) for a grounded configuration.
• You need a power fuse (9) to protect against a short-circuit occurring in the power supply.
EWA 4NEB 812 6120-02 3-21

N
3-22
L3
L2
L1
PE
(5)
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(1)
(4)
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aaaaaaaaaa aaaaaa
230 V AC
(2)
(6)
(7)
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aaaaaaaaaaaa aa
(10)
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aaa
(9)
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PS
CPU
aaaa
2
1
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DI
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2
1
aaaaaa
DI
aaaaaa
2
1
for Programmable Controller, Sensors, and Actuators

aaaa
2
1
DO DO
Figure 3-18. Configuration Possibility: S5-100U with 115/230 V AC Power Supply
EWA 4NEB 812 6120-02

S5-100U
(1)
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L1
L2
aaaa
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aaa
L3
N
aaaaaa
aaa
aaaaaa
aaa
PE
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
(2)
(3)
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(5) CPU
M L+
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aaaaaaaaaaaaaa
aaaaaa
aaaaa
L+
M
DI DI DO DO
aaaaaaaaaaaa
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aaaaaaaaaaaa
(10) 1 1 1 1
2 2 2 2
(6)
aaaa
aa
aaaa
aaaaaa
aaaa
(7)
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aaa
aaaa
aa
aaaaaa
aaaaaa
M L+
Figure 3.19 Configuration Possibility: S5-100U with 24 V DC Power Supply

(with Safe Electrical Isolation According to DIN VDE 0160)
for Programmable Controller, Sensors, and Actuators
EWA 4NEB 812 6120-02 3-23

L1 (1)
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aaa
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L2
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aaa
L3
N
PE
aaaa
aaaa
(2) (8)
1 µF/
100 K 500 V AC Install the standard mounting
rail electrically isolated
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aaaaaaaaaaaaaaa
(3) CPU
M L+
aaaa
aa
L+
aaaaaa
aaa
M
DI DI DO DO
1 1 1 1
2 2 2 2
(6)
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aaa
aaaaaa
aaaaaa
aaaaaa
aaa
aaaaaa
(7)
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aaa
aaaaa
aaa
aaaa
aa
aaaa
M L+
Figure 3-20. Non-Grounded Operation; 24 V DC Power Supply

(with Safe Electrical Isolation According to DIN VDE 0160)
for Programmable Controller and I/Os
Interference voltages are discharged to the ground conductor (PE) via a capacitor. You can prevent
static charges by connecting a high-ohmic resistor (approx. 100 k / W) parallel to the capacitor.
3-24 EWA 4NEB 812 6120-02

3.3.3 Non-Floating and Floating Configurations
The S5-100U is powered by its own control circuit. The I/Os are powered by the load circuit.
The circuits can either be connected to the same grounding point (non-floating) or galvanically
isolated (floating).
Example of a Non-Floating Connection of Digital Modules

A 24 V DC load circuit has the same chassis grounding as the control circuit of the S5-100U.
Central
grounding point
PS CPU
L+
M
Common
chassis ground
M L+
Load power
supply
Figure 3-21. Example: Non-Floating Connection of I/Os to the S5-100U
EWA 4NEB 812 6120-02 3-25

The common chassis grounding connection makes it possible for you to use reasonably priced non-
floating I/Os. These modules function according to the following principles.
• Input modules
- The ground line, line M (control circuit chassis) is the reference potential. A voltage drop V1 on
line affects the input signal level VI.
• Output modules
- Terminal 2 (M) of the terminal block is the reference potential. A voltage drop V2 on the
line raises the chassis potential of the output driver and thus reduces the resulting control
voltage VCV.
Figure 3-22 shows a simplified connection of the S5-100U with a non-floating external I/O.
+9 V
Data
GND
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aaaaaaaa
aaaa
VCV
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aaaaa
CPU
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
L+
M
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aaaaa
VI
aaaaaaaa
aaaa
aaaaaaaa
aaaa
1 2
aaaaaaaa
aaaaaaaa
V1
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aaaaaaaa
aaaa
L+
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aaaaaaaaaa
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24 V DC supply
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aaaaa
V2
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
Figure 3-22. Simplified Representation of a Non-Floating I/O Connection
3-26 EWA 4NEB 812 6120-02

When you have a non-floating configuration, you must make certain that the voltage drop on
cables and does not exceed 1 V. If 1 V is exceeded, the reference potentials could change
and the modules could malfunction.
Warning
If you use non-floating I/O modules, you must provide an external connection between
the chassis ground of the non-floating I/O module and the chassis ground of the CPU.
Example of a Floating Configuration with Digital Modules

Floating configuration is required in the following situations.
• When you need to increase interference immunity in the load circuits
• When load circuits cannot be interconnected
• When you have AC load circuits
If you have a floating configuration, the PLC's control circuit and the load circuit must be galvanically
isolated.
Figure 3-23 shows a simplified connection of galvanically isolated I/Os.
Central
grounding point
PS CPU
L+
M
aaaaaaaa
aaaaaaaa
L+ M
Load power
supply
Figure 3-23. Simplified Representation of a Galvanically Isolated Connection of the

I/Os to the S5-100U
EWA 4NEB 812 6120-02 3-27

Figure 3-24 shows a simplified schematic for the connection of floating I/O modules.
aaaaaaaa
aaaa
• +9 V
aaaaaaaa
aaaaaaaa
• • Data
aaaaaaaa
• GND
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
CPU
1L+
M
L1 2L+
N • • 2M
Figure 3-24. A Simplified Representation of a Floating I/O Connection
3-28 EWA 4NEB 812 6120-02

3.4 Wiring Arrangement, Shielding, and Measures to Guard against

Electromagnetic Interference
This section describes the wiring arrangements for bus cables, signal cables, and power supply
cables that guarantee the ElectroMagnetic Compatibility (EMC) of your installation.
3.4.1 Wiring Arrangement
Wiring Arrangement inside a Cabinet

When a cabling system is installed in a cabinet, the wiring arrangement significantly affects inter-
ference immunity (EMC). Even during the planning phase, you should divide your cables into the
following three groups:
• Group 1
- Shielded data cables (for programmers, OPs, SINEC L1, ET 200 bus etc.)
- Shielded analog cables
- Unshielded cables for DC and AC 60 V
- Shielded cables for DC and AC 230 V
• Group 2
- Unshielded cables for DC and AC > 60 V and 230 V
• Group 3
- Unshielded cables for DC and AC > 230 V and 1 kV
You should install each cable group in the cabinet separately. Separate installation refers to wiring
that requires the following:
• Separate cable ducts
• Separate cable bundles
Note
Make sure that you have a minimum clearance of 10 cm (4 in.) between signal cables
and power cables conducting over 500 V.
When you install shielded cables, make sure that you install the shield on a shield support rail.
The shield should reach the module, but it should not be connected to the module.
EWA 4NEB 812 6120-02 3-29

Wiring Arrangement outside a Cabinet

• Install cables on a metal cable bearer when cabinets are physically apart but within the same
building. Galvanically connect the cable bearer joints. The joints should be grounded at intervals
of about 20 to 30 meters (65 to 98 feet).
• Always use shielded analog signal cables .
• Install the following cables on the same cable raceways (cable routes, cable ducts, cable
channels, and cable conduits):
- Unshielded digital cables 60 V
- Shielded data cables and shielded analog cables, including the ET 200 bus cable
- Shielded signal cables of up to 230 V
• Install cables having voltages >230 V in separate wiring channels (routes, conduits).
Wiring Arrangement outside a Building

Make certain that cables installed outside buildings adhere to the regulations regarding lightning and
grounding.
• Lightning
When installing cables outside a building, use one of the following methods:
- Use corrosion-resistant steel conduit that is well grounded.
- Use nonmetallic conduit that is encased in steel-reinforced concrete. The reinforcing steel
should be made electrically continuous and should be well grounded.
• Grounding
- Make certain that you have sufficient equipotential bonding between the devices.
- Install an equipotential bonding cable that has an impedance 10% of the shield impedance
of the cables.
Tips for Cable Installations

• Do not install signal cables directly parallel to power cables.
• Install electromagnetically sensitive cables at least one meter (3.3 feet) away from any source of
interference (contactor, transformer, motor, arc welder, etc.).
• Make certain that you bundle the cables together if two control components are joined together
by several signal cables.
• Install signal cables and the corresponding equipotential bonding cables bundled together on the
shortest route possible.
• Install individual cables that carry the same type of signal (outgoing and return cables and power
supply cables) bundled together. Twist the cables, if needed.
• Route the cables against the chassis-grounded surfaces where possible.
• Avoid using terminal lugs to extend cables.
• Route power cables and signal cables through separate cable ducts and switch boxes.
• Use surface-type contact for the shields.
3-30 EWA 4NEB 812 6120-02

3.4.2 Shielding of Devices and Cables
Shielding is a means of weakening or damping magnetic, electrical, or electromagnetic interference

fields. Both devices and cables should be shielded.
Shielding of Devices
Use the following information if cabinets and housing are used in shielding the control system.
• Cabinet enclosures, such as side walls, back walls, top plates, and bottom plates, should be
bonded at certain intervals (e.g., 50 mm/2 inches) when you have an overlapping layout.
• Doors need additional bonding to the cabinet's chassis ground. Use wide grounding strips.
• The cables that exit the shield housing should either be shielded or filtered.
• Sheet metal must be used to separate strong interference sources located in the cabinet
(transformers, cables leading to motors, etc.) from sensitive electronic areas. The multiple
screw connections of the sheet metal to the cabinet's chassis ground must have a low
impedance.
The noise interference coming into the programmable controller via the signal cables and supply
lines must be discharged on the central grounding point (standard mounting rail).
Use a low impedance copper conductor, 10 mm2, that is as short as possible to connect the
central grounding point to the protective conductor PE (ground rail).
EWA 4NEB 812 6120-02 3-31

Shielding Cables
Both ends of shielded cables should have a good electrical connection to the cabinet's chassis
ground. You can effectively suppress interference of all coupled frequencies only if the cables are
shielded at both ends. The shield should reach the module, but it should not be connected to the
module.
Note
There can be a compensating current flowing across cables shielded at both ends if
there are ground potential fluctuations. You should therefore join the connected
components with an additional equipotential bonding cable.
It would be unusual to shield only one cable end because shielding only one cable end dampens
only the low frequencies. Shield a single cable end in only the following instances.
• It is not possible to lay an equipotential bonding cable.
• Only very low analog signals (a few mV or µA) are transmitted.
With SIMATIC controllers, the interference current on cable shielding is discharged to ground both
via the shielding rail and the equipotential bonding cable. To prevent these discharged currents from
becoming a source of interference, ground them on a low-resistance path as follows:
• Tighten the hold-down screws on the cable connectors, modules, and equipotential bonding
cables.
• Protect the contact surfaces of equipotential bonding cables against corrosion.
3.4.3 Measures to Guard against Electromagnetic Interference

Measures to guard against electromagnetic interference are frequently not taken until after the
controller is operating and problems develop with the reception of a signal.
When you install your controller, you can significantly reduce the number of problems caused by
electromagnetic interference if you proceed as follows.
• Arrange devices and cables correctly.
• Ground all inactive metal parts to chassis.
• Filter power cables and signal cables.
• Shield devices and cables.
• Take specific interference suppression measures.
Physical Arrangement of Devices and Cables

It would cost a lot of money to significantly decrease the constant magnetic fields or alternating
fields that occur at low frequencies (e.g., 50 Hz). You can frequently avoid this problem by having
as much space as possible between the interference source and any potentially susceptible device.
3-32 EWA 4NEB 812 6120-02

Chassis Grounding of Inactive Metal Components

Correct chassis grounding is an important factor in ensuring that you won't experience interference
problems. Chassis grounding refers to the conductive connection of all inactive metal components
(VDE 0160). Always use surface-contact grounding. Chassis-ground all inactive metal components.
Basic rules for surface-contact grounding:

• All chassis connections should have a low impedance.
• All metal components should have a large surface contact.
- Use especially wide grounding strips when you connect the components. The surface area of
the chassis ground is the deciding factor and not the cross-section of the interconnecting
cable.
• Use spring lock washers or serrated lock washers on all screwed connections.
Filters for Main Cables and Signal Cables

Filtering main cables and signal cables is a means of reducing conductive-associated interferences.
No overvoltages may be allowed to occur in the supply lines and signal cables located in a cabinet.
Use the following procedures to avoid having overvoltages occur:

• Interference suppression in main cables
A main filter (e.g., B84299-K64, 250 V AC/10 A) should be installed in the supply line for
incoming supplies from the main supply. Always install the main filter on the cabinet opening.
When you install the main filter, make certain that it has a large surface contact and a low
impedance to the cabinet's chassis ground. Make sure that the contact surfaces are bare.
• Discharge capacitors for a DC power supply
If a cabinet is connected to a central 24-V power supply, then noise interference can pass into
the control system via this supply line.
This can be avoided by installing interference-suppression capacitors on the cabinet opening of
the 24-V supply. Mount these capacitors either on the cabinet's chassis ground or on the
shielding rail.
Figure 3-25 shows the layout of the interference-suppression capacitors.
e.g. 0.6 µF
B81551-A-B16
Cabinet's chassis
ground
Block diagram
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aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
0.2 µF
e.g. 0.2 µF
B81111-A-B42
0.6 µF 0.6 µF
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
+24 V 0V +24 V 0V
Figure 3-25. Layout of the Interference-Suppression Capacitors
EWA 4NEB 812 6120-02 3-33

Using Special Interference Suppression Measures
Protective Inductive Circuit

Inductors located in the same cabinet and not directly controlled by SIMATIC outputs (e.g., contactor
coils and relay coils) must be bridged by arc suppressing elements (e.g., RC elements).
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Protective circuits for DC-controlled coils Protective circuits for AC-controlled coils
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aaaaaaaa
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With a diode With a zener diode With a varistor With an RC element
Figure 3-26. RC Circuits for Coils
Partitioning Inductors
It is recommended that you use metal barriers to partition the portion of the cabinet that contains
large inductors, such as transformers or contactors.
Protection against Electrostatic Discharge

You should use metal enclosures or cabinets closed on all sides to protect devices and modules
against electrostatic discharges. These enclosures or cabinets should have a good conductive
connection to the grounding point at the installation site.
If you install your control system in a terminal box, then use a cast-metal housing or sheet-metal
housing if possible. A plastic housing should always have a metallic surface. Connect housing doors
or covers to the chassis ground via grounding strips or contact springs.
If you work on the system and have the cabinet open, adhere to the guidelines for working with
electrostatic sensitive devices (ESD).
3-34 EWA 4NEB 812 6120-02

Power Connection for Programmers

Every group of cabinets should have a grounded socket for the power supply to the programmers.
The sockets should receive their power supply from the distributor that is also connected to the
cabinet's protective ground.
Cabinet Lighting
Do not use any fluorescent lamps inside a cabinet. They can cause noise interference. If you must
use fluorescent lamps, then carry out the measures shown in Figure 3-27. It would be better to use
LINESTRA® (incandescent) lamps.
Screen grid above the lamp
Completely shielded cable
Metal-encased switch
Main filter or shielded system supply line
Figure 3-27. How to Reduce Noise Interference Caused by

Fluorescent Lamps in a Cabinet
EWA 4NEB 812 6120-02 3-35

3.5 Protective Devices and Insulation Monitoring Devices
When you configure systems that have programmable controllers, follow the relevant VDE
regulations (e.g., VDE 0100, VDE 0113 or VDE 0160). Pay special attention to the following points:
• Prevent conditions that can endanger people or property.
• When power is restored after a power failure or after EMERGENCY OFF devices are
deactivated, machines must not be able to restart automatically.
• When a programmable controller malfunctions, commands for EMERGENCY OFF devices and
safety limit switches must remain effective under all circumstances. These safety measures
must directly affect the actuators in the power supply.
• When EMERGENCY OFF devices are activated, safety must be guaranteed for both people and
the system as follows:
- Actuators and drives that could cause dangerous situations (e.g., main spindle drives for
machine tools) must be shut off.
- Actuators and drives that could endanger persons or the controlled system by being shut off
(e.g., clamping devices) must not be shut off by EMERGENCY OFF devices.
• The programmable controller must be able to record the activation of EMERGENCY OFF
equipment, and the control system must be able to evaluate it.
Protection in Case of Indirect Contact

Accessible parts must not be dangerous to touch even if there is a fault.
This requirement is fulfilled if you make all accessible metal parts electrically safe that could be
dangerous to touch in the event of a failure (e. g, standard mounting rails, transoms, the cabinet).
This is done by connecting these parts to the protective ground conductor (PE). The maximum
permissible resistance between the protective-conductor terminal and the accessible part that
requires protecting is 0.5 .
3-36 EWA 4NEB 812 6120-02

Protection against Lightning

If you run cables and lines for SIMATIC S5 devices outside buildings, you must use shielded cables.
The shield must be able to conduct current and be connected at both ends to ground. Use double-
shielded cables for analog signal lines. Ground the inner shield on one end only.
In addition, you must connect signal cables to protective elements, such as varistors or lightning
arresters filled with inert gas, so that you don't have an overvoltage. The protective elements should
be present where the cable enters the building, if possible. Otherwise, the protective elements
should be where the cable enters the cabinet.
SIMATIC cabinet
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PLC
Lightning Sensors/
arrester actuators
aaaaaaaaaaaaaaa
Varistor
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Figure 3-28. Layout of Elements to Protect against Lightning
Note
Use varistors or lightning arresters filled with inert gas to protect against overvoltages.
Install these protective elements where the cable enters the building, if possible.
Each system must be looked at individually to determine measures that should be taken
to protect it against lightning. Please address your questions to your local Siemens
office.
EWA 4NEB 812 6120-02 3-37

4 Start-up and Program Tests
4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.3 Performing an Overall Reset on the Programmable Controller . . . . 4-2
4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Suggestions for Configuring and Installing the Product . . . . . . . . . 4-3
4.2.2 Procedures for Starting Up the Programmable Controller . . . . . . . 4-4
4.3 Loading the Program into the Programmable Controller ........ 4-5
4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.1 Backing Up the Program on a Memory Submodule . . . . . . . . . . . . 4-7
4.4.2 Function of the Back-Up Battery . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.5 Program-Dependent Signal Status Display “STATUS” ......... 4-8
4.6 Direct Signal Status Display “STATUS VAR” ................ 4-9
4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher .......... 4-10
4.8 Forcing Variables, “FORCE VAR” ........................ 4-10
4.9 Search Function .................................... 4-11
4.10 Program Check, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 4-11
EWA 4NEB 812 6120-02

Figures
4-1 CPU Operator Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4-2 Procedure for Loading the Program Automatically . . . . . . . . . . . . . . . . . . . 4 - 5
4-3 Procedure for Loading the Program Manually . . . . . . . . . . . . . . . . . . . . . . 4 - 6
4-4 Procedure for Backing Up the Program on a Memory Submodule ....... 4 - 7
4-5 “STATUS” Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9
4-6 “STATUS VAR” Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9
Table
4-1 Starting Up the Programable Controller .......................... 4 - 4
EWA 4NEB 812 6120-02

S5-100U Start-up and Program Tests
4 Start-up and Program Tests
4.1 Operating Instructions
4.1.1 CPU Operator Panel

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aaaaaaaa
BATTERY Operating mode display

aaaaaaaaaaaaaaaaaaaaaaaaaa
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aaaaaaaa
aaaaaaaa
aaaa
Battery low OFF/ RUN

(green LED: RUN)
LOW
(yellow LED lights:
Operating mode display
aaaaaaaa
aaaaaaaa
aaaaaaaa
battery discharged or STOP

not installed) (red LED: STOP)
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
RUN
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
I
STOP Operating mode switch
O
aaaaaaaaaa
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aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
COPY
ON/OFF switch
Figure 4.1 CPU Operator Panel
ON/OFF Switch
The ON/OFF switch turns on the CPU’s voltage regulators. This switch does NOT separate the
voltage regulator from the L+/M terminals.
Operating Mode Switch

Use the operating mode switch to select either the RUN or STOP operating mode. The CPU
automatically goes into the START-UP mode during the transition from STOP to RUN (see section
7.4.2).
4.1.2 Operating Modes
STOP Operating Mode

• The program is not executed.
• The current values for timers, counters, flags, and process image I/O tables are saved when the
STOP mode begins.
• The output modules are disabled (signal status “0”).
• The process image I/O tables, timers, and non-retentive flags and counters are set to “zero”
during the transition from STOP to RUN.
RUN Operating Mode

• The program is processed cyclically.
• Already started timers continue to run.
• The signal states for the input modules are stored.
• The output modules are addressed.
• The RUN operating mode can also be set after an OVERALL RESET, that is, when the program
memory is empty.
EWA 4NEB 812 6120-02 4-1

Start-up and Program Tests S5-100U
START-UP Operating Mode

• The operating system processes DB1 and accepts the parameters (see section 9.1).
• Either the start-up organization block OB21 or OB22 is processed (see section 7.4.2).
• The amount of time start-up requires is not limited since the scan time monitor is not activated.
• Neither time-controlled program processing nor interrupt-driven program processing is possible.
• The input modules and output modules are disabled during start-up.
Changing Operating Modes

A change in operating mode can be caused by the following:
• The operating mode switch - when its position is changed.
• A programmer - if the operating mode switch on the programmable controller is set to RUN.
• Malfunctions - if one occurs that causes the programmable controller to go into the STOP
operating mode (see chapter 5).
4.1.3 Performing an Overall Reset on the Programmable Controller
You should perform an overall reset before you input a new program. An overall reset erases the
following:
• The programmable controller's program memory
• All data (flags, timers, and counters)
• All error IDs
Note
If you do not perform an overall reset, then the information indicated above is retained
even if the program is overwritten.
Manual Reset
To perform a manual overall reset, you must:
1. Set the operating mode switch to STOP.
2. Remove the battery.
3. Set the ON/OFF switch to “0”.
4. Change the ON/OFF switch to “1”.
5. Insert the battery.
Performing an Overall Reset with the Programmer

You can select the overall reset function from the programmer's menu line. Refer to the
programmer manual.
4-2 EWA 4NEB 812 6120-02

4.2 Starting Up a System
The following section contains suggestions for configuring and starting up a system containing
programmable controllers.
4.2.1 Suggestions for Configuring and Installing the Product
A programmable controller is often used as a component in a larger system. The suggestions

contained in the following warning are intended to help you safely install your programmable
controller.
Warning
• Adhere to any safety and accident-prevention regulations applicable to your
situation and system.
• If your system has a permanent power connection (stationary equipment) that is
not equipped with an isolating switch and/or fuses that disconnect all poles,
install either a suitable isolating switch or fuses in the building wiring system.
Connect your system to a ground conductor.
• Before start-up, if you have units that operate using the main power supply,
make sure that the voltage range setting on the equipment matches the local
main power voltage.
• When using a 24 V supply, make sure to provide proper electric isolation
between the main supply and the 24-V supply. Use only power supplies
manufactured according to IEC 364-4-41 or HD 384.04.41 (VDE 0100, part 410).
• Fluctuations or deviations of the supply voltage from the rated value may not
exceed the tolerance limit specified in the technical data. If they do, functional
failures or dangerous conditions can occur in the electronic modules or
equipment.
• Take suitable measures to make sure that programs that are interrupted by a
voltage dip or power failure resume proper operation when the power is restored.
Make sure that dangerous operating conditions do not occur even momentarily.
If necessary, force an EMERGENCY OFF.
• EMERGENCY OFF devices must be in accordance with EN 60204/IEC 204
(VDE 0113) and be effective in all operating modes of the equipment. Make
certain to prevent any uncontrolled or undefined restart when the
EMERGENCY OFF devices are released.
• Install power supply and signal cables so that inductive and capacitive
interference can not affect the automation functions.
• Install your automation system and its operative components so as to prevent
unintentional operation.
• Automation equipment can assume an undefined state in the case of a wire
break in the signal lines. To prevent this, take the proper hardware and software
safety measures when linking the inputs and outputs of the automation
equipment.
EWA 4NEB 812 6120-02 4-3

4.2.2 Procedures for Starting Up the Programmable Controller
Table 4-1. Starting Up the Programmable Controller

Prerequisites Remarks Displays
Procedures
System and programmable Check the mechanical assembly
controller are off-load. (VDE 0100 and VDE 0160). Ter-
minal “M” of the load power
• Check the mechanical
supply and the ground terminal of
configuration and wiring.
the programmable controller must
(see section 3.1 and 3.2).
be connected to the central
grounding point (standard
mounting rail). For non-floating
modules, a module’s “M” terminal
must be connected to the
programmable controller’s “M”
terminal.
Set the ON/OFF switch to
“0” and the operating mode
switch to ”STOP”.
• Switch on the power supply • Red fault LEDs on the I/O
and load power supply. modules lights.
• Set ON/OFF switch to “1”. • Red LED of the CPU lights;.
• Connect programmer to yellow LED lights if the battery is
CPU. low or not installed.
• Reset the programmable
controller (see section 4.1.3).
• Set operating mode switch to • Green LED on the CPU lights.
RUN.
• Switch on sensor power • Red fault LEDs on the input
supply. modules darken.
• Actuate the sensors one after The input signals in the PII can be • Green LEDs on the input modules
the other. observed with the “STATUS VAR” light.
programmer function.
• Switch on power supply for • Red fault LEDs on the output
output modules and modules darken.
actuators.
• Force the outputs with the The switching states of the • Green LEDs of the output
“FORCE” programmer associated actuators change. modules light up.
function.
Program on memory sub-

module
• Set ON/OFF switch to “0”.
• Plug in the memory
submodule.
• Set ON/OFF switch to Program is loaded. • Red LED of the CPU lights.
“1”. *
• Test program and make any
necessary corrections.
• Set operating mode switch to
STOP.
• Switch on the load.
• Set operating mode switch to
RUN.
• Back up the program. The system is in operation. • Green LED of the CPU lights.
* For the CPU 102 only: press the <COPY> key simultaneously (manual loading).
4-4 EWA 4NEB 812 6120-02

4.3 Loading the Program into the Programmable Controller
You can load a program from a connected programmer (online operation). When you load a
program, it is transferred to the programmable controller's program memory. There are specific
instructions in your programmer manual for doing this.
You can also load your program from a memory submodule, but only valid blocks can be loaded.
See section 7.5.2. The different memory submodules you can use are listed in Appendix D.
Section 4.3 describes how you can load a program from a memory submodule.
Warning
You can connect or disconnect memory submodules only in the Power OFF mode.
Loading the Program Automatically

Automatic loading copies the program from a memory submodule into the program memory of the
CPU. You can only load valid blocks. See section 7.5.2.
Figure 4-2 shows how a program can be loaded automatically.
No battery is installed
(yellow LED lights). PLC overall reset
Switch the S5-100U off.
Plug memory submodule

into the CPU.
Error
Switch the S5-100U on.
Red LED flashes.

CPU 100: red LED lights;
CPU 102/103: red LED flickers.
Perform error diagnostics

(see section 5.1).
Program is loaded.
Program is in the
S5-100U.
The CPU 102 is in

the Normal Mode.
Figure 4-2. Procedure for Loading the Program Automatically
EWA 4NEB 812 6120-02 4-5

Loading the Program Manually

Manual loading copies the program from a memory submodule into the program memory of the
CPU. If a back-up battery is installed, any program in the memory is completely erased.
You can only load valid blocks. See section 7.5.2.
Figure 4-3 shows how a program can be loaded manually.
Turn off the S5-100U.
Plug memory sub-

module into the CPU.
Press <COPY> key

and hold it down.
Error
Turn on the S5-100U. Red LED flashes.
Red LED flickers; release Release <COPY>

<COPY> key. key.
Program is Red LED Red LED

lights. flashes.
loaded
Red LED shows Perform error

steady light; No valid program
program is in the diagnostics
is in submodule.
S5-100U. (see section 5.1).
The CPU 102 is

in Test Mode
Figure 4-3. Procedure for Loading the Program Manually
4-6 EWA 4NEB 812 6120-02

4.4 Backing Up the Program
A program can be backed up only if the back-up battery is connected. Backing up copies a program
from the program memory of the CPU to a memory submodule. Only valid blocks are backed up.
As soon as you have changed the integral, default DB1 data block, it is a valid block that can be
backed up. See section 7.5.2.
4.4.1 Backing Up the Program on a Memory Submodule
You can use various EEPROM memory submodules to back up a program. Appendix D contains a
list of the submodules you may use. Figure 4-4 illustrates how to back up a program on a memory
submodule.
Battery low LED (yellow) Insert / replace

lights. Yes battery.
No
Turn off the S5-100U.
Plug EEPROM sub-

module into the CPU.
Turn on the S5-100U.
Press <COPY> key Error

Red LED flashes.
for at least 3 s.
Red LED flickers; Release <COPY>

Release <COPY> key.
Program is Red LED Red LED

loaded. 1) lights. flashes.
Red LED lights; - No / wrong sub-

Program backed up module plugged Perform error
on EEPROM in. diagnostics
submodule. (see section 5.1).
- No program is in
the S5-100U.
The CPU is in the

Normal Mode.
1) Program load time: 40 s/1024 statements
Figure 4-4. Procedure for Backing Up the Program on a Memory Submodule
EWA 4NEB 812 6120-02 4-7

4.4.2 Function of the Back-Up Battery
If the power fails or the programmable controller is turned off, the contents of the internal (retentive)
memory are stored only if a back-up battery is connected. When power is recovered or when the
programmable controller is turned on, the following contents are available:
• Control program and data blocks (see section 7.3.5)
• Retentive flags and count values (see section 2.2.1)
• ISTACK contents (see section 5.3]
Note
• Insert and replace the battery while the programmable controller is turned on.
Otherwise, an OVERALL RESET is required when you turn the programmable
controller on.
• The lithium battery in the programmable controller has a life expectancy of at least
one year.
• The yellow LED on the operator panel lights up if the battery fails.
Warning
Do not charge lithium batteries. They could explode. Dispose of used batteries properly.
4.5 Program-Dependent Signal Status Display “STATUS”

This test function displays the current signal states and the Result of Logic Operations (RLO) of the
individual operands during program processing.
You can use this test function to make corrections to the program.
Note
The current signal states are displayed only in the RUN operating mode.
4-8 EWA 4NEB 812 6120-02

Cycle trigger
aaaaaaaaaaaaaaa
ontrol
STATUS ogram
= Q 2.0 1 1
Transfer data
Figure 4-5. “STATUS" Test Function
Refer to your programmer manual for information about the test function on your programmer.
4.6 Direct Signal Status Display “STATUS VAR”
This test function specifies the status of the operands (inputs, outputs, flags, data words, counters,
or timers) at the end of program processing. You can obtain information about inputs and outputs
from the process image I/O tables of the selected operands.
Cycle trigger
Control program
Transfer data
STATUS
VAR
Figure 4-6. “STATUS VAR” Test Function
EWA 4NEB 812 6120-02 4-9

4.7 Forcing Outputs, “FORCE”, for CPU 103 and Higher
Outputs can be set directly to a desired status even without the control program. This enables you
to control the wiring and functionality of output modules. This does not change the process I/O
image table, but the output disable condition is cancelled.
Note
The programmable controller must be in the STOP operating mode.
Refer to your programmer manual for information about calling up the test function on your
programmer.
4.8 Forcing Variables, “FORCE VAR”
The process image I/O table of the operands is changed regardless of the programmable controller's
operating mode. You can change the following variables: I, Q, F, T, C, and D.
The program is processed in the RUN operating mode using the changed process variables. They
can be changed again during program scanning without an acknowledgement being required. The
process variables are forced asynchronously to the program scanning.
Special characteristics
• You can change the I, Q, and F variables in the process I/O image table by bits, bytes, or words.
• For the T and C variables in KM and KH format, note the following:
- For programmers with screens, you must also enter “YES” in the system commands input
field in the presettings screen.
- You must be careful when you force edge trigger flags. You do not want to enable a higher-
order byte inadvertently because this could give you a timer or counter value you did not set.
• The signal status display breaks off if there is an error in the format entry or operand entry. The
programmer then displays the “NO FORCING POSSIBLE” message.
4-10 EWA 4NEB 812 6120-02

4.9 Search Function
This function allows you to search for specific terms in the program and list them on the pro-
grammer's display panel. You can perform program changes at this point.
You can have search runs in the following programmer functions:

• INPUT
• OUTPUT
• STATUS
Some of the items you can search for are:

• Statements (e.g., A I 0.0)
• Operands (e.g., Q 3.5)
• Labels (e.g., X 01); possible only in function blocks
• Addresses (e.g., 0006 H)
Note
Search runs are handled differently by different programmers. The respective users
guides contain extensive information about search runs.
4.10 Program Check, for CPU 103 and Higher
When this programmer function is called up, program scanning is stopped at a definite point. The
cursor indicates this breakpoint, which is a statement in the program. The programmable controller
scans the program up to the statement selected. The current signal states and the RLO up to the
statement selected are displayed (as in the “STATUS” test function).
The program can be scanned section by section by shifting the breakpoint. Program scanning takes
place as follows:
• All jumps in the block called are executed.
• Block calls are executed immediately. The program check is not resumed until control is
returned to the calling block.
The following applies during the program check:

• The two mode LEDs are not lit.
• The program writes to the PIQ and reads out the PII.
• No process image (data cycle) is transferred.
• All outputs are set to zero.
EWA 4NEB 812 6120-02 4-11

During the program check, you can execute the following additional test and programmable
controller functions from the programmer:
• Input and output (program modification possible)
• Direct signal status display (STATUS VAR)
• Forcing of outputs and variables (FORCE, FORCE VAR)
• Information functions (ISTACK, BSTACK)
If the function is aborted due to hardware faults or program errors, the programmable controller goes
into the STOP mode and the red LED on the control panel of the CPU lights.
Refer to your programmer manual for information about calling up these functions on your
programmer.
4-12 EWA 4NEB 812 6120-02

5 Diagnostics and Troubleshooting
5.1 Indication of Errors by LEDs ............................ 5 - 1
5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2.1 “ISTACK” Analysis Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5.2.2 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5.2.3 Errors during Program Copying . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6
5.2.4 Explanation of the Mnemonics Used in “ISTACK” . . . . . . . . . . . . . 5 - 7
5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9

5.3.1 Locating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9
5.3.2 Tracing the Program with the “BSTACK” Function ............ 5 - 12
5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
5.6 The Last Resort .................................... 5 - 15
EWA 4NEB 812 6120-02

Figures
5-1 Example of an “ISTACK” Display on the PG 615, Software Version V 1.4 . 5 - 2

5-2 Structured Program with an Illegal Statement . . . . . . . . . . . . . . . . . . . . . . 5 - 9
5-3 Addresses in the CPU’s Program Memory . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10
5-4 Example of a “DIR PC” Display on the PG 615 .................... 5 - 11
5-5 Calculating the Error Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 11
5-6 Tracing the Program with “BSTACK” ........................... 5 - 12
5-7 Example of a “BSTACK” Display on the PG 615 ................... 5 - 13
5-8 Analyzing the Cause of a Fault in the I/Os . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
Tables
5-1 Error Indication and Error Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5-2 ISTACK Output (Bytes 1 to 32) ............................... 5 -3/4
5-3 Interrupt Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -5/6
5-4 Errors when Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6
5-5 Meaning of the Remaining ISTACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 7
5-6 Mnemonics Used for the Interrupt Display . . . . . . . . . . . . . . . . . . . . . . . . 5 - 8
EWA 4NEB 812 6120-02

S5-100U Diagnostics and Troubleshooting
5 Diagnostics and Troubleshooting
5.1 Indication of Errors by LEDs
The programmable controller's operator panel will show you if your device is not functioning
correctly (see Table 5-1).
Table 5-1. Error Indication and Error Analysis

Error Indication Error Analysis
CPU in STOP CPU malfunction

Red LED lights Use the programmer to execute an interrupt analysis
(see section 5.2).
CPU in STOP Error when loading or backing up the program

Red LED flashes Use the programmer to execute an interrupt analysis
(see section 5.2).
CPU in RUN Program error
Green LED lights (see section 5.3)
Faulty operation or
I/O fault
Execute a fault analysis
(see section 5.4).
If both LEDs light, your programmable controller is in the START-UP operating mode.
5.2 CPU Malfunctions
5.2.1 “ISTACK” Analysis Function

The interrupt stack is an internal CPU memory area where the causes of malfunctions are stored. If
there is a malfunction, a bit in the respective byte of the memory area is set. Using the pro-
grammer, you can read out the contents of this memory area byte-by-byte.
Calling the ISTACK

The call is made through the programmer menu in the STOP operating mode.
Refer to your programmer manual for the key sequence.
Note
Only ISTACK bytes 1 through 6 can be output in the RUN mode. There is no cause for
an interrupt to force the CPU to go into the STOP mode. The control bits are output in
bytes 1 through 6.
EWA 4NEB 812 6120-02 5-1

5-2
ISTACK bytes
Representation
Reason for STOP
aaaaaaaaaaaaaaaaaa aaaaaaaaaa
PB 7
ISTACK Display on the PG 615 Programmer
*ISTACK
Binary
Hex
0000 0000 00
0000 0000 00
aaaaaaaaa aaaaaaaaaa
ILLEGAL OPERATION
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaaaaaaaaa aaaaaaaaaa
2
1
REL. ERR. ADDR.:0002
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
Byte number
Figure 5-1. Example of an “ISTACK” Display on the PG 615, Software Version V 1.4
EWA 4NEB 812 6120-02

S5-100U
9
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
Byte
Bit
S5-100U
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
shaded bits).
NAU
AS
ZUS
STO
KEIN
ANZ1
STOPS
EWA 4NEB 812 6120-02

aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
ANZ
STO
FEH
aaaaaaaaaaaaaaaa
SYN
ANZ0
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
NI
BST
STA
SUF
SCH
NEU
OVFL
KOPF
aaaaaaaa
NINEU
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
5th nesting level

4th nesting level
6th nesting level
ZYK
TAE
SCH
TRAF
OR
BAT
PUF
BAU
ADR
NNN
IRRELEVANT
IRRELEVANT
IRRELEVANT
SYSFE
AF
OR
OR
OR
STS
STA
TUS
PEU
1
VKE
VKE
VKE
VKE
BAU
STUEB
Table 5-2. ISTACK Output (Bytes 1 to 16)
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
UR
aaaaaaaaaaaaaaaa
FKT
FKT
FKT
LAD
ERAB
ASPFA
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
lute
EBA6
EBA8
EA0E
EA0A
EA0C
EBAA
EBAC
Addr. (SD)
The following table shows which positions in the bit pattern are relevant for error diagnosis (gray-
SD 7
SD 6
SD 5
ta Word
(UAW)
SD 211
SD 212
SD 213
SD 214
Abso- Syst. Da-
5-3
*
5-4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Byte
Bit
7
section 9.1).
6
ACCU 1 (low)
ACCU 2 (low)
ACCU 1 (high)
ACCU 2 (high)
1st nesting level

3rd nesting level
2nd nesting level
5

Nesting depth (0 to 6)
Operation register (low)

Block stack pointer (low)
Operation register (high)

Block stack pointer (high)
4
Step address counter (low)*

Step address counter (high)*
Start address of the data block (low)

3
Start address of the data block (high)

2
OR
OR
OR
1
VKE
VKE
VKE
0
FKT
FKT
FKT
Table 5-2. ISTACK Output (Bytes 17 to 32) [continued]

aaaaaaaaaaaaaaa
lute
EB96
EB98
EB9A
EB9E
EBA0
EBA2
EBA4
EB9C
The PG 615 displays the cause of an interrupt as plain text before the ISTACK is output.
Addr. (SD)
If the step address counter displays a DB1 address, then there is a DB1 parameter setting error (see
The absolute memory address of the next statement to be processed from the faulty block is displayed.
ta Word
SD 203
SD 204
SD 205
SD 206
SD 207
SD 208
SD 209
SD 210
Abso- Syst. Da-
EWA 4NEB 812 6120-02

S5-100U
5.2.2 Interrupt Analysis

When there is an interrupt in program processing, you can use the following table to determine the
cause of the error. The CPU always goes into the STOP mode.
Table 5-3. Interrupt Analysis

ISTACK
Byte Cause of Error Remedy
Display
ASPFA and 10 Error during program transfer from the PG to the Shorten program.
KEIN AS 6 PLC: Compress memory.
and NNN 9 Overflow of the internal program memory during
and 25 and 26 compilation
SAZ=FFFF*
(CPU 102)
BAU 10 When automatically loading the program: Replace the battery and
- Battery is missing or dead and there is no recreate the program, or
valid program available on the memory load the program again.
submodule
NAU 10 Interruption in the power supply voltage to the

CPU
NINEU 6 The program in the PLC memory is defective. Perform an overall reset
Cause: and load the program
• A power failure has interrupted one of the again.
following operations.
- Compress
- Block transfer from the PG to the PLC or
memory submodule to the PLC
- PLC overall reset
• Battery has been replaced while the power
was off.
NNN 9 • Statement cannot be decoded. Eliminate program

• Nesting level is too high. errors.
• Parameter exceeds permitted limits.
PEU 10 • Expansion module not connected • Check the power

• I/O bus malfunction supply in the
• Maximum length of shift register exceeded expansion unit.
• Module unknown • Check the
• Module in wrong slot connections.
• Check the module
slots.
STOPS 9 Operating mode switch on STOP Set to RUN
STS 9 • Software stop by statement (STP)

• STOP requested by programmer
STUE 9 Block stack overflow: the maximum block call Eliminate program
nesting depth (16) has been exceeded. errors.
SYS** FEH 10 DB1 parameter setting error Correct DB1.
* SAZ = STEP address counter - The ISTACK bytes 25 and 26 read “1111 1111(FF)”.
** Relevant only for the PG 605U/PG 615U and for the CPU 103, version 8MA03 and higher.
EWA 4NEB 812 6120-02 5-5

Diagnostics and Troubleshooting S5-100U
Table 5-3. Interrupt Analysis (continued)

ISTACK Byte Cause of Error Remedy
Display
SUF* 9 Substitution error: Change actual

Function block called with an incorrect actual parameter.
parameter
TRAF 9 Transfer error Eliminate program error

• Data block statement programmed with a (see your programmer
data word number larger than the data manual).
block length
• Data block statement programmed without
previously opening a data block
ZYK 10 Scan time exceeded: Check the program for

The program processing time exceeds the continuous loops or
set monitoring time. Causes: shorten program.
• Program too long
• Interrupts too frequent
* Relevant for CPU 102, version 8MA02 and higher
5.2.3 Errors during Program Copying
Error message: after the <COPY> key is released, the red LED continues flashing.
Table 5-4. Errors when Copying

ISTACK Cause of Error Remedy
Display
ASPFA Loading the memory submodule into the PLC: Check the program on the
• Program on the memory submodule is too long memory submodule.
for the PLC's program memory.
• Program on the module contains an invalid block

number.
ASPFA Saving from the PLC to the memory submodule: Replace the memory
EEPROM memory submodule is defective or too submodule, or use a larger
small for the program in the PLC memory. EEPROM memory
submodule.
ASPFA and Internal program memory overflow during Shorten program.

KEIN AS and compilation
NNN
and SAZ=FFFF*
(CPU 102)
* SAZ = STEP Address Counter
The ISTACK bytes 25 and 26 read “1111 1111(FF)”
5-6 EWA 4NEB 812 6120-02

5.2.4 Explanation of the Mnemonics Used in “ISTACK”

Table 5-5. Meaning of the Remaining ISTACK Bits
ISTACK
Byte Explanation
Display
BST SCH 1 Shift block.
SCH TAE Execute shift operation.
ADR BAU Structure address list.
STO ANZ 3 PLC in STOP

STO ZUS Internal control bit for STOP/RUN change
BAT PUF Battery backup available
NEU STA PLC not yet in cycle after Power ON
- See bytes 9 and 10 for cause.
AF* 4 Interrupt enable/enabling of time-controlled OB13 and interrupt-
driven OB3
KOPFNI 5 Program contains errors.
Block header cannot be interpreted.
KEIN AS** 6 Not enough S5 statement memory available
URLAD Overall reset, program defective

SYNFEH Program contains errors.
ANZ 1/ANZ 0 12 Condition code bits for arithmetic, logic, and shift operations.
OV Arithmetic overflow
OR ID bit of OR memory
STATUS Status ID of operand of last binary statement executed
VKE Result of logic operation (RLO)
ERAB ID bit of first scan
FKT 13 0: O( OR parenthesis open
1: A( AND parenthesis open
* relevant for CPU 103 only

** for CPU 102: 0 = normal mode
1 = test mode
EWA 4NEB 812 6120-02 5-7

Table 5-6. Mnemonics Used for the Interrupt Display

Mnemonics Used
Explanation
for the Interrupt Display
ANZ1/ANZ0 Condition codes for various operations (see section A.1.4)

ASPFA Illegal memory submodule
BAU Battery failure

ERAB First scan
FKT 0 : O( 1 : A(
KE1...KE6 Nesting stack entry 1 to 6 entered for A( and O(
KEINAS Insufficient S5 statement memory available
NAU Power failure

NINEU Cold restart not possible
NNN Statement cannot be interpreted in the PLC

OR OR memory (set by command “0”)
OVFL Arithmetic overflow (+ or -)

PEU I/Os not ready:
• First bus unit not connected
• Expansion module not connected
• I/O bus malfunction
• Maximum shift register length exceeded
• Unknown module
• Module in the wrong slot
STATUS STATUS of the operand of the last binary statement executed

STOPS Operating mode switch on STOP
STS Operation interrupted by a programmer STOP request or

programmed STOP statements
STUE Block stack overflow: The maximum block call nesting depth of 16
has been exceeded.
SUF Substitution error

SYSFEH* Error in DB1
TRAF Transfer error for data block statements:

• When accessing a data word even though no corresponding data
block was opened or
• When the data word number is larger than the data block length
UAW Interrupt display word
VKE Result of logic operation (RLO)

ZYK Scan time exceeded: the set maximum permissible program scan
time has been exceeded
* Relevant only for CPU 103 version 8MA03 and higher
5-8 EWA 4NEB 812 6120-02

5.3 Program Errors
5.3.1 Locating the Error Address

The SAZ (STEP address counter) in the ISTACK (bytes 25 and 26) contains the absolute address
of the STEP 5 statement in the programmable controller before which the CPU went into the STOP
mode.
Use the “DIR PC” programmer function to determine the associated block start address.
Example: You have entered a control program consisting of OB1, PB0 and PB7. An illegal
statement has been programmed in PB7.
PB7
PB0
OB1
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
JU PB0 Illegal
L PB 0
JU PB7 statement
BE
BE
BE
Figure 5-2. Structured Program with an Illegal Statement
When it reaches the illegal statement, the CPU interrupts program scanning and enters the STOP
mode with the “NNN” message. The STEP address counter is at the absolute address of the next
(but not yet scanned) statement in the program memory.
EWA 4NEB 812 6120-02 5-9

5-10
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
i
xx
04
02
00
00
02
00
i+2

BE
BE
BE
L PB 0
JU PB7
JU PB0
PB7 Header
OB1 Header
PB0 Header
F5FF
EE41
EE40
EE32
EE17
EE09
EE00
EE42
EE31
EE30
EE19
EE18
EE0A
EE3F
EE2F
EE0E
EE0B
EE3C
EE3B
EE0C
EE3E
EE2E
EE3D
EE0D
aaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa
26
25
Byte
programmed blocks.
Figure 5-3. Addresses in the CPU’s Program Memory

Absolute addresses in
the CPU’s internal RAM
42
EE
Contents
paring these two addresses.
absolute start addresses of all
STEP address counter

The “DIR PC” function gives the
address of the illegal statement.
It is not possible to localize an error in
The error can then be localized by com-

the program on the basis of the physical
EWA 4NEB 812 6120-02

S5-100U
Display (example):
*DIR PC ALL
Block number
BLOCK ADDR.
NO DB
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
Block type PB 0 EE18

PB 7 EE3C
Start address
NO FB
OB 1 EE0A
Figure 5-4. Example of a “DIR PC” Display on the PG 615
Calculating the Address (necessary only when using the PG 605U)

In order to be able to make program corrections, it is necessary to have the address of the
statement that led to the fault referenced to the particular block (relative address).
The faulty block is found by comparing the SAZ (STEP address counter) contents and the “DIR
PC” display.
The relative error address gives the difference between the SAZ value and the block start address.
Figure 5-5 gives you an example of how to calculate the relative error address.
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
ISTACK byte 25 26 DIR PC
STEP address counter EE 42 Block Start Address
The absolute address EE42 is PB0 EE18

greater than the start address for PB7 EE3C
PB7. The faulty statement is
therefore in PB7. OB1 EE0A
Calculating the relative address: EE42 - EE3C = 0006
“0006” is the relative address of the statement in PB7 following the statement that
caused the CPU to go into the STOP mode.
Figure 5-5. Calculating the Error Address
Output of an Error Statement

Use the “SEARCH” programmer function to find certain program locations and to look for the
relative error address. Refer to your programmer manual for additional information about this
programmer function.
EWA 4NEB 812 6120-02 5-11

5.3.2 Tracing the Program with the “BSTACK” Function

Program trace with “BSTACK” is not possible on the 605U programmer.
During program processing, the following information about jump operations is entered in the block
stack (BSTACK):
• The data block that was valid before program processing exited a block.
• The relative return address
- It specifies the address where program processing will continue after the return from the
called up block.
• The absolute return
- It specifies the memory address in the program memory where program processing will
continue after the return.
You can call up this information with the “BSTACK” programmer function in the STOP operating
mode if a fault caused the CPU to go into the STOP operating mode. “BSTACK” then reports the
status of the block stack at the time the interruption occurred.
Example:
Program scanning was interrupted at function block FB2. The CPU went into the STOP mode with
the error message “TRAF” (because of incorrect DB access, e.g., DB5 is two words long and DB3
is ten words long).
“BSTACK” lets you determine the path used to reach FB2 and lets you know which DB was open
at the time of call up. “BSTACK” contains the three (marked) return addresses.
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
PB1
00 Interrupt with the
“TRAF” error
message
xx BE
PB4
OB1
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
PB2 00
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
00 JU PB1 00 C DB5
02 02 JU PB4 08 JC FB2
04 JU PB2 04
10
06
08 JC PB3 FB2
xx BE xx BE
10 00
PB3
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
2A L DW4
xx BE 00 C DB3
16 JU FB2
18 BE xx BE
Figure 5-6. Tracing the Program with “BSTACK”
5-12 EWA 4NEB 812 6120-02

Display
*BSTACK
BLOCK REL. ADDR. DB
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
Block type and PB 4 0010 5

block number
PB 2 0004 5
OB 1 0006
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
0505
Relative return Insignificant ID Number of the currently

address numbers valid data block
Figure 5-7. Example of a “BSTACK” Display on the PG 615
This display indicates that a block was called up via the path of OB1 PB2 PB4. During the
processing of this block, the programmable controller went into the STOP mode. The STOP can
have been caused by one of the following:
• A change of the operating mode switch to the STOP position
• The exceeding of the cycle time
• An error in the STEP 5 block
Refer to the ISTACK for the block that was being processed when the error occurred and for the
cause of the error.
EWA 4NEB 812 6120-02 5-13

5.4 I/O Faults
Fault
Module with fault

no
indication no Check supply
Power supply ok?
(red LED) leads.
yes yes
no Module addressable via
the process input image yes - Check module
Red LED lights. (exchange).
(PII) and the process out-
put image (PIQ) (STA- - Check program.
yes TUS VAR, FORCE VAR)
no Check no
Module power supply
supply ok? no
leads. Bus connection ok? Replace bus unit.
yes
yes Eliminate yes
Short circuit at
short
the outputs? Replace module with
circuit. yes
simulator module. Replaced module
no Is a check with STATUS is defective.
VAR or FORCE VAR
no possible?
Defective
Defective fuse module
no
yes Check connections of
other bus units and
Replace fuse. interface modules.
Figure 5-8. Analyzing the Cause of a Fault in the I/Os
5.5 System Parameters

The “SYSPAR” programmer function makes it possible to read out the system parameters (e.g.,
CPU software version) of the programmable controller (see programmer manual).
5-14 EWA 4NEB 812 6120-02

5.6 The Last Resort

The programmable controller will not go back to the RUN operating mode:
Possible cause: The battery was installed or changed when the programmable controller
was turned off.
Remedy: Perform an overall reset and load the program again.
How to perform an overall reset without a programmer

2. Remove the battery.
5. Install a battery.
Contact your local Siemens representative if the above measures are ineffective.
EWA 4NEB 812 6120-02 5-15

6 Addressing
6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1
6.2 Digital Modules ..................................... 6 - 4
6.3 Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5
6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . 6 - 6

6.4.1 Output Modules with Error Diagnostics . . . . . . . . . . . . . . . . . . . . 6 - 6
for CPU 102, Version 8MA01, Revision 5 and Higher . . . . . . . . . . 6 - 7
6.4.3 Function Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6.5 The Structure of Process Image Input and Output Tables ....... 6 - 8
6.5.1 Accessing the Process Image Input Table (PII) . . . . . . . . . . . . . . . 6 - 10
6.5.2 Accessing the Process Image Output Table (PIQ) . . . . . . . . . . . . . 6 - 11
6.6 Interrupt Process Images and Time-Controlled Program

Processing in OB13 for CPU 103, Version 8MA02 and Higher . . . . 6 - 12
6.6.1 Accessing the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12
6.6.2 Accessing the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
6.7 RAM Address Assignments ............................ 6 - 15
EWA 4NEB 812 6120-02

Figures
6-1 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1

6-2 Consecutive Numbering of Slots in a Single-Tier Configuration . . . . . . . . . 6 - 1
6-3 Slot Numbering in a Multi-Tier Configuration . . . . . . . . . . . . . . . . . . . . . . 6 - 2
6-4 Expanding from 14 to 18 Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3
6-5 Configuration of a Digital Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4
6-6 Address Assignment for Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5
6-7 Assignment of Process Images to the I/O Modules . . . . . . . . . . . . . . . . . . 6 - 9
6-8 Accesses to the PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 10
6-9 Accesses to the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 11
6-10 Accesses to the Interrupt PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 13
6-11 Accesses to the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 14
Tables
6-1 Error Messages for Output Modules with Error Diagnostics . . . . . . . . . . . . 6 - 6

6-2 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 7
6-3 Structure of the PII and the PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8
6-4 Structure of the Interrupt PII and the Interrupt PIQ . . . . . . . . . . . . . . . . . . 6 - 12
6-5 Important Addresses in the RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 15
6-6 System Data Area Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 16
EWA 4NEB 812 6120-02

S5-100U Addressing
6 Addressing
The inputs and the outputs have different assigned addresses so that you can access them
specifically. The I/O addresses are the same as the module slot addresses.
When you mount a module in a slot on a bus unit, the module is assigned a slot number and
consequently a fixed byte address in one or both process image I/O tables.
Connect the sensors and actuators to the terminal block. The terminal selected determines the
channel number.
Process image I/O

tables in the CPU Control
I/O module
program
Address in the pro-
cess image input
Slot number table (PII) Address
+
Address in the pro-
= in a
Channel number statement
cess image output
table (PIQ)
Data direction: module - CPU
Figure 6-1. Address Assignment
6.1 Slot Numbering

The programmable controller can have a maximum of four tiers. You can use up to 16 bus units
(32 slots). The slots are numbered consecutively. Numbering begins with “0” at the slot beside
the CPU. Whether a module is plugged in or not has no effect on the numbering.
Slot numbers
CPU 0 1 2 3 30 31
Figure 6-2. Consecutive Numbering of Slots in a Single-Tier Configuration
EWA 4NEB 812 6120-02 6-1

Addressing S5-100U
If the programmable controller consists of more than one tier, numbering of the expansion tiers is
continued at the slot on the extreme left.
Slot numbers
26 27 28 29 30 31
18 19 20 21 22 23 24 25
8 9 10 11 12 13 14 15 16 17
CPU 0 1 2 3 4 5 6 7
Figure 6-3. Slot Numbering in a Multi-Tier Configuration
When expanding your system, always add the new bus units to the topmost tier on the right. Other-
wise, the slot numbers on the right of the new bus units will be changed, requiring address changes
in your control program.
Note
After every expansion, check to make certain that the addressing used in the control
program is the same as that in the actual configuration.
6-2 EWA 4NEB 812 6120-02

S5-100U Addressing
Example: Expanding from 14 to 18 slots
Existing configuration New bus units
8 9 10 11 12 13
CPU 0 1 2 3 4 5 6 7
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
Correct expansion procedure
8 9 10 11 12 13 14 15 16 17
The new bus units are added at

the right. The interface module
is moved correspondingly to the
right. The old slot numbers are
retained. Continue numbering
CPU 0 1 2 3 4 5 6 7
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
the new slots sequentially.
Incorrect expansion procedure
8 9 10 11 12 13 14 15 16 17
8 9 10 11 12 13
The slot numbers of the old bus

units move to numbers 12 to 17.
The new slots are given the num-
bers 8 to 11.
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
CPU 0 1 2 3 4 5 6 7
Figure 6-4. Expanding from 14 to 18 Slots
EWA 4NEB 812 6120-02 6-3

Addressing S5-100U
6.2 Digital Modules

Digital modules can be plugged into all slots (0 through 31).
Only two information states (“0” or “1”, OFF or ON) per channel can be transferred from or to a
digital module. The memory requirement is one bit.
Each channel of a digital module is displayed by a bit. This is the reason that every bit must be
assigned its own number. Use the following form for a digital address:
x . y
Bit number (channel number)
Byte number (slot number)
Figure 6-5. Configuration of a Digital Address
The “X.Y” address consists of the following two components:

• Byte Address X (Slot Number X)
- The byte address is the same as the number of the slot the module is plugged into.
• Channel Number Y (Bit Address Y)
- The channel number comes from the connection of the actuators or sensors to the terminals
of the terminal block. The assignment for the channel number and the terminal number is
printed on the frontplate of the module.
Example: Address Assignment

You are connecting a 2-wire BERO proximity limit switch to an 8 x 24-V DC digital input module
(6ES5 421-8MA11) at terminal 3. The other wire is routed to an L+ (positive supply voltage) termi-
nal block (see section 3.2 for wiring). The module is plugged into slot 3.
This defines the address used by the control program to evaluate the signal states of the BERO.
• The byte address is 3 since the module is plugged into slot 3.
• As shown on the frontplate, channel number 1 is used.
• The complete address for the BERO switch is 3.1.
Note
You can address 4-channel digital modules only with channel numbers 0 through 3. The
channel numbers 4 through 7 printed on the frontplate are relevant only for the ET 100U
system.
6-4 EWA 4NEB 812 6120-02

S5-100U Addressing
6.3 Analog Modules

You can plug analog modules only into slots 0 through 7. Transfer of 65,536 different items of
information is possible per channel from or to an analog module. The memory requirement is
16 bits=2 bytes=1 word. The modules are addressed byte-by-byte or word-by-word with load or
transfer operations.
The programmable controller takes this increased memory requirement into account when an analog
module is plugged in.
• Eight bytes (=four words) are reserved per slot.
• Two bytes (=1 word) are reserved per channel.
• The slot addressing area is changed.
• The permissible address space extends from byte 64 (slot 0, channel 0) to byte 127 (slot 7,
channel 3).
Slot number 0 1 2 3 4 5 6 7 Channel number
64+65 72... 80... 88... 96... 104... 112... 120... 0

CPU
66+67 1
68+69 2
70+71 ...79 ...87 ...95 ...103 ...111 ...119 ...127 3
Figure 6-6. Address Assignment for Analog Modules
Examples: 1) Bytes 88+89=analog module in slot 3, channel number 0

2) Channel 1 address of an analog module in slot 5?
Solution: bytes 106+107
Note
Any combination of analog and digital modules is possible in slots 0 through 7.
EWA 4NEB 812 6120-02 6-5

Addressing S5-100U
6.4 Combined Input Modules and Output Modules

With these modules it is possible to write data from the control program to the module and to read
in data from the module to the control program.
The byte addresses in the process image input table (PII) and process image output table (PIQ) are
identical. The meaning of the transferred data is usually different.
6.4.1 Output Modules with Error Diagnostics
In addition to the fault LED (red LED), the following output modules can signal errors to the CPU.
4 x 24 V DC / 0.5 A (6ES5 440-8MA11)
4 x 24 V DC / 2.0 A (6ES5 440-8MA21)
4 x 24 to 60 V DC / 0.5 A (6ES5 450-8MB11)
You can read the error messages on input channels I X.0 and I X.1 (not with CPU 100, version
8MA01).
The following error messages are possible.
Table 6-1. Error Messages for Output Modules with Error Diagnostics
Address Type of Error
I X.0 Short circuit on an output channel / fuse blown

or
no-load voltage
I X.1 Defective module (output transistor shorted)

X is the byte address (slot number) of the output module
Signal state “1” indicates an error is present. The PII is set to “0” for output modules without error
diagnostics.
6-6 EWA 4NEB 812 6120-02

S5-100U Addressing

for CPU 102, Version 8MA01, Revision 5 and Higher
Plug the module only into slots 0 through 7.
This module occupies the same address space as an analog module. However, only the first two of
the eight reserved bytes are used.
The address consists of byte address n or n+1 and channel number Y. “n” is the start address of
a slot, the first of the reserved bytes (e.g., byte 64 for slot 0). “n+1” is therefore the second of the
reserved bytes. The designations “n” and “n+1” are printed on the frontplate of the module.
The input and output information occupies the same addresses.
The channel number is defined by the connection of the actuators and sensors to the crimp
connector. The channel numbers are printed on the frontplate.
Table 6-2. Address Assignment
Slot Number 0 1 2 3 4 5 6 7
Address Channel 64.0 to 72.0 to 80.0 to 88.0 to 96.0 to 104.0 to 112.0 to 120.0 to
PII (IN) n.0 to n.7 64.7 72.7 80.7 88.7 96.7 104.7 112.7 120.7
and
PIQ Channel 65.0 to 73.0 to 81.0 to 89.0 to 97.0 to 105.0 to 113.0 to 121.0 to
(OUT) n+1.0 to
n+1.7 65.7 73.7 81.7 89.7 97.7 105.7 113.7 121.7
Examples: Determining the Address

1) You plugged the module into slot 4 and connected an actuator at byte n,
channel 4. The address is 96.4.
2) Address 113.3 indicates a sensor or an actuator is connected at byte n+1,
channel 3. The module is plugged into slot 6.
6.4.3 Function Modules
Function modules have module-specific addressing. Some function modules are addressed like
digital modules, and other function modules are addressed like analog modules. The addressing for
each function module is explained in chapter 15.
EWA 4NEB 812 6120-02 6-7

Addressing S5-100U
6.5 The Structure of Process Image Input and Output Tables

Information about inputs is stored in the process image input table (PII). Information about outputs
is stored in the process image output table (PIQ).
The PII and the PIQ each have an area of 128 bytes in the RAM memory.
The PII and the PIQ have identical structures. The PII and the PIQ can be divided into three address
areas as shown in Table 6-3.
Table 6-3. Structure of the PII and the PIQ

Byte Address in the PII
and PIQ Module Slot Number
0 to 31 Digital modules 0 to 31
32 to 63 Unassigned address space
64 to 127 Analog modules 0 to 7
• The address space for bytes 0 through 31 is reserved for information from or to modules that
are addressed like digital modules.
• The unassigned address space in bytes 32 to 63 can be used to store intermediate results.
• The address space in bytes 64 to 127 is reserved for information from or to modules that are
addressed like analog modules.
6-8 EWA 4NEB 812 6120-02

S5-100U
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa
Bit
EWA 4NEB 812 6120-02

process I/O images.
Slot
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaa
Unassigned
address area
7 6 5 4 3 2 1 0
CPU
4
3
2
1
0
67
66
65
64
31
127
Byte
0
AI
1
AQ
PII
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
°
°
°
°
2
DI
aaaaaaaaaaaaaa
°
°
°
°
°
°
°
°
3
DE
°
°
°
°
°
°
°
°
4
DI DQ
Unused areas
...
PIQ
°
°
°
°
27
DQ
4
3
2
1
0
28
127
79
72
65
64
31
27
Byte
aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
29
Bit
Figure 6-7. Assignment of Process Images to the I/O Modules

30
Unassigned
31
address area
7 6 5 4 3 2 1 0
Figure 6-7 shows a possible programmable controller configuration and storage of information in the
Addressing
6-9
Addressing S5-100U
6.5.1 Accessing the Process Image Input Table (PII)

During a data cycle, data is read into the process image input table (PII) from input modules (see
section 2.2.2 - Data Cycle). This data is available to the control program for evaluation in the next
program processing cycle.
Access to the PII is expressed by the operand identifiers “I”, “IB”, or “IW” in a statement in the
control program.
The letter “L” identifies the “Load” operation (see chapter 8). The letter “A” identifies the “AND
logic” operation (see chapter 8).
PII
• Bit-by-bit reading “I <bit address>” Bit number
Example: Reading in the signal state of
7 6 5 4 3 2 1 0
channel 2 of a 4-channel digital input module
in slot 2
aaaaaaaa
aaaa
Byte 2
A I 2.2
• Byte-by-byte reading “IB <byte address>”

Example: Reading in the signal states of all
channels of an 8-channel digital input module
in slot 12
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaa
L IB 12 Byte 12
15 0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
ACCU 1
High byte Low byte
• Word-by-word reading “IW <word address>”

Example: Reading in the analog value of
channel 3 of a 4-channel analog input module in
slot 4
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
L IW 102
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
Byte 102
15 0 Byte 103
ACCU 1
High byte Low byte
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
Always set to “0”
Figure 6-8. Accesses to the PII
6-10 EWA 4NEB 812 6120-02

S5-100U Addressing
6.5.2 Accessing the Process Image Output Table (PIQ)
During a program cycle, data coming from the control program to the output modules is written into
the process image output table (PIQ). The data is transferred to the output modules in the following
data cycle.
Access to the PIQ is expressed by the operand identifiers “Q”, “QB”, or “QW” in a statement in
the control program.
The letter “T” identifies the “Transfer” operation (see Chapter 8). The “=” character assigns the
result of a logic operation (RLO) to the operand that follows the character (see chapter 8).
PIQ
• Bit-by-bit writing Bit number

“Q <bit address>” 7 6 5 4 3 2 1 0
Example: Writing the signal state to
channel 6 of an 8-channel digital output
module in slot 4
aaaaaaaa
aaaaaaaa
= Q 4.6 Byte 4
• Byte-by-byte writing
“QB <byte address>”
Example: Writing the signal states to all
channels of an 8-channel digital output
module in slot 29
T QB 29
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
Byte 29
15 0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
ACCU 1
High byte Low byte
• Word-by-word writing
“QW <word address>”
Example: Writing an analog value to
channel 2 of a 4-channel analog output
module in slot 6
T QW 116
Byte 116
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
Byte 117
15 0
ACCU 1
High byte Low byte
Figure 6-9. Accesses to the PIQ
EWA 4NEB 812 6120-02 6-11

Addressing S5-100U
6.6 Interrupt Process Images and Time-Controlled Program Processing

in OB13 for CPU 103, Version 8MA02 and Higher
In the event of a time-controlled or process interrupt, the CPU does not access the I/O modules
directly. The CPU stores its information in interrupt process images.
• The interrupt process images are used only for time-controlled or interrupt-driven program
processing.
• The interrupt process images and the “normal” process images have identical structures.
• The interrupt process input image (interrupt PII) and interrupt process output image (interrupt
PIQ) take up an area of 128 bytes each in the RAM.
The interrupt PII and interrupt PIQ can be divided into three address areas as shown in Table 6-4.
Table 6-4. Structure of the Interrupt PII and the Interrupt PIQ
Byte address in interrupt Module Slot number
PII and interrupt PIQ
0 to 31 Digital modules 0 to 31
32 to 63 Unassigned address space
64 to 127 Analog modules 0 to 7
Note
The interrupt process images can be accessed by byte or word operations only.
6.6.1 Accessing the Interrupt PII
• The interrupt PII can only be accessed in connection with time-controlled or interrupt-driven
program processing.
• Data from inputs is read into the interrupt PII only at the beginning of time-controlled program
processing. This data is available only to the time-controlled program for evaluation.
6-12 EWA 4NEB 812 6120-02

S5-100U Addressing
Time-Controlled Program Processing

Access to the interrupt PII is expressed by the “PB” or “PW” operand identifiers in a statement in
the time-controlled program.
The letter “L” represents the “Load” operation (see chapter 8).
Interrupt PII
• Byte-by-byte reading “PB <byte address>”

Example: Reading in the signal states of all
channels of an 8-channel digital input module
in slot 21
L PB/PY* 21
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaaaaa
Byte 21
15 0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
ACCU 1
High byte Low byte
• Word-by-word reading “PW <word address>”

Example: Reading in the analog value of
channel 2 of a 4-channel analog input module
in slot 1
L PW 76
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
Byte 76
Byte 77
15 0
ACCU 1
High byte Low byte
* depending on the programmer you have
Figure 6-10. Accesses to the Interrupt PII
Interrupt-Driven Program Processing

• When a process interrupt occurs, only the data of the interrupt inputs, slots 0 and 1, is read into
the interrupt PII.
• Only this data of the interrupt PII is available to the interrrupt-driven program for evaluation.
• In a statement in the interrrupt-driven program, access to the interrupt PII is possible only with
the following operands: PB0, PB1, and PW0.
• If other parameters are specified, the CPU goes into the STOP mode and the “NNN” error
message is specified in the ISTACK. See section 5.2.
EWA 4NEB 812 6120-02 6-13

Addressing S5-100U
6.6.2 Accessing the Interrupt PIQ

When accessing the interrupt PIQ, the following rules apply.
• Data can be written to the interrupt PIQ only within time-controlled or interrupt-driven program
processing.
• Data from a time-controlled or interrupt-driven program to external outputs is written during time-
controlled or interrupt-driven program processing both to the “normal” PIQ and the interrupt
PIQ.
• Data from the interrupt PIQ is read out to the outputs in the next interrupt output data cycle.
• The PIQ is copied to the interrupt PIQ after the OB1 program cycle.
Note
The interrupt output data cycle is executed only after the interrupt PIQ has been written
to.
Access to the interrupt PIQ is expressed by the “PB” or “PW” operand identifiers in a statement in
the time-controlled or interrrupt-driven program.
The letter “T” identifies the “Transfer” operation (see chapter 8).
Interrupt PIQ
• Byte-by-byte writing
“PB <byte address>”
Example: Writing signal states to all
channels of an 8-channel digital output
module in slot 13
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
T PB/PY* 13 Byte 13
15 0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
ACCU 1
High byte Low byte
• Word-by-word writing
“PW <word address>”
Example: Writing an analog value to channel 3
of a 4-channel analog output module in slot 5
T PW 110
Byte 110
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
Byte 111
15 0
ACCU 1
High byte Low byte
* depending on the programmer you have
Figure 6-11. Accesses to the Interrupt PIQ
6-14 EWA 4NEB 812 6120-02

S5-100U Addressing
6.7 RAM Address Assignments
The following table gives an overview of the major addresses in the RAM of the three CPUs (in
hexadecimal code).
Table 6-5. Important Addresses in the RAM
CPU 100 102* 103
Program memory EE00 to FFFF D000 to DFFF 8000 to CFFF
Memory submodule C000 to DFFF 4000 to 5FFF 0000 to 7FFF
PII, digital E400 to E41F EF00 to EF1F EF00 to EF1F

PII, analog E440 to E47F EF40 to EF7F EF40 to EF7F
PIQ, digital E480 to E49F EF80 to EF9F EF80 to EF9F

PIQ, analog E4C0 to E4FF EFC0 to EFFF EFC0 to EFFF
Timers E280 to E29F EC00 to EC39 EC00 to ECFF

Retentive counters E2A0 to E2AF ED00 to ED0F ED00 to ED0F
Non-retentive counters E2B0 to E2BF ED10 to ED3F ED10 to ED3F

Retentive flags E300 to E33F EE00 to EE3F EE00 to EE3F
Non-retentive flags E340 to E37F EE40 to EE7F EE40 to EE7F
Module address list
OB E080 to E0FF FC80 to FCFF DC00 to DDFF
FB E100 to E17F FD00 to FEFF DE00 to DFFF

PB E180 to E1FF FF00 to FF7F E000 to E1FF
SB ---- ---- E200 to E3FF
DB E200 to E27F FF80 to FFFF E400 to E5FF
System data EA00 to EBFF EA00 to EBFF EA00 to EBFF

* Program memory; block address list only in TEST mode.
EWA 4NEB 812 6120-02 6-15

Addressing S5-100U
The following table gives an overview of the most important system data in the system data area.
Table 6-6. System Data Area Assignment
System data Chapter/

Contents
word Section Reference
5 to 7 ISTACK (Interrupt STACK) 5.2
8 to 12 Integral real-time clock 12

33 First free program memory address
35 Program memory starting address
37 Program memory end address

40 to 45 CPU version, software release
57 to 63 SINEC L1 13
96 Scan monitoring time (value . 10 ms)
97 Calling interval for OB 13 for time-controlled program 7.4.4

processing (value . 10 ms)
128 to 159 BSTACK (Block STACK) 5.3.2

203 to 214 ISTACK (Interrupt STACK) 5.2
6-16 EWA 4NEB 812 6120-02

7 Introduction to STEP 5
7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.1.1 Methods of Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1
7.1.2 Operand Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.1.3 Circuit Diagram Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3
7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.2.1 Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4
7.2.2 Structured Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5
7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.3.1 Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7.3.2 Program Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.3 Sequence Blocks, for CPU 103 and Higher . . . . . . . . . . . . . . . . . 7 - 11
7.3.4 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 11
7.3.5 Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

7.4.1 Program Processing with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7.4.2 START-UP Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7.4.3 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7.4.4 Time-Controlled Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 28
7.4.5 Interrupt-Driven Program Processing, for CPU 103
Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 29
7.5 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30

7.5.1 Changing Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.2 Changing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.5.3 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7.6 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 31
EWA 4NEB 812 6120-02

Figures
7-1 Compatibility of STEP 5 Methods of Representation . . . . . . . . . . . . . . . . . 7 - 2

7-2 Nesting Depth of Programmed Organization Blocks . . . . . . . . . . . . . . . . . 7 - 6
7-3 Structure of a Block Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8
7-4 Example of Organization Block Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 10
7-5 Programming a Function Block Parameter, for CPU 103 and Higher . . . . . . 7 - 13
7-6 Programming a Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16
7-7 Example of Data Block Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 17
7-8 Validity Areas of Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 17
7-9 Programm Scanning with CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
7-10 Mode Change for CPU 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 21
7-11 Display of the Processing Mode in the ISTACK . . . . . . . . . . . . . . . . . . . . 7 - 22
7-12 Setting the Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 24
7-13 Cyclic Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26
7-14 Calculating the Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 27
7-15 Compressing the Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30
7-16 Bit Assignment of a 16-Bit Fixed-Point Binary Number . . . . . . . . . . . . . . . 7 - 31
7-17 BCD and Decimal Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 32
Tables
7-1 Comparison of Operation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 2

7-2 Comparison of Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7
7-3 Overview of Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 9
7-4 Block Parameter Types and Data Types with Permissible Actual
Parameters, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14
7-5 Programming Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18
7-6 Comparison of Number Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 32
EWA 4NEB 812 6120-02

S5-100U Introduction to Step 5
7 Introduction to STEP 5
This chapter explains how to program the S5-100U. It describes how to write a program, how the
program is structured, the types of blocks the program uses, and the number representation of the
STEP 5 programming language.
7.1 Writing a Program

A control program specifies a series of operations that tell the programmable controller how it has to
control a system. For example, a control program might be the series of operations that tell the
S5-100U how to use open-loop control or closed-loop control for a specific system. You must write
the program in a special programming language and according to specific rules so that the pro-
grammable controller can understand it. The programming language that has been developed for the
SIMATIC S5 family is called STEP 5.
7.1.1 Methods of Representation
The following methods of representation are possible with the STEP 5 programming language.
• Statement List (STL)
STL represents the program as a sequence of operation mnemonics. A statement has the
following format:
Operation
Operand
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
002: A I 0.1
Parameter
Operand ID
Relative address of the statement
in a particular block
The operation tells the programmable controller what to do with the operand. The parameter
indicates the operand address.
• Control System Flowchart (CSF)
CSF represents logic operations with graphics symbols.
• Ladder Diagram (LAD)
LAD graphically represents control functions with circuit diagram symbols.
• GRAPH 5, for CPU 103 and higher
GRAPH 5 describes the structure of sequence control systems.
You cannot use CSF, LAD, or GRAPH 5 with the PG 605 and PG 615 programmers.
EWA 4NEB 812 6120-02 7-1

Introduction to STEP 5 S5-100U
Each method of representation has its own special characteristics. A program block that has been
programmed in STL cannot necessarily be output in CSF or LAD. The three methods of graphic re-
presentation are not compatible. However, programs in CSF or LAD can always be converted to
STL. Figure 7-1 illustrates these points in a diagram.
CSF LAD
STL
Figure 7-1. Compatibility of STEP 5 Methods of Representation
The STEP 5 programming language has the following three operation types:
• Basic
• Supplementary
• System
Table 7-1 provides further information about these operations.
Table 7-1. Comparison of Operation Types
STEP 5 PROGRAMMING LANGUAGE
Supplementary
Basic Operations System Operations
Operations
Application In all blocks Only in function blocks Only in function blocks
Methods of
STL, CSF, LAD STL STL
representation
For users with good
Special features
system knowledge
Refer to Chapter 8 for a description of all operations and for programming examples.
7-2 EWA 4NEB 812 6120-02

7.1.2 Operand Areas
The STEP 5 programming language has the following operand areas:
I (inputs) Interfaces from the process to the programmable controller
Q (outputs) Interfaces from the programmable controller to the process
F (flags) Memory for intermediate results of binary operations
D (data) Memory for intermediate results of digital operations
T (timers) Memory for implementing timers
C (counters) Memory for implementing counters
P (peripherals) Interfaces from the process to the programmable controller
K (constants) Defined numeric values
OB, PB, SB
FB, DB (blocks) Program structuring aids
Refer to Appendix A for a listing of all operations and operands.
7.1.3 Circuit Diagram Conversion
If your automation task is in the form of a circuit diagram, you must convert it to STL, CSF, or LAD.
EWA 4NEB 812 6120-02 7-3

Example: Hard-Wired Control

A signal lamp (H1) is supposed to light up when a normally open contact (S1) is acti-
vated and a normally closed contact (S2) is not activated.
Programmable Control
The signal lamp is connected to an output (i.e., Q 1.0). The signal voltages of the two
contacts are connected to two programmable controller inputs (i.e., I 0.0 and I 0.1).
The S5-100U scans to see if the signal voltages are present (signal state “1” at the
activated normally open contact or non-activated normally closed contact). Both signal
states are combined through logic AND. The result of logic operation (RLO) is assigned
to output Q 1.0 (the lamp lights).
Circuit Diagram STL CSF LAD
S1
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
A I 0.0 I 0.0 I 0.0 I 0.1 Q 1.0

S2
A I 0.1 & ( )
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
I 0.1 Q 1.0
= Q 1.0
H1
7.2 Program Structure
An S5-100U program can be one of the two following types:

• Linear
• Structured
Sections 7.2.1 and 7.2.2 describe these program types.
7.2.1 Linear Programming
Programming individual operations in one section (block) is sufficient for handling simple automation
jobs. For the S5-100U, this is organization block 1 (see section 7.3.1). The S5-100U scans this
block cyclically. After the S5-100U scans the last statement, it goes back to the first statement and
begins scanning again. Please note the following rules:
• When OB1 is called, five words are assigned to the block header in the program memory (see
section 7.3).
• Normally, a statement takes up one word in the program memory.
Two-word statements also exist (e.g., with the operation “Load a constant”). Count these
statements twice when calculating the program length.
• Like all blocks, OB1 must be terminated by a Block End statement (BE).
7-4 EWA 4NEB 812 6120-02

7.2.2 Structured Programming
To solve complex tasks, it is advisable to divide a program into individual, self-contained program
parts (blocks). This procedure has the following advantages:
• Simple and clear programming, even for large programs
• Program parts can be standardized
• Easy alterations
• Simple program test
• Simple start-ups
• Subroutine techniques (block call from different locations)
The STEP 5 programming language has the following five block types:
• Organization Block (OB)
Organization blocks manage the control program.
• Program Block (PB)
Program blocks arrange the control program according to functional or technical aspects.
• Sequence Block (SB)
Sequence blocks are special blocks that program sequence controls. They are handled like
program blocks. (This is available for CPU 103 and higher.)
• Function Block (FB)
Function blocks are special blocks for programming frequently recurring or especially complex
program parts (e.g., reporting and arithmetic functions). You can assign parameters to them
(available for CPU 103 and higher). They have an extended set of operations (e.g., jump
operations within a block).
• Data Block (DB)
Data blocks store data needed to process a control program. Actual values, limiting values, and
texts are examples of data.
EWA 4NEB 812 6120-02 7-5

The program uses block calls to exit one block and jump to another. You can therefore nest pro-
gram, function, and sequence blocks randomly up to 16 levels (see section 7.3). Nesting can be up
to 32 levels for CPU 103 version 8MA03.
Note
When calculating the nesting depth, note that the system program in the programmable
controller can call an organization block automatically under certain circumstances
(e.g., OB2).
The total nesting depth is the sum of the nesting depths of call programmed organization blocks. If
nesting goes beyond 16 levels (32 levels for CPU 103 version 8MA03), the CPU goes into the
STOP mode with the error message “STUEB,” block stack overflow (see section 5.2). Figure 7-2
illustrates the nesting principle.
OB 1
.......
.......
Level 1 Level 2 Level 3 ....... Level 16
Figure 7-2. Nesting Depth of Programmed Organization Blocks
7-6 EWA 4NEB 812 6120-02

S5-100U Introduction to STEP 5
7.3 Block Types
The following table lists the most important characteristics of the individual block types:
Table 7-2. Comparison of Block Types
OB1 PB SB FB2 DB3
Number 64 64 64 62
CPU 100 OB0 to OB63 PB0 to PB63 FB0 to FB63 DB2 to DB63
Number 64 64 64 62
CPU 102 OB0 to OB63 PB0 to PB63 FB0 to FB63 DB2 to DB63
Number 256 256 256 2562 254
CPU 103 OB0 to OB255 PB0 to PB255 SB0 to SB255 FB0 to FB255 DB2 to DB255
Length (max.)
4 Kbytes 4 Kbytes 4 Kbytes 256 data words
CPU 100
Length (max.)
4 Kbytes 4 Kbytes 4 Kbytes 256 data words
CPU 102
Length (max.)
8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes
CPU 103
Operations Basic Basic Basic Basic, Bit patterns,

set operations operations operations supple- numbers,
(contents) mentary, texts
system
operations
Representa- STL, CSF, STL, CSF, STL, CSF, STL

tion methods LAD LAD LAD
Block header 5 words 5 words 5 words 5 words 5 words

length
1 The operating system calls up particular OBs automatically (see section 7.3.1 and 9.3).
2 Function blocks are already integrated into the operating system (see section 9.2).
3 Data blocks DB0 and DB1 are reserved.
EWA 4NEB 812 6120-02 7-7

•
•
7-8
byte
order)
Absolute
addresses
Programming
Block Structure
(in ascending
1. Specify the block type (e.g., PB).

2. Specify the block number (e.g., 27).

Each block consists of the following parts:
3. Enter the control program statements.

4. Terminate the block with the “BE” statement.

The block body that has the STEP 5 program or data
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Program your blocks as follows (does not apply to data blocks):

- Generated by the programmer when it transforms the block

The block header that specifies the block type, number, and length
Figure 7-3. Structure of a Block Header

pattern
Block type
Block length
Block number
Library number
Programmer ID
Synchronization
EWA 4NEB 812 6120-02

S5-100U
•
•
•
aaaaaaaa
aaaaaaaa
aaaa
OB2
OB1
7.3.1
OB31
OB34
OB22
OB21
OB13
OB251
OB No.
S5-100U
EWA 4NEB 812 6120-02

Battery failure
When power returns
PID control algorithm

to events or at certain times:
Handling start-up procedures

Organization Blocks
Cyclic program processing

- By interrupts (OB2 and OB13)
Function
Interrupt-driven program processing

Interrupt-driven program processing
Time-controlled program processing

- By a switch from STOP to RUN (OB21)
When starting manually (STOP to RUN)
Handling programming errors and device errors

Table 7-3 provides an overview of organization blocks.
Scan time triggering (resets scan time monitor)
OB is ready or is supported by the operating system
must call the organization blocks from the control program.

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The OB is already programmed. You must call up the OB.

aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaa aaaaaa
Organization blocks are handled in one of the following three ways:

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Organization block OB1 is called cyclically by the operating system.

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CPU 100
You must program the OB. The operating system calls up the OB.
Table 7-3. Overview of Organization Blocks

- By a switch from Power OFF to Power ON (OB22 (see Table 7-3))
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aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaa
CPU 102
OB integrated in
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You can program all organization blocks using parameters from the permissible range. CPU 100
Some organization blocks are event-driven or time-controlled. They can be called in response
blocks). They can be called by the control program (for CPU 103 and higher; see section 9.3).
CPU 103
and CPU 102 use organization blocks OB0 to OB63. CPU 103 uses OB0 to OB255. However, you
Organization blocks (OB) form the interface between the operating system and the control program.
Some other organization blocks represent operating functions (similar to the the integral function
7-9
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aaaaaaaa
7-10
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaa
organization blocks.
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaa
System program
* For CPU 103 and higher
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
OB1
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
OB21/OB22
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
FB2
PB1
Control program
SB1*
FB61
Figure 7-4. Example of Organization Block Use

Figure 7-4 shows how to set up a structured control program. It also illustrates the significance of
EWA 4NEB 812 6120-02

S5-100U
7.3.2 Program Blocks
Self-contained program parts are programmed in program blocks (PB).

Special feature: Control functions can be represented graphically in program blocks.
Call
Block calls JU and JC activate program blocks. You can program these operations in all block types
except data blocks. Block call and block end cause the RLO to be reloaded. However, the RLO
can be included in the “new” block and be evaluated there.
7.3.3 Sequence Blocks, for CPU 103 and Higher
Sequence blocks (SB) are special program blocks that process sequence controls. They are treated
like program blocks.
7.3.4 Function Blocks
Frequently recurring or complex control functions are programmed in function blocks (FB).
Function blocks have the following special features.

• FBs can be assigned parameters (for CPU 103 and higher).
- Actual parameters can be assigned when the block is called (for CPU 103 and higher).
• FBs have an extended set of operations not available to other blocks.
• The FB program can be written and documented in STL only.
If you are using CPU 102 version 8MA02 or higher, you have the following types of function blocks
available:
• FBs that you can program
• FBs that are integrated in the operating system (see section 9.2)
• FBs that are available as software packages (standard function blocks, see Catalog ST 57)
EWA 4NEB 812 6120-02 7-11

Block Header
Besides the block header, function blocks have organizational information that other blocks do not
have.
A function block's memory requirements consist of the following:

• Block header (five words) as for other blocks
• Block name (five words)
• Block parameter for parameter assignment (three words per parameter)
Creating a Function Block, for CPU 103 and Higher
In contrast to other blocks, parameters can be assigned to FBs.

To assign parameters, you must program the following block parameter information.
• Block Parameter Name (formal operand)
Each block parameter as a formal operand is given a designation (DES). Under this designation
it is replaced by an actual parameter when the function block is called.
The name can be up to four characters long and must begin with an alpha character. You can
program up to 40 block parameters per function block.
• Block Parameter Type
You can enter the following parameter types:
-I input parameters
-Q output parameters
-D data
-B blocks
-T timers
-C counters
In graphic representation, output parameters appear to the right of the function symbol. Other
parameters appear to the left.
• Block Parameter Data Type
You can specify the following data types:
- BI for operands with a bit address
- BY for operands with a byte address
-W for operands with a word address
-K for constants
7-12 EWA 4NEB 812 6120-02

When assigning parameters, enter all block parameter specifications.
Block header
Name
NAME: EXAMPLE
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aaaaaa
DES: IN 1 I BI Block parameter

DES: IN 2 I BI Name
Block
parameter DES: OUT 1 Q BI
. Data type
.
. Parameter type
: A = IN 1
: A = IN 2
Control
program : == OUT 1
.
.
.
Memory assignment Program example
Figure 7-5. Programming a Function Block Parameter, for CPU 103 and Higher
EWA 4NEB 812 6120-02 7-13

Table 7-4. Block Parameter Types and Data Types with Permissible Actual
Parameters, for CPU 103 and Higher
Parameter
Data Type Permissible Actual Parameters
Type
I, Q BI for an operand with bit address I x.y Inputs
Q x.y Outputs
F x.y Flags
BY for an operand with byte address IB x Input bytes

QB x Output bytes
FY x Flag bytes
DL x Data bytes left
DR x Data bytes right
PY x Peripheral bytes*
W for an operand with word address IW x Input words

QW x Output words
FW x Flag words
DW x Data words
PW x Peripheral words*
D KM for a binary pattern (16 digits) Constants

KY for two absolute numbers, one byte each,
each in the range from 0 to 255
KH for a hexadecimal pattern (maximum 4
digits)
KS for a character (maximum 2
alphanumeric characters)
KT for a time (BCD-coded time) with time
base 1.0 to 999.3
KC for a count (BCD-coded) 0 to 999
KF for a fixed-point number in the range
from -32768 to +32767
B Type designation not permitted DBx Data blocks. The C DBx operation is
executed.
OBx Organization blocks are called
unconditionally (JU ... x).
FBx Function blocks (permissible without
parameters only) are called
unconditionally (JU..x).
PBx Program blocks are called
SBx Sequence blocks are called
T Type designation not permitted T Timer. The time should be assigned

parameters as data or be programmed
as a constant in the function block.
C Type designation not permitted C Counter. The count should be

assigned parameters as data or be
programmed as a constant in the
function block.
* Not permitted for integral FBs
Calling a Function Block

Like other blocks, function blocks are stored under a specific number in the program memory (e.g.,
FB47). The numbers 240 to 255 are reserved for the integral function blocks (in CPU 103 version
8MA02 and higher).
You can program function block calls in all blocks except data blocks.
7-14 EWA 4NEB 812 6120-02

A function block call consists of the following parts:

• Call statement
- JU FBx unconditional call (Jump Unconditional)
- JC FBx call if RLO = 1 (Jump Conditional)
• Parameter list (only if block parameters were defined in the FB)
Function blocks can be called only if they have been programmed. When a function block call is
being programmed, the programmer requests the parameter list for the FB automatically if block
parameters have been defined in the FB.
Setting Parameters for a Function Block

The program in the function block specifies how the formal operands (parameters defined as “DES”)
are to be processed.
As soon as you have programmed a call statement (for example JU FB2), the programmer displays
the parameter list. The parameter list consists of the names of the parameters. Each parameter
name is followed by a colon (:). You must assign actual operands to the parameters. The actual
operands replace the formal operands defined in the FB when the FB is called, so that the FB
operates with the actual operands.
A parameter list has a maximum of 40 parameters.
Example: The name (DES) of a parameter is IN1, the parameter type is I (as in input), the data
type is BI (as in bit). The formal operand for the FB has the following structure:
DES: IN1 I BI
Specify in the parameter list of the calling block which actual operand is to replace the
formal operand in the FB call. In our example it is : I 1.0.
Enter in the parameter list:
IN1: I 1.0
When the FB is called, it replaces the formal operand “IN1” with the actual operand
“I 1.0”.
Figure 7-6 provides you with a detailed example of how to set parameters for a function block.
The FB call takes up two words in the internal program memory. Each parameter takes up an
additional memory word.
You can find the memory requirements for standard function blocks and the run times in the
specifications in Catalog ST 57.
The name of the function block is stored in the function block. The designations (DES) of the
function block inputs and outputs that appear on the programmer during programming are also
stored in the function block. Before you begin programming on the programmer, you must choose
one of the following two options:
• Transfer all necessary function blocks to the program diskette (for off-line programming)
• Input all necessary function blocks directly into the program memory of the programmable
controller
EWA 4NEB 812 6120-02 7-15

Executed
PB 3 FB 5 program
NAME : EXAMPLE
DES: X1 I BI
DES: X2 I BI
: JU FB5 DES: X3 Q BI
: A = X1
NAME : EXAMPLE : A = X2 First call
X1 : I 0.0 : = = X3 A I 0.0
Parameter list
X2 : F 1.3 for first call : BE A F 1.3
X3 : Q 1.0 = Q 1.0
. Formal operands
. Actual operands
: A I 0.1
: JC FB5
NAME : EXAMPLE Second call
X1 : I 0.3 A I 0.3
Parameter list
X2 : I 0.2 for second call A I 0.2
X3 : Q 1.0 = Q 1.0
Formal operands
Figure 7-6. Programming a Function Block
7.3.5 Data Blocks
Data blocks (DB) store data to be processed in a program.
The following data types are permissible:

• Bit pattern (representation of controlled system states)
• Hexadecimal, binary or decimal numbers (times, results of arithmetic operations)
• Alphanumeric characters (ASCII message texts)
7-16 EWA 4NEB 812 6120-02

Programming Data Blocks

Begin programming a data block by specifying a block number between 2 and 63 for CPU 100 or
CPU 102, and between 2 and 255 for CPU 103. DB0 is reserved for the operating system, DB1 for
setting parameters for internal functions (see section 9.1). Data is stored in this block in words.
If the information takes up less than 16 bits, the high-order bits are padded with zeros. Data input
begins at data word 0 and continues in ascending order. A data block can hold up to 256 data
words. You can call up or change the data word contents with load or transfer operations.
Input Stored Values
0000 : KH = A13C DW0 A13C

0001 : KT = 100.2 DW1 2100
0003 : KF = +21874 DW2 5572
Figure 7-7. Example of Data Block Contents
You can also create or delete data blocks in the control program (see section 8.1.8).
Program Processing with Data Blocks

• A data block must be called in the program with the C DBx operation (x = DB number) before it
can be accessed.
• Within a block, a data block remains valid until another data block is called.
• When the program jumps back into the higher-level block, the data block that was valid before
the block call is again valid.
• After OB1, 2, 13, 21, 22 have been called by the operating system, no DB is valid.
Valid Valid
DB PB7 PB20 DB
C DB10 DB10
DB10
C DB11
JU PB20
DB11
DB10
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aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
When PB20 is called, the valid data area is entered into memory.
When the program jumps back, this area is reopened.
Figure 7-8. Validity Areas of Data Blocks
The Function of DB1

DB1 is used for special functions. DB1 is already integrated into CPU 103 version 8MA03 and
higher and contains (default) values that you can either accept or change (see section 9.1). DB1 is
evaluated once during start-up: either after Power ON or after a transition from STOP to RUN.
EWA 4NEB 812 6120-02 7-17

7.4 Program Processing
Some of the organization blocks (OBs) are responsible for structuring and managing the control
program.
These OBS can be grouped according to the following assignments:

• OBs for START-UP program processing
• One OB for cyclic program processing
• OBs for time-controlled program processing
• OBs for (process) interrupt-driven program processing
The S5-100U has additional OBs whose functions are similar to those of integral function blocks
(e.g., PID control algorithm). These OBs are described in chapter 9.
Section 7.3.1 summarizes all of the OBs.
Comparing Programming Possibilities for CPU 100, CPU 102, and CPU 103
Table 7-5. Programming Possibilities
CPU CPU 100 CPU 102 CPU 103
Cyclical Yes Yes Yes
Interrupt-driven No No Yes
(for 8MA02 and higher)
Time-controlled No No Yes
Integral FBs No Yes Yes
Graph 5 No No Yes
Programmable FBs No No Yes
Beginning with section 7.4.2, you learn which special organization blocks each of the CPUs has
available to perform the programming tasks described in Table 7-5. You also learn which pre-
cautions you need to take when you program.
7-18 EWA 4NEB 812 6120-02

7.4.1 Program Processing with CPU 102
You can process the program in the following two modes:

• Normal mode
• Test mode
Program processing is faster in the normal mode, but you can not use the STATUS test function.
Transferring from one mode to the other is called a mode change.
Test Mode:
Scanning the STEP 5 program
Normal Mode:
The control program you have written in STEP 5 is not processed directly. What is processed is a
translated or runtime-optimized form of the program generated by the programmable controller.
Cycle trigger
Cycle trigger
Control Runtime-
Assemble
program optimized
(compile)
in STEP 5 program
Transfer
data
Transfer
data
Test mode Normal mode
Figure 7-9. Program Scanning with CPU 102
EWA 4NEB 812 6120-02 7-19

Special Features of the Normal Mode
Significance of the Memory Submodule

Normal mode is only possible if the memory submodule is plugged in.
This submodule contains only the STEP 5 program.
The CPU RAM contains the STEP 5 program and the compiled program to be processed.
Program Change
You can enter, modify, or erase PBs, OBs and FBs only in the test mode.
You can read out the STEP 5 program with the programmer.
Signal Status Display

You can monitor and control signals states with the “STATUS VAR” and “FORCE VAR” functions.
The “STATUS” function can be used only in the test mode.
Diagnostics
The “BSTACK” diagnostics function cannot be activated.
Fault Analysis
The ISTACK bytes 23 to 27 are not valid. Therefore, you cannot determine the point in a program
where an interruption took place (programmable controller in STOP, e.g., programmed loop with
timeout). However, when compiling the program, errors (e.g., illegal operations and parameters) are
detected and displayed by the STEP address counter in the ISTACK. This counter points to the
error in the STEP 5 program.
7-20 EWA 4NEB 812 6120-02

S5-100U
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Mode Change
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
EWA 4NEB 812 6120-02

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a
module
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa
hold it down
submodule
Test
(manual)
mode
Load program
Reset PLC
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa
4. Turn on the PLC

1. Turn off the PLC
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a
(without PG)
4. Turn on the PLC

2. Turn off the PLC
- Red LED flickers
5. Release COPY key

program is loaded
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2. Plug in memory sub-
1. Remove the battery

3. Press COPY key and
3. Remove the memory

- Red LED lights when
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aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
least 3 s
flickering
submodule
Battery required
CPU’s RAM
(with PG)
1. Turn on the PLC

3. Turn on the PLC
1. Turn off the PLC
(without PG)
- Red LED lights
reset with the PG

2. Plug in EEPROM
Load program
the red LED starts
3. Perform an overall
4. Enter the program

With or without battery
Back up program
2. Switch PLC to STOP
5. Transfer the program

and compiled in the
5. Release it as soon as
- Program is stored in
4. Press COPY key for at
EEPROM submodule
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FIgure 7-10. Mode Change for CPU 102

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aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
resumed.
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
loaded
interrupted
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
submodule
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
(automatic)
1. Reset the PLC
mode
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Load program
3. Plug in memory
at STOP or Power
when program
OFF in the case of

Normal
4. Turn on the PLC
2. Turn off the PLC
mode when RUN is

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battery backup), the
will be the operating

- Red LED flickers
(fault, mode selector
mode that was active

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If program scanning is
prior to the interruption

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aaaaaaaaaaaaaaaa
aaaaaaaa
7-21
Determining the Processing Mode in the ISTACK
Bit
Byte 7 6 ...
1
2
.
.
.
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aaaaaaaaaaaaaa
6 KEIN
AS
7
.
.
.
Figure 7-11. Display of the Processing Mode in the ISTACK
You can use a programmer to check the current processing mode in the ISTACK. The ISTACK
display, byte 6, is possible in RUN and STOP (see section 5.2).
KEIN AS=1 : Test mode

Execution time is 70 ms/1024 binary statements. There are no limitations on the test or operator
functions.
KEIN AS=0: Normal mode

Execution time is 7 ms/1024 binary statements. There are limited test and operator functions.
7-22 EWA 4NEB 812 6120-02

Further Reduction in the Execution Time in Normal Mode

Logic operations executed in one input byte, output byte, or flag byte require only 2 µs per logic
operation. Program your control according to example 2.
Example 1: Example 2:
STL Time/ µs STL Time/ µs
A I 0.0 5 A I 0.0 5
AN I 1.1 6 AN I 0.1 2
ON I 2.3 6 ON I 0.3 2
O I 3.5 6 O I 0.5 2
= Q 4.2 8 = Q 4.2 8
A F 15.1 5 A F 15.1 5
A F 16.3 6 A F 15.3 2
AN F 17.7 6 AN F 15.7 2
= Q 4.5 8 = Q 4.5 8
Execution time 56 µs Execution time 36 µs
Approx. 6 µs/binary operation Approx. 4 µs/binary operation
EWA 4NEB 812 6120-02 7-23

7.4.2 START-UP Program Processing
In the START-UP mode, the operating system of the CPU automatically calls up a start-up OB if the
OB has been programmed.
• OB21 is called up for a manual cold restart.
• OB22 is called up for an automatic cold start after power recovery if the programmable controller
was previously in the RUN mode.
If you have programmed start-up OBs, they are processed before the cyclic program processing
occurs. The start-up OB program is appropriate, for example, for a one-time presetting of certain
system data. If the appropriate start-up OB is not programmed, the programmable controller jumps
directly to the RUN mode. See section 4.1.2.
Features of the start-up blocks (OB21, OB22):

• The red and green LEDs light.
• Timers are processed.
• Scan monitoring is not activated.
• Interrupts are not processed.
Operating mode switch set from STOP Power recovery1

to RUN; Programmer command RUN
Cold
restart
Clear the process image I/O table, Clear the process image I/O table, routine
the non-retentive timers, the non-retentive timers,
counters, and flags. counters, and flags.
Interpret DB12 Interpret DB12
Processing OB21 Processing OB22

START-
UP
Enable the outputs
Read in the PII
RUN
Process OB1
Read out the PIQ

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1 This is the procedure if the programmable controller was in the RUN mode when the power went off,
if the mode switch was still on RUN when the power was restored, and if the battery was inserted. If
the battery was not inserted, you must insert a memory submodule containing the valid blocks.
2 For CPU 103 version 8MA03 and higher
Figure 7-12. Setting the Start-Up Procedure
7-24 EWA 4NEB 812 6120-02

The following two examples show you how you can program a start-up OB.
Example 1: Programming OB22
Example STL Explanation
After power recovery, you AN T 1 A 5 s time value is loaded in

want to be sure that the power L KT 500.0 ACCU 1.
supply voltage for the I/Os has SP T 1 Timer 1 is started.
attained its rated value before F001: A T 1 After 5 s, cyclic program
the cyclic program is pro- JC =F001 processing begins in OB1.
cessed. A time loop is there- BE
fore programmed in OB22.
Example 2: Programming OB21
After the operating mode L KH 0 Value “0” is loaded in

switch causes a cold restart, T FW 0 ACCU 1 and transferred into
flag bytes 0 to 9 are preset T FW 2 flag words 0, 2, 4, 6, and 8.
with “0”. The other flag bytes T FW 4
are retained since they contain T FW 6
important machine functions. T FW 8
BE
EWA 4NEB 812 6120-02 7-25

7.4.3 Cyclic Program Processing
The operating system calls OB1 cyclically. If you want to

have structured programming, you should program only jump
operations (block calls) in OB1. The blocks you call up, PBs, Cycle trigger
FBs, and SBs, should contain completed functional units in
order to provide a clearer overview.
A time monitor is triggered at the beginning of each program
processing cycle (scan cycle trigger). If the scan cycle time
trigger is not reset within the scan monitoring time, the CPU
automatically enters the STOP mode and disables the output Control
modules. program
You can set the monitoring time (see Table 6-6). You could
have a control program that is so complex that it cannot be
processed within 300 ms. With CPU 103 and higher, you can
use OB31 (see section 9.3) to lengthen (retrigger) the scan
monitoring time in the control program. Transfer
Monitoring time is exceeded, for example, if you program data
endless loops or if there is a malfunction in the programmable
controller.
Figure 7-13. Cyclic Program Processing
7-26 EWA 4NEB 812 6120-02

Response Time
Response time tR is defined as the time between a change in the input signal and the subsequent
change in the output signal.
Prerequisites for the following information:

• No interrupts are running.
• The programmer interface is not in use. (The load is very dependent on the function.)
The response time is influenced by the following factors:

• The input module delay (see chapter 14)
• The program processing time (see Appendix A)
• The data cycle times (number of data bits x 25 µs - a bus configuration of 256 data bits results
in a data cycle time of approximately 8 ms)
• The operating system run time (up to 3% of the program cycle)
• The processing of the internal timers T 0 to T15 for CPU 100
T 0 to T31 for CPU 102
T 0 to T127 for CPU 103
Calculating the maximum response time tRm:

• With tG= 2 x program processing time + 3 x data cycle time + 3 x operating system run time
+ delay time of the input modules
• Maximum processing time of the internal timers tTm
tTm = number of processed timers x 32 µs (number of processed timers for CPU 100: 16
number of processed timers for CPU 102: 32
number of processed timers for CPU 103: 128)
tTm = 103 µs for CPU 103 version 8MA03
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tTm
tRm = tG ( 1 + ) + tTm.
10 ms
During the transition from STOP to RUN, there is a one-time increase in the response time to about
200 ms.
Response
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Input
module
delay
1
I 0.0
0
1
Q 1.0 0
Time
Data Program processing Data

cycle A I 0.0 = Q 1.0 cycle
Figure 7-14. Calculating the Response Time
EWA 4NEB 812 6120-02 7-27

7.4.4 Time-Controlled Program Processing, for CPU 103 Version 8MA02

and Higher
Time-controlled program processing can be defined as a (periodic) time signal causing the CPU to
interrupt cyclic program processing to process a specific program. Once this program has been
processed, the CPU returns to the interruption point in the cyclic program and resumes processing.
Prerequisites for time-controlled program processing

Time-controlled program processing is possible only if the following prerequisites have been fulfilled.
• Organization block OB13 must be programmed.
• The programmable controller must be set to Power ON and the RUN mode must be selected.
• Interrupt processing may not be disabled (by the IA - disable interrupt - operation). See
section 8.2.8.
• The OB13 call-up interval is set to > 0.
OB13 is available for time-controlled program processing when using CPU 103 version 8MA02 and
higher. You determine the intervals at which you want the operating system to process OB13. It is
also possible to change the call-up intervals during cyclic program processing. Cyclical program
processing continues if OB13 is not programmed.
• Setting the call-up interval

You can set the call-up interval in DB1 using the TFB: block ID. You can set the times from
10 ms to 655,530 ms (use 10-ms increments). The default for OB13 is 100 ms.
• Interrupt possibilities
OB13 can interrupt the cyclical program after any STEP 5 statement. After the current STEP 5
statement is executed, you can use process interrupts to interrupt time-controlled program
processing. After interrupt processing, time-controlled program processing continues until it is
finished.
OB13 cannot interrupt the operating system, the process interrupts (OB2), or the current time-
controlled program processing (OB13).
• Disabling/enabling the call-up
Use the IA command to disable, and the RA command to enable the OB13 call-up.
A call-up request can be stored during a call-up disable. The default is RA. See section 8.2.8.
• Saving data
If a time-controlled OB uses scratchpad flags that are also used in the cyclic control program,
then these scratchpad flags must be saved in a data block during the processing of the time-
controlled OB.
Note
When processing OB13, you may not exceed the block nesting depth of 16 levels.
When processing with CPU 103 (6ES5 103-8MA03), you may not exceed the block
nesting depth of 32 levels.
7-28 EWA 4NEB 812 6120-02

• Reading out the interrupt PII

When OB13 is called, the signals of the input modules are read into the interrupt PII. The
interrupt PII can be scanned in OB13 by means of the L PB 0 to 127 or L PW 0 to 126 load
operations (load byte x or word x of the interrupt PII in ACCU 1). There is an interrupt input data
cycle prior to time-controlled program processing. The interrupt data cycle time lengthens the
response time of the cyclical program processing.
If other operands are entered, the CPU goes in the STOP mode (see section 5.2.1). This error
is indicated in ISTACK by the “NNN” error message.
• Writing to the interrupt PIQ
Data to the external I/Os can be written to the interrupt PIQ by means of transfer operations
T PB 0 to 127 or T PW 0 to 126. The “normal” PIQ is written to simultaneously. After OB13
has finished, the data that has been transferred to the interrupt PIQ is output to the peripheral
I/Os in an interrupt output data cycle (before “normal” program processing). The interrupt data
cycle time lengthens the response time of the cyclical program processing.
Note
The interrupt output data cycle is executed only if the interrupt PIQ has been written to.
7.4.5 Interrupt-Driven Program Processing, for CPU 103 Version 8MA02

and Higher
For CPU 103 version 8MA02 and higher, interrupt-driven program processing is initiated when a
signal from the process causes the CPU to interrupt the cyclic or time-controlled program
processing and execute a specific program. When this program has been scanned, the CPU returns
to the point of interruption in the cyclic or time-controlled program and resumes scanning at that
point. Chapter 10 contains detailed information about interrupt processing.
EWA 4NEB 812 6120-02 7-29

7.5 Processing Blocks

Earlier sections in this chapter described how to use blocks. Chapter 8 introduces all of the
operations required to work with blocks. You can change any block that has been programmed.
The following sections will deal only briefly with the different ways you can change blocks. Refer to
the operator‘s guide for your programmer for more detailed information on changing blocks.
7.5.1 Changing Programs

You can use the following programmer functions to make program changes with any block type.
• INPUT
• OUTPUT
• STATUS (see section 4.5)
These three programmer functions make it possible for you to make the following types of changes:
• Delete, insert, or overwrite statements.
• Insert or delete segments.
7.5.2 Changing Blocks

Program changes refer to changing the contents of a block. You can also delete or overwrite a
complete block. When you delete a block, it is not deleted from the program memory but simply
becomes invalid. You cannot enter new information in the memory location of an invalid block. This
may cause new blocks not to be accepted. If a new block is not accepted, then the PG transmits
the “no space available” error message. You can make more space by compressing the
programmable controller memory.
7.5.3 Compressing the Program Memory

Figure 7-15 illustrates what takes place in the program memory during a COMPRESS operation.
Internally, one block is shifted per cycle.
Program memory Program memory

RAM RAM
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Valid
blocks
Invalid
Compress Input
possible
Input not
possible
PB
PB Available
memory space
Figure 7-15. Compressing the Program Memory
7-30 EWA 4NEB 812 6120-02

You can use the COMPRESS programmer function to clean up internal program memory.
If there is a power failure during the compress operation when a block is being shifted and block
shifting can not be completed, the CPU remains in the STOP mode. The “NINEU” error message
appears. Both the“BSTSCH” and the “SCHTAE” bits are set in the ISTACK.
Remedy: Overall reset.
7.6 Number Representation
With STEP 5 you can work with numbers in the following five representations:
• Decimal numbers from -32768 to +32767 (KF)
• Hexadecimal numbers from 0000 to FFFF (KH)
• BCD-coded numbers (4 tetrads) from 0000 to 9999
• Bit patterns (KM)
• Constant byte (two-byte representation) from 0 to 255 for each byte (KY)
Number Formats
The programmable controller is designed to process binary signal states (only “0” and “1”).
Therefore the programmable controller represents all numbers internally as 16-bit binary numbers or
as bit patterns.
Four bits can be combined into a tetrad (BCD) to shorten the binary code representation. The value
of these tetrads can be displayed in hexadecimal representation.
Example: 16-bit binary coded number and shortened hexadecimal representation
Word no. n
Byte no. n (high byte) n+ 1 (low byte)
Bit no. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Binary code representation 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 1

Meaning 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
Hexadecimal representation 1 F 6 3
Figure 7-16. Bit Assignment of a 16-Bit Fixed-Point Binary Number
EWA 4NEB 812 6120-02 7-31

You can work with binary-coded decimals to program timers and counters in the decimal system.
BCD tetrads are defined in the range of 0 to 9.
Example: 12-bit timer or counter value in BCD and decimal formats
Word No. n
Byte No. n (high byte) n+ 1 (low byte)
Bit No. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BCD No. 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1
Meaning 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
Decimal format 0 9 3 1
Figure 7-17. BCD and Decimal Formats
Table 7-6. Comparison of Number Formats
Binary Decimal BCD Hexadecimal
0000 0 0000 0000 0

0001 1 0000 0001 1
0010 2 0000 0010 2
0011 3 0000 0011 3
0100 4 0000 0100 4
0101 5 0000 0101 5
0110 6 0000 0110 6
0111 7 0000 0111 7
1000 8 0000 1000 8
1001 9 0000 1001 9
1010 10 0001 0000 A
1011 11 0001 0001 B
1100 12 0001 0010 C
1101 13 0001 0011 D
1110 14 0001 0100 E
1111 15 0001 0101 F
7-32 EWA 4NEB 812 6120-02

You can use the “LC” operation to convert a binary number to a BCD number for timers and
counters.
Example: Comparing a count in counter 1 with decimal number 499
The comparison value must be stored in the accunulator by means of a load

operation. Use the “LKF + 499” statement so that you do not have to convert the
value 499 into other numerical systems (binary or hexadecimal) for the input. The
number 1F3H is then stored in the accumulator.
The current count must also be loaded into the accumulator.
Incorrect Method: Correct Method:

If you use the “LCC1” The formats are identical if the
statement, the current count will “LC1” statement is input.
be loaded in BCD. The “!=F”
comparison operation results in
a “not equal to” condition since
the comparison uses different
formats.
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
High Byte Low Byte
0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1
L KF+499 L KF+499
0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1
LC C 1 L C1
EWA 4NEB 812 6120-02 7-33

8 STEP 5 Operations
8.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

8.1.1 Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8.1.2 Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8.1.3 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8.1.4 Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8.1.5 Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8.1.6 Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8.1.7 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8.1.8 Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8.1.9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
8.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8.2.1 Load Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . 8 - 40
8.2.2 Enable Operation, for CPU 103 and Higher . . . . . . . . . . . . . . . . . 8 - 41
8.2.3 Bit Test Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . 8 - 42
8.2.4 Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8.2.5 Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8.2.6 Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8.2.7 Decrement/Increment, for CPU 103 and Higher . . . . . . . . . . . . . . 8 - 52
8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher . 8 - 53
8.2.9 “DO” Operation, for CPU 103 and Higher .................. 8 - 54
8.2.10 Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8.2.11 Substitution Operations, for CPU 103 and Higher . . . . . . . . . . . . . 8 - 58
8.3 System Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . 8 - 64

8.3.1 Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.2 Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8.3.3 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8.3.4 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 68
8.4 Condition Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 69
8.5 Sample Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71

8.5.1 Momentary-Contact Relay/Edge Evaluation . . . . . . . . . . . . . . . . . 8 - 71
8.5.2 Binary Scaler/Binary Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 71
8.5.3 Clock/Clock-Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 73
EWA 4NEB 812 6120-02

Figures
8-1 Accumulator Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10

8-2 Execution of the Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
8-3 Transferring a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
8-4 Output of the Current Time (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18
8-5 Outputting the Current Counter Status (Example) . . . . . . . . . . . . . . . . . . 8 - 27
8-6 Executing a “DO” Operation ................................ 8 - 55
Tables
Basic Operations
8-1 Overview of Boolean Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2
8-2 Overview of the Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8-3 Overview of Load and Transfer Operations . . . . . . . . . . . . . . . . . . . . . . 8 - 11
8-4 Overview of Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8-5 Overview of Counter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
8-6 Overview of Comparison Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
8-7 Overview of Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 31
8-8 Overview of Block Call Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
8-9 Other Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 38
Supplementary Operations
8-10 Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 40
8-11 Enable Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 41
8-12 Overview of Bit Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 42
8-13 Effect of “TB” and “TBN” on the RLO ......................... 8 - 42
8-14 Overview of Digital Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 44
8-15 Overview of Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 48
8-16 Overview of Conversion Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 50
8-17 Decrement/Increment Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 52
8-18 Disable/Enable Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 53
8-19 Overview of the “DO” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 54
8-20 Operations That Can Be Combined with the “DO” Statement ......... 8 - 54
8-21 Overview of Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 56
8-22 Overview of Binary Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 58
8-23 Overview of Set/Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 59
8-25 Overview of Timer and Counter Operations . . . . . . . . . . . . . . . . . . . . . . 8 - 61
8-26 “DO” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 63
System Operations
8-27 Overview of Set Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 64
8-29 Overview of the “ADD” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 67
8-30 The “TAK” and “STS” Operations ............................ 8 - 68
8-31 Condition Code Settings for Comparison Operations . . . . . . . . . . . . . . . . 8 - 69
8-32 Condition Code Settings for Fixed-Point Arithmetic Operations . . . . . . . . . 8 - 69
8-33 Condition Code Settings for Digital Logic Operations . . . . . . . . . . . . . . . 8 - 70
8-34 Condition Code Settings for Shift Operations . . . . . . . . . . . . . . . . . . . . . 8 - 70
8-35 Condition Code Settings for Conversion Operations . . . . . . . . . . . . . . . . 8 - 70
EWA 4NEB 812 6120-02

S5-100U STEP 5 Operations
8 STEP 5 Operations
The STEP 5 programming language has the following three operation types:
• Basic Operations include functions that can be executed in organization, program, sequence,
and function blocks. Except for the addition (+F), subtraction (-F), and organizational ope-
rations, the basic operations can be input and output in the statement list (STL), control system
flowchart (CSF), or ladder diagram (LAD) methods of representation.
• Supplementary Operations include complex functions such as substitution statements, test
functions, and shift and conversion operations. They can be input and output in STL form only.
• System Operations access the operating system directly. Only an experienced programmer
should use them. System operations can be input and output in STL form only.
8.1 Basic Operations

Sections 8.1.1 through 8.1.9 use examples to describe the basic operations.
EWA 4NEB 812 6120-02 8-1

STEP 5 Operations S5-100U
8.1.1 Boolean Logic Operations
Table 8-1 provides an overview of Boolean logic operations. Examples follow the table.
Table 8-1. Overview of Boolean Logic Operations

Operation Operand Meaning
O Combine AND operations through logic OR

Combine the result of the next AND logic operation (RLO) with the previous
RLO through logic OR.
A( Combine expression enclosed in parentheses through logic AND

Combine the RLO of the expression enclosed in parentheses with the
previous RLO through logic AND.
O( Combine expression enclosed in parentheses through logic OR

Combine the RLO of the expression enclosed in parentheses with the
previous RLO through logic OR.
) Close parenthesis
Conclude the expression enclosed in parentheses.
A Scan operand for “1” and combine with RLO through logic AND
The result is “1” when the operand in question carries signal state “1”.
Otherwise the scan results in “0”. Combine this result with the RLO in the
processor through logic AND1.
O Scan operand for “1” and combine with RLO through logic OR
The result is “1” when the operand in question has signal state “1”.
processor through logic OR1.
AN Scan operand for “0” and combine with RLO through logic AND
processor through logic AND1.
ON Scan operand for “0” and combine with RLO through logic OR
processor through logic OR1.
ID Parameter CPU 100 CPU 102 CPU 103

I 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
Q 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
F 0.0 to 127.7 0.0 to 127.7 0.0 to 255.7
T 0 to 15 0 to 31 0 to 127
C 0 to 15 0 to 31 0 to 127
1 If the scan follows an RLO limiting operation directly (first scan), the scan result is reloaded as a new
RLO.
8-2 EWA 4NEB 812 6120-02

AND Operation
The AND operation scans to see if various conditions are satisfied simultaneously.
Example Circuit Diagram
Output Q 1.0 is “1” when all three inputs are “1”. I 0. 0

The output is “0” if at least one input is “0”.
The number of scans and the sequence of the logic I 0.1
statements are at random.
I 0.2
Q 1.0
STL CSF LAD

A I 0.0 I 0.0 I 0.1

A I 0.1 &
I 0.1
A I 0.2
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
I 0.2 Q 1.0
= Q 1.0 I 0.0 I 0.2 Q 1.0
OR Operation
The OR operation scans to see if one of two (or more) conditions has been satisfied.
Output Q 1.0 is “1” when at least one of the inputs is “1”.

Output Q 1.0 is “0” when all inputs are “0” simultaneously. I 0.0 I 0.1 I 0.2
The number of scans and the sequence of their
programming are optional.
Q 1.0
STL CSF LAD

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
I 0.0 Q 1.0
O I 0.0
O I 0.1 I 0.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
>=1 I 0.1
O I 0.2 I 0.1
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
= Q 1.0
I 0.2 Q 1.0
I 0.2
EWA 4NEB 812 6120-02 8-3

8-4
=
A
A
O
A
A
Q
I
I
I
I
STL
been satisfied.
1.0
0.3
0.2
0 1
0.0
STEP 5 Operations
has been satisfied.

aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa
AND before OR Operation

I 0.3
I 0.2
I 0.1
I 0. 0
Example
&
&
CSF
>=1
Q 1.0
Output Q 1.0 is “1” when at least one AND condition has
Output Q 1.0 is “0” when neither of the two AND conditions

aaaaaaaaaa aaaaaaaaaa
I 0.2
I 0.0
I 0.1
I 0.0
aaaaa aaaaa
aaaaaaaa aaaaaaaaaa
aaaaaaaa aaaaaaaaaa
I 0.3
I 0.1
aaaaaaaa aaaaaaaaaa
LAD
Q 1.0
aaaaaaaa aaaaaaaaaa
aaaa aaaaa
I 0.3
I 0.2
Circuit Diagram
aaaaaaaa
aaaaaaaa
aaaaaaaa
Q 1.0
aaaaaaaa
aaaa
EWA 4NEB 812 6120-02

S5-100U
=
)
O
O
A
O
O
A(
S5-100U
Q
I
I
I
I
STL
been satisfied.
1.0
0.3
0.2
0.1
0.0
EWA 4NEB 812 6120-02

has been satisfied:
• Input I 0.0 is “1”.
aaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa
I 0.3
I 0.2
I 0.1
I 0.0
OR before AND Operation
>=1
Example
&
CSF
• Input I 0.1 and either input I 0.2 or I 0.3 is “1”.
>=1
Output Q 1.0 is “1” when one of the following conditions
aaaaaaaaaa
aaaaaaaaaa
Q 1.0
aaaaaaaaaa
Output Q 1.0 is “0” when none of the AND conditions has

aaaaaaaaaa
aaaaaaaaaa
I 0.0
aaaaaaaaaa aaaaaaaa aaaaaaaa
I 0.3
I 0.2
I 0.0
aaaaaaaa
I 0.2
aaaaaaaa
I 0.1
aaaaaaaa
LAD
aaaaaaaa
Q 1.0
aaaa
I 0.3
Circuit Diagram
I 0.1
aaaaaaaa
aaaaaaaa
Q 1.0
aaaaaaaa
aaaaaaaa
aaaa
8-5
STEP 5 Operations
OR before AND Operation
Output Q 1.0 is “1” when both OR conditions have been

satisfied. I 0.0 I 0.1
Output Q 1.0 is “0” when at least one OR condition has not
been satisfied.
I 0.2 I 0.3
Q 1.0
STL CSF LAD
A( I 0.0 >=1
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
O I 0.0 Q 1.0
I 0.0 I 0.2
O I 0.1 &
I 0.1
)
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
A( I 0.1 I 0.3
O I 0.2 I 0.2 >=1
O I 0.3
)
I 0.3 Q 1.0
= Q 1.0
8-6 EWA 4NEB 812 6120-02

8.1.2 Set/Reset Operations
Set/reset operations store the result of logic operation (RLO) formed in the processor. The stored
RLO represents the signal state of the addressed operand. Storage can be dynamic (assignment)
or static (set and reset). Table 8-2 provides an overview of the set/reset operations. Examples
follow the table.
Table 8-2. Overview of the Set/Reset Operations

S Set
The first time the program is scanned with RLO = “1”, signal state
“1” is assigned to the addressed operand. An RLO change does
not affect this status.
R Reset
The first time the program is scanned with RLO = “1”, signal state
“0” is assigned to the addressed operand. An RLO change does
not affect this status.
= Assign
Every time the program is scanned, the current RLO is assigned to
the addressed operand.
I 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
Q 0.0 to 127.7 0.0 to 127.7 0.0 to 127.7
F 0.0 to 127.7 0.0 to 127.7 0.0 to 255.7
EWA 4NEB 812 6120-02 8-7

Flip-Flop for a Latching Signal Output (reset dominant)

aaaaaaaaaaaaaa
A “1” at input I 0.1 sets flip-flop Q 1.0 (signal state “1”). If

the signal state at input I 0.1 changes to “0”, the state of
output Q 1.0 is maintained, i.e., the signal is latched. I 0.0 I 0.1
A “1” at input I 0.0 resets the flip-flop (signal state “0”).
When the “SET” signal (input I 0.1) and the “RESET”
signal (input I 0.0) are applied at the same time, the
scanning operation that was programmed last (in this case
Q 1.0
A I 0.0) is in effect during processing of the rest of the
program.
In this example, resetting output Q 1.0 has priority.
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aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
STL CSF LAD
A I 0.1
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
S Q 1.0 I 0.1 Q 1.0

A I 0.0 Q 1.0 S
R Q 1.0
NOP 0 * I 0.1 S
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
I 0.0 R Q I 0.0
R Q
* NOP 0 “NOP 0” is necessary if the program is to be represented in LAD or CSF form on programmers
with a screen. During programming in LAD and CSF, such “NOP 0” operations are allotted
automatically.
8-8 EWA 4NEB 812 6120-02

RS Flip-Flop with Flags (set dominant)

A “1” at input I 0.0 sets flip-flop F 1.7 (signal state “1”).
If the signal state at input I 0.0 changes to “0”, the state of
flag F 1.7 is maintained, i.e., the signal is latched.
A “1” at input 0.1 resets the flip-flop (signal state “0”). If I 0.0 I 0.1
the signal state at input I 0.1 changes to “0”, flag F 1.7
retains signal state “0”.
If both inputs have a “1” signal state, the flip-flop is set (set
dominant).
The signal state of the flag is scanned and transferred to F 1.7
output Q 1.0.
STL CSF LAD

aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
A I 0.1 F 1.7 I 0.1 F 1.7

R F 1.7 R
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
I 0.1 R Q 1.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
A I 0.0
I 0.0
S F 1.7
S Q
A F 1.7 I 0.0 S Q Q 1.0
= Q 1.0
EWA 4NEB 812 6120-02 8-9

8.1.3 Load and Transfer Operations
Use load and transfer operations to do the following tasks.

• Exchange information between various operand areas
• Prepare time and count values for further processing
• Load constants for program processing
Information flows indirectly via accumulators (ACCU 1 and ACCU 2). The accumulators are special
registers in the programmable controller that serve as temporary storage. They are each 16 bits
long. The accumulators are structured as shown in Figure 8-1.
ACCU 2 ACCU 1
15 8 7 0 15 8 7 0
Figure 8-1. Accumulator Structure
You can load and transfer permissible operands in bytes or words. For exchange in bytes, infor-
mation is stored right-justified, i.e., in the low byte.
The remaining bits are set to zero.
You can use various operations to process the information in the two accumulators.
Load and transfer operations are executed independently of condition codes. Execution of these
operations does not affect the condition codes.
You can program load and transfer operations graphically only in combination with timer or counter
operations; otherwise you can represent them only in STL form.
Table 8-3 provides an overview of the load and transfer operations. Examples follow the table.
8-10 EWA 4NEB 812 6120-02

Table 8-3. Overview of Load and Transfer Operations

Opera-
Operand Meaning
tion
L Load
The operand contents are copied into ACCU 1 regardless of the RLO.
The RLO is not affected.
T Transfer
The contents of ACCU 1 are assigned to an operand regardless of the
RLO.
ID Parameter
CPU 100 CPU 102 CPU 103
IB 0 to 127 0 to 127 0 to 127
IW 0 to 126 0 to 126 0 to 126
QB 0 to 127 0 to 127 0 to 127
QW 0 to 126 0 to 126 0 to 126
FY 0 to 127 0 to 127 0 to 255
FW 0 to 126 0 to 126 0 to 254
DR 0 to 255 0 to 255 0 to 255
DL 0 to 255 0 to 255 0 to 255
DW 0 to 255 0 to 255 0 to 255
T1 0 to 15 0 to 31 0 to 127
C1 0 to 15 0 to 31 0 to 127
PB/PY* ----- ----- 0 to 127
PW ----- ----- 0 to 126
KM1 random bit random bit random bit
pattern (16 bits) pattern (16 bits) pattern (16 bits)
KH1 0 to FFFF 0 to FFFF 0 to FFFF
KF1 -32768 to+32767 -32768 to +32767 -32768 to +32767
KY1 0 to 255 0 to 255 0 to 255
per byte per byte per byte
KB1 0 to 255 0 to 255 0 to 255
KS1 any 2 any 2 any 2
alphanumeric alphanumeric alphanumeric
characters characters characters
KT1 0.0 to 999.3 0.0 to 999.3 0.0 to 999.3
KC1 0 to 999 0 to 999 0 to 999
LD Load in BCD
Binary times and counts are loaded into ACCU 1 in BCD code regardless
of the RLO.
T 0 to 15 0 to 31 0 to 127
C 0 to 15 0 to 31 0 to 127
1 These operands cannot be used for transfer.
* Programmer dependent
EWA 4NEB 812 6120-02 8-11

Load Operation
During loading, information is copied from a memory area, e.g., from the PII, into ACCU 1.
The previous contents of ACCU 1 are shifted to ACCU 2.
The original contents of ACCU 2 are lost.
Example: Two consecutive bytes (IB7 and IB8) are loaded from the PII into the accumulator.
Loading does not change the PII (see Figure 8-2).
Lost Information
information ACCU 2 ACCU 1 from the PII
Byte d Byte c Byte b Byte a
L IB7
Byte d Byte c Byte b Byte a 0 IB7 IB7
L IB8
Byte b Byte a 0 IB7 0 IB8 IB
Figure 8-2. Execution of the Load Operation
Transfer Operation
During transfer, information from ACCU 1 is copied into the addressed memory area, e.g., into the
PIQ.
This transfer does not affect the contents of ACCU 1.
Example: Figure 8-3 shows how byte a, the low byte in ACCU 1, is transferred to QB5.
ACCU 2 ACCU 1 Information Lost

in the PIQ information
Byte d Byte c Byte b Byte a
T QB5
Previous value
Byte d Byte c Byte b Byte a Byte a of QB5
Figure 8-3. Transferring a Byte
8-12 EWA 4NEB 812 6120-02

Loading and Transferring a Time (See also Timer and Counter Operations)
Example Representation
During graphic input, QW62 is assigned to output BI of
a timer. The programmer automatically stores the
corresponding load and transfer operation in the
control program. Thus the contents of the memory lo-
cation addressed with T 10 are loaded into ACCU 1. T 10 Load
Afterwards, the contents of the accumulator are
transferred to the process image addressed with
QW62. In this example, you can see timer T 10 at
QW62 in binary code.
Outputs BI and DE are digital outputs. The time at Transfer
QW62
output BI is in binary code. The time at output DE is
in BCD code with time base.
STL CSF LAD
A I 0.0 I 0.0 T 10
L IW 22 T 10 1
SP T 10 I 0.0 1
NOP 0
IW22 TV IW22
L T 10 BI TV
QW62 BI QW62
T QW 62 DE DE
R Q R Q
NOP 0
NOP 0
EWA 4NEB 812 6120-02 8-13

Loading and Transferring a Time (Coded)
The contents of the memory location addressed with
T 10 are loaded into the accumulator in BCD code.
Then a transfer operation transfers the accumulator
T 10
contents to the process image memory location Load
addressed by QW50. A coding operation is possible

only indirectly for the graphic representation forms
LAD and CSF by assigning an address to output DE of
a timer or counter location. However, this operation Transfer
can be entered with a separate statement with STL. QW50
STL CSF LAD
A I 0.0 T 10
T 10 I0.0
L IW 22
1
SP T 10 I 0.0 1
NOP 0
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
IW22 TV
NOP 0 BI IW22 TV
LD T 10 DE QW50 BI
R Q DE QW50
T QW 50 R Q
NOP 0
8-14 EWA 4NEB 812 6120-02

8.1.4 Timer Operations
The program uses timer operations to implement and monitor chronological sequences. Table 8-4
provides an overview of timer operations. Examples follow the table.
Table 8-4. Overview of Timer Operations

SP Pulse Timer
The timer is started on the leading edge of the RLO.
When the RLO is “0”, the timer is set to “0”.
Scans result in signal state “1” as long as the timer is running.
SE Extended Pulse Timer
When the RLO is “0”, the timer is not affected.
Scans result in signal state “1” as long as the timer is running.
SD On-Delay Timer
When the RLO is “0”, the timer is set to “0”.
Scans result in signal state “1” when the timer has run out and the
RLO is still pending at the input.
SS Stored On-Delay Timer
Scans result in signal state “1” when the timer has run out.
The signal state becomes “0” when the timer is reset with the “R”
operation.
SF Off-Delay Timer
The timer is started on the trailing edge of the RLO.
When the RLO is “1”, the timer is set to its initial value.
Scans result in signal state ”1” as long as the RLO at the input is
“1” or the timer is still running.
R Reset Timer
The timer is reset to its initial value as long as the RLO is “1”.
Scans result in signal state “0” as long as the timer is reset or has
not been started yet.
T 0 to 15 0 to 31 0 to 127
EWA 4NEB 812 6120-02 8-15

Loading a Time
Timer operations call internal timers.
When a timer operation is started, the word in ACCU 1 is used as a time value. You must therefore
first specify time values in the accumulator.
You can load a timer with any of the following data types:
KT constant time value

or
DW data word
IW input word These data types must be
QW output word in BCD code.
FW flag word
Loading a Constant Time Value

The following example shows how you can load a time value of 40 s.
Operation
Operand
L KT 40.2
Coded time base (0 to 3)
Time (0 to 999)
Key for Time Base

Base 0 1 2 3
Factor 0.01 s 0.1 s 1s 10 s
8-16 EWA 4NEB 812 6120-02

Example: KT 40.2 corresponds to 40 x 1 s.
Tolerance:
The time tolerance is equivalent to the time base.
Examples Operand Time Interval
Possible KT 400.1 400 x 0.1 s - 0.1 s 39.9 s to 40 s

settings for
KT 40.2 40 x 1s - 1s 39 s to 40 s
the time
40 s KT 4.3 4 x 10 s - 10 s 30 s to 40 s
Note
Always use the smallest time base possible.
Loading a Time as an Input, Output, Flag, or Data Word

Load Statement: L DW 2
The time 638 s is stored in data word DW2 in BCD code.

Bits 14 and 15 are insignificant for the time value.
15 11 0 Bit
1 0 0 1 1 0 0 0 1 1 1 0 0 0 DW2
Three-digit time value

(in BCD code)
Time base
Key for Time Base:
Base 00 01 10 11
Factor 0.01 s 0.1 s 1s 10 s
You can also use the control program to write to data word DW2.
Example: Store the value 270 x 100 ms in data word DW2 of data block DB3.
C DB 3
L KT 270.1
T DW2
EWA 4NEB 812 6120-02 8-17

Output of the Current Time 1
You can use a load operation to put the current time into ACCU 1 and process it further from there
(see Figure 8-4).
Use the “Load in BCD” operation for digital display output.
Current time in T1
L T1 LD T1
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
ACCU 1
Binary time value Time Three-digit time value

base in BCD code
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
indicates bit positions occupied by “0”.
Figure 8-4. Output of the Current Time (Example)
1 The current time is the time value in the addressed timer.
8-18 EWA 4NEB 812 6120-02

Starting a timer
In the programmable controller, timers run asynchronously to program scanning. The time that has
been set can run out during a program scanning cycle. It is evaluated by the next time scan. In the
worst case, an entire program scanning cycle can go by before this evaluation. Consequently,
timers should not activate themselves.
Example:
Schematic Representation Explanation
Program Signal from The schematic shows the “nth + 1”

timer 17 processing cycle since timer T 17* was
0 1 started. Although the timer ran out
shortly after the statement “= Q 1.0”,
output Q 1.0 remains set. The change is
not considered until the next program
scanning cycle.
L KT 100.0
SP T 17
1s - n · tp
A T 17
= Q 1.0
n: number of program scanning cycles

tp: program scan time * KT 100.0 is equal to 1 s.
The following rules apply to timers:

• Except for “Reset timer”, all timer operations are started only when there is an edge change.
The RLO alternates between “0” and “1”.
• After being started, the loaded time is decremented in units corresponding to the time base until
it reaches zero.
• If there is an edge change while the timer is running, the timer is reset to its initial value and
restarted.
• The signal state of a timer can be scanned with Boolean logic operations.
EWA 4NEB 812 6120-02 8-19

Pulse
Example:
Output Q 1.0 is set when the signal state at input I 0.0 changes from “0” to “1”.
However, the output should not remain set longer than 5 s.
Timing Diagram Circuit Diagram
Signal states
I 0.0
1
I 0.0
0
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
T1
1
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
0 Q 1.0
Q 1.0
Time in s
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
5 T 1: Time relay with transitional

NO contact
STL CSF LAD
A I 0.0
T1 T1
L KT 500.0 I 0.0
SP T 1 I 0.0 1 1
NOP 0 KT 500.0 TV BI KT 500.0 TV BI
NOP 0 DE DE
NOP 0
R Q Q 1.0 R Q
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
A T 1
Q 1.0
= Q 1.0
Note
The time tolerance is equivalent to the time base. Always use the smallest time base
possible.
8-20 EWA 4NEB 812 6120-02

Extended pulse
Example:
Output Q 1.0 is set for a specific time when the signal at input I 0.0 changes to “1”. The time is
indicated in IW16.
Signal states
1
I 0.0 I 0.0
0
1
Q 1.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
0 T2
Time
Q 1.0
t t
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
T 2: Time relay with pulse shaper
STL CSF LAD

aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
A I 0.0
T2 T2
L IW 16 I 0.0
SE T 2 I 0.0 1 V 1 V
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
NOP 0 TV BI
IW16 IW16 TV BI
NOP 0
DE DE
NOP 0
A T 2 R Q Q 1.0 R Q
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
= Q 1.0 Q 1.0
EWA 4NEB 812 6120-02 8-21

On-Delay
Example:
Output Q 1.0 is set 9 s after input I 0.0 and remains set as long as the input carries signal “1”.
Signal states
I 0.0
1
0 I 0.0
1
Q 1.0
0
T3
Time in s
9 9
Q 1.0
STL CSF LAD
A I 0.0
T3 T3
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
L KT 900.0 I 0.0
SD T 3 I 0.0 T 0 T 0
NOP 0 KT 900.0 TV BI KT 900.0 TV BI
NOP 0
DE DE
NOP 0
A T 3 R Q Q 1.0 R Q
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
= Q 1.0 Q 1.0
8-22 EWA 4NEB 812 6120-02

Stored On-Delay and Reset
Example:
Output Q 1.0 is set 5 s after I 0.0.

Further changes in the signal state at input I 0.0 do not affect the output.
Input I 0.1 resets timer T 4 to its initial value and sets output Q 1.0 to zero.

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
Signal states I 0.1
1
I 0.0
0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
1 H1 I 0.0 H1
I 0.1
0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
1 Q 1.0 T4
0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
Time Q 1.0 H1
5 5
in s
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
H 1: Auxiliary relay
STL CSF LAD
A I 0.0 T4
T4
L KT 500.0 I 0.0
SS T 4 I 0.0 T s T s
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
A I 0.1 KT 500.0 TV BI KT 500.0 TV BI

R T 4
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
DE DE
NOP 0 I 0.1
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
NOP 0 I 0.1 R Q Q 1.0 R Q

A T 4 Q 1.0
= Q 1.0
Note
The time tolerance is equivalent to the time base.
EWA 4NEB 812 6120-02 8-23

Off-Delay
Example:
When input I 0.0 is reset, output Q 1.0 is set to zero after a certain delay (t). The value in FW14
specifies the delay time.
Signal states
I 0.0
1
0 I 0.0
1
0 Q 1.0
Time in s T5
t t
Q 1.0
STL CSF LAD
A I 0.0 T5
T5
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
L FW 14 I 0.0
SF T 5 I 0.0 0 T 0 T
NOP 0 FW14 TV BI FW14 TV BI
NOP 0
DE DE
NOP 0
A T 5 R Q Q 1.0 R Q
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
= Q 1.0 Q 1.0
8-24 EWA 4NEB 812 6120-02

8.1.5 Counter Operations
The programmable controller uses counter operations to handle counting jobs. Counters can count
up and down. The counting range is from 0 to 999 (three decades). Table 8-5 provides an
overview of the counter operations. Examples follow the table.
Table 8-5. Overview of Counter Operations

S Set Counter
The counter is set on the leading edge of the RLO.
R Reset Counter
The counter is set to zero as long as the RLO is “1”.
CU Count Up
The count is incremented by 1 on the leading edge of the RLO.
When the RLO is “0”, the count is not affected.
CD Count Down
The count is decremented by 1 on the leading edge of the RLO.
When the RLO is “0”, the count is not affected.

C 0 to 15 0 to 31 0 to 127
Loading a Count
Counter operations call internal counters.
When a counter is set, the word in ACCU 1 is used as a count. You must therefore first store
counts in the accumulator.
You can load a count with any of the following data types:
KC constant count
or
DW data word
IW input word The data for these words must
QW output word be in BCD code.
FW flag word
EWA 4NEB 812 6120-02 8-25

Loading a Constant Count

The following example shows how the count 38 is loaded.
Operation
Operand
L KC 38
Count (0 to 999)
Loading a Count as an Input, Output, Flag, or Data Word

Load statement: L DW 3
The count 410 is stored in data word DW3 in BCD code.

Bits 12 to 15 are insignificant for the count.
15 11 0 Bit
0 1 0 0 0 0 0 1 0 0 0 0 DW3
Three-digit count
(in BCD code)
Scanning the Counter

Use Boolean logic operations to scan the counter status (e.g., A Cx). As long as the count is not
zero, the scan result is signal state “1”.
8-26 EWA 4NEB 812 6120-02

Outputting the Current Counter Status

You can use a load operation to put the current counter status into ACCU 1 and process it further
from there. The “Load in BCD” operation outputs a digital display (see Figure 8-5).
Current Counter Status in C2
L C2 LD C2
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
ACCU 1
Binary count Three-digit count

in BCD code
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
indicates bit positions occupied by “0”.

Figure 8-5. Outputting the Current Counter Status (Example)
EWA 4NEB 812 6120-02 8-27

Setting a Counter “S” and Counting Down “CD”
Example:
When input I 0.1 is switched on (set), counter 1 is set to count 7. Output Q 1.0 is now “1”.
Every time input I 0.0 is switched on (count down), the count is decremented by 1.
The output is set to “0” when the count is “0”.
I 0.1
aaaaaaaaaaaa
aaaaaaaaaaaa
1
0 I 0.0
KC 7
aaaaaaaaaaaa
aaaaaaaaaaaa
1 I 0.1 R S CI
0
aaaaaa
aaaaaa
C1
7
I 0.0
aaaaaa
aaaaaa
0 IIII
Binary
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
CQ
1 Q 1.0 0 16 bits
0
Time
Q 1.0 Count
S C1 S C1
STL CSF LAD

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
A I 0.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
C1 I 0.0 C1
CD C 1
I 0.0 CD CD
NOP 0
A I 0.1 CU CU
I 0.1
L KC 7 S
I 0.1 S
S C 1 KC 7
KC 7 CV BI CV BI
NOP 0 DE
DE
NOP 0
R Q Q 1.0 R Q
NOP 0
A C 1 Q 1.0
= Q 1.0
8-28 EWA 4NEB 812 6120-02

Resetting a Counter “R” and Counting Up “CU”
Example:
When input I 0.0 is switched on, the count in counter 1 is incremented by 1. As long as a second
input (I 0.1) is “1”, the count is reset to “0”.
The A C 1 operation results in signal state “1” at output Q 1.0 as long as the count is not “0”.

aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaa aaaaaaaaaaaaaaaaaaaaaaa
1 I 0.0 I 0.1
0
1
0 I 0.1 R S CI
2
C 1
0 I 0.0 IIII
1 Q 1.0
CQ
Binary
0 0 16 bits
Time
R C1 Q 1.0
STL CSF LAD
A I 0.0 C1 C1
CU C 1 I 0.0
I 0.0 CU CU
NOP 0
NOP 0 CD CD
NOP 0 S S
A I 0.1
CV BI CV BI
R C 1 DE DE
NOP 0 I 0.1
I 0.1 R Q Q 1.0 R Q
NOP 0
A C 1 Q 1.0
= Q 1.0
EWA 4NEB 812 6120-02 8-29

8.1.6 Comparison Operations
Comparison operations compare the contents of the two accumulators. The comparison does not
change the accumulators' contents. Table 8-6 provides an overview of the comparison operations.
An example follows the table.
Table 8-6. Overview of Comparison Operations

! = F Compare for “equal to”

The contents of the two accumulators are interpreted as bit patterns
and scanned to see if they are equal.
> < F Compare for “not equal to”
The contents of the two accumulators are interpreted as bit patterns
and compared to see if they are not equal.
> F Compare for “greater than”
The contents of the two accumulators are interpreted as fixed-point
numbers. They are compared to see if the operand in ACCU 2 is
greater than the operand in ACCU 1.
> = F Compare for “greater than or equal to”

greater than or equal to the operand in ACCU 1.
< F Compare for “less than”
less than the operand in ACCU 1.
< = F Compare for “less than or equal to”

less than or equal to the operand in ACCU 1.
Processing Comparison Operations

To compare two operands, load them consecutively into the two accumulators. Execution of the
operations is independent of the RLO.
The result is binary and is available as RLO for further program processing. If the comparison is
satisfied, the RLO is “1”. Otherwise it is “0”.
Executing the comparison operations sets the condition codes (see section 8.4).
Note
When using comparison operations, make sure the operands have the same number
format.
8-30 EWA 4NEB 812 6120-02

Example: The values of input bytes IB19 and IB20 are compared. If they are equal, output
Q 1.0 is set.
Circuit Diagram STL CSF/LAD
IB19 IB20
L IB 19
L IB 20
!=F C1 F
C1 C2 IB19
= Q 1.0
!=
=
IB20 C2 Q Q 1.0
Q 1.0
8.1.7 Arithmetic Operations
Arithmetic operations interpret the contents of the accumulators as fixed-point numbers and
manipulate them. The result is stored in ACCU 1. Table 8-7 provides an overview of the arithmetic
operations. An example follows the table.
Table 8-7. Overview of Arithmetic Operations

+F Addition
The contents of both accumulators are added.
-F Subtraction
The contents of ACCU 1 are subtracted from the contents of
ACCU 2.
CPU 102 and higher have integral function blocks for multiplication and division (see section 9.2).
EWA 4NEB 812 6120-02 8-31

Processing an Arithmetic Operation

Before an arithmetic operation is executed, both operands must be loaded into the accumulators.
Note
When using arithmetic operations, make sure the operands have the same number
format.
Arithmetic operations are executed independently of the RLO. The result is available in ACCU 1 for
further processing. The contents of ACCU 2 are not changed.
These operations do not affect the RLO. The condition codes are set according to the results.
STL Explanation
L C 3 The value of counter 3 is loaded into ACCU 1.
L C 1 The value of counter 1 is loaded into ACCU 1. The previous contents of

ACCU 1 are shifted to ACCU 2.
+ F The contents of the two accumulators are interpreted as 16-bit fixed-point

numbers and added.
T QW12 The result, contents of ACCU 1, is transferred to output word QW12.
Numeric Example
15 0
876 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 ACCU 2
+ +F
668 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 ACCU 1
=
1544 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 ACCU 1
8-32 EWA 4NEB 812 6120-02

8.1.8 Block Call Operations

Block call operations specify the sequence of a structured program. Table 8-8 provides an overview
of the block call operations. Examples follow the table.
Table 8-8. Overview of Block Call Operations

JU Jump unconditionally
Program scanning continues in a different block regardless of the
RLO.
JC Jump conditionally
Program scanning jumps to a different block when the RLO is “1”.
Otherwise program scanning continues in the same block.
The RLO is set to “1”.
OB 0 to 63 0 to 63 0 to 255*
PB 0 to 63 0 to 63 0 to 255
FB 0 to 63 0 to 63 0 to 255
SB 0 to 255
C Call a data block

A data block is activated regardless of the RLO.
Program scanning is not interrupted.
G Generate and delete a data block**
An area is set up in the RAM to store data regardless of the RLO.
DB 2 to 63*** 2 to 63*** 2 to 255***
BE Block end
The current block is terminated regardless of the RLO.
Program scanning continues in the block in which the call originated.
The RLO is “carried along” but not affected. BE is always the last
statement in a block.
BEU Block end, unconditional

The current block is terminated regardless of the RLO.
The RLO is “carried along” but not affected.
BEC Block end, conditional
When the RLO is “1”, the current block is terminated.
During the block change, the RLO remains “1”.
If the RLO is “0”, the operation is not executed.
The RLO is set to “1” and linear program scanning continues.
* If using the PG 615, select “SYS. OPS. Y” in the presets menu. Also note that certain OBs are assigned
by the operating system.
** The length of the DB must be loaded into ACCU 1 before execution of the operation. A length of 0
makes the DB invalid.
*** Data blocks DB0 and DB1 are reserved for special functions.
EWA 4NEB 812 6120-02 8-33

Unconditional Block Call “JU”
One block is called within another block, regardless of conditions.
Example: A special function has been programmed in FB26. It is called at several locations in
the program, e.g., in PB63, and processed.
Program Sequence STL Explanation
.
PB63 FB26 . The “JU FB26” statement in program
. block PB63 calls function block FB26.
.
.
JU FB 26
.
JU FB26
Conditional Block Call “JC”

One block is called within another block when the previous condition has been satisfied
(RLO = “1”).
Example: A special function has been programmed in FB63. It is called and processed under
certain conditions, e.g., in PB10.
.
PB10 FB63 . The “JC FB63” statement in program
. block PB10 calls function block FB63
S F 1.0 if input I 0.0 is “1”.
A I 0.0 A I 0.0
JC FB 63
JC FB63 .
8-34 EWA 4NEB 812 6120-02

Call a Data Block “C DB”

Data blocks are always called unconditionally. All data processed following the call refers to the data
block that has been called. This operation cannot generate new data blocks. Blocks that are called
must be programmed or created before program scanning.
Example: Program block PB3 needs information that has been programmed as data word DW1 in
data block DB10. Other data, e.g., the result of an arithmetic operation, is stored as
data word DW3 in data block DB20.
PB3 DB10
C DB 10 The information from data word DW1
in data block DB10 is loaded into the
C DB10 DW1 L DW 1 accumulator. The contents of ACCU 1
L DW1 . are stored in data word DW3 of data
. block DB20.
.
C DB20 .
DB20
C DB 20
T DW3
DW3
T DW 3
Generating and Deleting a Data Block

The “G DB x” statement does not call a data block. Instead, it generates a new block. If you want
to use the data in this data block, call it with the “C DB” statement.
Before the “G DB” statement, indicate in ACCU 1 the number of data words the block is to have
(see the example below).
If you specify zero as the data block length, the data block in question is deleted, i.e., it is removed
from the address list. It is considered nonexistent.
Note
The block is stored in memory and is designated as invalid until the programmable
controller memory is compressed (see section 7.5.3).
If you try to set up a data block that already exists, the “G DB x” statement is not executed.
A data block can be a maximum of 256 data words (DW0 to 255) in length.
EWA 4NEB 812 6120-02 8-35

Generating a Data Block

Generate a data block with 128 data L KF + 127 The constant fixed-point number
words without the aid of a pro- G DB 5 +127 is loaded into ACCU 1. At
grammer. the same time, the old contents
of ACCU 1 are shifted to ACCU 2.
Data block 5 is generated with a
length of 128 data words (0000)
in the RAM of the PLC and
entered in the block address list.
The next time the “G DB5”
operation is processed, it has no
effect if the contents of
ACCU 1 are not 0.
Deleting a Data Block

Delete a data block that is no longer L KF + 0 The constant fixed-point number
needed. G DB 5 +0 is loaded into ACCU 1. At the
same time, the old contents of
ACCU 1 are shifted to ACCU 2.
Data block 5, which must be in
the RAM of the PLC, is declared
invalid and removed from the
block address list.
8-36 EWA 4NEB 812 6120-02

Block End “BE”

The “BE” operation terminates a block. Data blocks do not need to be terminated. “BE” is always
the last statement in a block.
In structured programming, program scanning jumps back to the block where the call for the current
block was made.
Boolean logic operations cannot be continued in a higher-order block.
Example: Program block PB3 is terminated by the “BE” statement.

.
OB1 PB3
. The “BE” statement terminates
. program block PB3 and causes
. program scanning to return to
JU PB3 . organization block OB1.
.
BE
BE
Unconditional Block End “BEU”

The “BEU” operation causes a return within a block. However, jump operations can bypass the
“BEU” operation in function blocks (see sections 8.2.10 and 8.3.4).
Binary logic operations cannot be continued in a higher-order block.
Example: Scanning of function block FB21 is terminated regardless of the RLO.
PB8 FB21 .
. The “BEU” statement causes program
. scanning to leave function block FB21
. and return to program block PB8.
JC=
JC= BEU
.
JU FB21 BEU .
.
.
BE
BE
EWA 4NEB 812 6120-02 8-37

Conditional Block End “BEC”

The “BEC” operation causes a return within a block if the previous condition has been satisfied
(RLO = 1).
Otherwise, linear program scanning is continued with RLO “1”.
Example: Scanning of program block FB20 is terminated if the RLO = “1”.
PB7 FB20 .
. The “BEC” statement causes program
. scanning to return to program block
. PB7 from function block FB20 if input
A I 0.0 I 0.0 is “1”.
A I 0.0 BEC
.
JU FB20 BEC .
.
.
8.1.9 Other Operations
Table 8-9 lists other basic operations. Explanations follow the table.
Table 8-9. Other Operations

STP Stop at the end of program scanning (in OB1)

Current program scanning is terminated.
The PIQ is read out. Then the PLC goes into the STOP mode.
NOP 0 “No” Operation

Sixteen bits in the RAM are set to “0”.
NOP 1 “No” Operation

Sixteen bits in the RAM are set to “1”.
BLD Display Generation Operation

“BLD” means a display generation operation for the programmer.
ID Parameter
130, 131, 132, 133, 255
Note
These operations can be programmed in STL form only.
8-38 EWA 4NEB 812 6120-02

STOP Operation
The “STP” operation puts the programmable controller into the STOP mode. This can be desirable
for time-critical system circumstances or when a programmable controller error occurs.
After the statement is processed, the control program is scanned to the end, regardless of the RLO.
Afterwards the programmable controller goes into the STOP mode with the error ID “STS”. You
can restart the programmable controller with the mode selector (STOP to RUN) or with a
programmer.
“NOP” (No Operations)

The “NOP” operations reserve or overwrite memory locations.
Display Generation Operations

“BLD” display generation operations divide program parts into segments within a block.
“NOP” operations and display generation operations are significant only for the programmer when
representing the STEP 5 program.
The programmable controller does not execute any operation when these statements are processed.
8.2 Supplementary Operations
Supplementary operations extend the operations set. However, compared to basic operations,
which can be programmed in all blocks, supplementary operations have the following limitations.
• They can be programmed in function blocks only.
• They can be represented in STL form only.
The following sections describe the supplementary operations.
EWA 4NEB 812 6120-02 8-39

8.2.1 Load Operation, for CPU 103 and Higher
As with the basic load operations, the supplementary load operation copies information into the
accumulator. Table 8-10 explains the load operation. An example follows the table.
Table 8-10. Load Operation

L Load
A word from the system data is loaded into ACCU 1 regardless of the
RLO.
ID Parameter
RS 0 to 255
In order to set parameters for ...

SINEC L1 bus operation via the L RS 57 Load ACCU 1 with the pro-
system data, the programmer and ... grammer and slave numbers.
slave numbers from SD57 should
be input into ACCU 1.
8-40 EWA 4NEB 812 6120-02

8.2.2 Enable Operation, for CPU 103 and Higher
You can use the enable operation (FR) to execute the following operations even without an edge
change.
• Start a timer
• Set a counter
• Count up and down
Table 8-11 presents the enable operation. An example follows the table.
Table 8-11. Enable Operation

FR Enable a Timer/Counter
Timers and counters are enabled on the leading edge of the RLO.
This operation restarts a timer, sets a counter, or causes a counter
to count up or down when the RLO “1” is pending at the “Start”
operation.
ID Parameter
T 0 to 127
C 0 to 127
Input I 0.0 starts a timer T 2 as an A I 0.0

extended pulse (pulse width 50 s). L KT 500.1
This timer sets output Q 1.0 for the SE T 2 Start a timer T 2 as an extended
duration of the pulse. A T 2 pulse.
= Q 1.0 Output Q 1.0 is set for 50 s.
. .
. .
. .
. .
If output Q 1.1 is reset repeatedly, the A Q 1.1 If output Q 1.1 is set (positive
timer should also be restarted FR T 2 edge change of the RLO) during
repeatedly. the time in which input I 0.0 is
BE set, timer T 2 is restarted. Output
Q 1.0 therefore remains set at the
restarted time or is reset.
If input I 0.0 is not set during the
edge change of output Q 1.1, the
timer is not restarted.
EWA 4NEB 812 6120-02 8-41

8.2.3 Bit Test Operations, for CPU 103 and Higher
Bit test operations scan digital operands bit by bit and affect them. Bit test operations must always
be at the beginning of a logic operation. Table 8-12 provides an overview of these operations.
Table 8-12. Overview of Bit Operations

TB Test a bit for signal state “1”

A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
TBN Test a bit for signal state “0”

A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
SU Set a bit unconditionally

The addressed bit is set to “1” regardless of the RLO. The RLO is
not affected.
RU Reset a bit unconditionally
The addressed bit is set to “0” regardless of the RLO. The RLO is
not affected.
ID Parameter
T 0.0 to 127.15
C 0.0 to 127.15
D 0.0 to 255.15
RS1 0.0 to 255.15
1 RS applies only to TB and TBN
Table 8-13 shows how the RLO is formed during the bit test operations “TB” and “TBN”. An
example for applying the bit operations follows the table.
Table 8-13. Effect of “TB” and “TBN” on the RLO

Operation TB TBN
Signal state of the bit in 0 1 0 1

the operand indicated
Result of logic operation 0 1 1 0
8-42 EWA 4NEB 812 6120-02

A photoelectric barrier that counts C DB 10 Call data block 10.

piece goods is installed at input A I 0.0
I 0.0. After every 100 pieces, the CU C 10 Input I 0.1 loads the count of
program is to jump to FB5 or FB6. A I 0.1 counter 10 with the constant 0. With
After 800 pieces, counter 10 is to L KC 000 each positive edge change at I 0.0,
be reset automatically and start S C 10 the counter is incremented by 1. The
counting again. O I 0.2 counter is reset by either input I 0.2
O F 5.2 or flag F 5.2.
R C 10
LD C 10 The current count of the counter is
T DW 12 stored in data word DW12 in BCD
code.
TBN D 12.8 As long as bit 8 of data word DW12

is zero, program processing jumps to
JC FB 5 function block FB5. This is the case
for the first, third, fifth etc. batch of
100 pieces.
TB D 12.8 As long as bit 8 of data word DW12
is “1”, program scanning jumps to
JC FB 6 function block FB 6. This is the case
for the second, fourth, sixth, etc.
batch of 100 pieces.
TB D 12.11 When data bit 11 of data word DW12
becomes “1” (the count is then 800),
= F 5.2 flag F 5.2 is set conditionally.
A photoelectric barrier that counts :A I 0.3 Input I 0.4 loads the count of counter
piece goods is installed at input :CU C 2 20 with the constant 0. The count is
I 0.3. After every 256 pieces, the :A I 0.4 incremented by 1 with each positive
counter is supposed to be reset and :L KC 000 edge change at input I 0.3. If the
start counting again. :S C 20 count has reached 256 = 100H (bit 8
is “1”), program scanning jumps to
:TB C 20.8 the label “FULL”. Otherwise the
block is terminated.
:JC = FULL
:BEU
FULL:RU C 20.8 Bit 8 of counter C 20 is set to “0”

:BE unconditionally. Then the count is
again 000H.
Note
Times and counts are stored in the timer/counter word in hexadecimal notation in the
10 least significant bits (bits 0 to 9).
The time base is stored in bits 12 and 13 of the timer word.
EWA 4NEB 812 6120-02 8-43

8.2.4 Digital Logic Operations
Digital logic operations combine the contents of both accumulators logically bit by bit.
Table 8-14 provides an overview of these digital logic operations. Examples follow the table.
Table 8-14. Overview of Digital Logic Operations

AW Combine bit by bit through logic AND

OW Combine bit by bit through logic OR
XOW Combine bit by bit through logic EXCLUSIVE OR
Processing a Digital Logic Operation

A digital logic operation is executed regardless of the RLO. It also does not affect the RLO.
However, it sets condition codes according to the result of the arithmetic operation (see section 8.4).
Note
Make sure both operands have the same number format. Then load them into the
accumulators before executing the operation.
8-44 EWA 4NEB 812 6120-02

The result of the arithmetic operation is available in ACCU 1 for further processing. The contents of
ACCU 2 are not affected.
STL Explanation
L IW 92 Load input word IW92 into ACCU 1.
L KH 00FF Load a constant into ACCU 1. The previous contents of ACCU 1 are shifted
to ACCU 2.
AW Combine the contents of both accumulators bit by bit through logic AND.
T QW 82 Transfer the resulting contents from ACCU 1 to output word QW82.
Numeric Example
IW92 Set the 8 high-order bits in input

15 0
word IW92 to “0”.
ACCU 2 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 Compare both words bit by bit. If
AND corresponding bits are both “1”, the
KH 00FF result bit is set to “1”.
ACCU 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Result
ACCU 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0
EWA 4NEB 812 6120-02 8-45

STL Explanation
L KH 00FF Load a constant into ACCU 1. The previous contents of ACCU 1 are shifted
to ACCU 2.
OW Combine the contents of both accumulators bit by bit through logic OR.
T IW 36 Transfer the result (contents of ACCU 1) to input word IW36.
Numeric Example
IW36
15 0 Set the 8 low-order bits in input word
ACCU 2 1 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 IW36 to “1”. Compare both words
bit by bit.
OR If either of the corresponding bits is
KH 00FF “1”, a “1” is set in the result word.
ACCU 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Result
ACCU 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1
8-46 EWA 4NEB 812 6120-02

STL Explanation
L IW 6 Load input word IW6 into ACCU 1. The previous contents of ACCU 1 are
shifted to ACCU 2.
XOW Combine the contents of both accumulators bit by bit through logic
EXCLUSIVE OR.
T QW 86 Transfer the result (contents of ACCU 1) to output word QW86.
Numeric Example
IW70 Check to see if input words IW70

15 0
and IW6 are equal.
ACCU 2 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 The result bit is set to “1” only if
X-OR corresponding bits in ACCU 1 and
IW6 ACCU 2 are unequal.
ACCU 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0
Result
ACCU 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0
EWA 4NEB 812 6120-02 8-47

8.2.5 Shift Operations
Shift operations shift a bit pattern in ACCU 1. The contents of ACCU 2 are not affected. Shifting
multiplies or divides the contents of ACCU 1 by powers of two. Table 8-15 provides an overview of
the shift operations. Examples follow the table.
Table 8-15. Overview of Shift Operations

SLW Shift to the left.

The bit pattern in ACCU 1 is shifted to the left.
SRW Shift to the right.

The bit pattern in ACCU 1 is shifted to the right.
Parameter 0 to 15
Processing a Shift Operation

Execution of shift operations is unconditional. The RLO is not affected. However, shift operations
set condition codes.
Consequently, the status of the last bit that is shifted out can be scanned with jump functions.
The shift statement parameter indicates the number of bit positions by which the contents of
ACCU 1 are to be shifted to the left (SLW) or to the right (SRW). Bit positions vacated during
shifting are assigned zeros.
The contents of the bits that are shifted out of ACCU 1 are lost. Following execution of the
operation, the state of bit 20 (SRW) or bit 215 (SLW) has an influence on the CC1 bit, which can
then be evaluated.
A shift operation with parameter “0” is handled like a “NOP” operation. The central processor pro-
cesses the next STEP 5 statement with no further reaction.
Before executing a shift operation, load the operand to be processed into ACCU 1.
The altered operand is available there for further processing.
8-48 EWA 4NEB 812 6120-02

STL Explanation
L DW 2 Load the contents of data word DW2 into ACCU 1.
SLW 3 Shift the bit pattern in ACCU 1 three positions to the left.
T DW 3 Transfer the result (contents of ACCU 1) to data word DW3.
Numeric Example
46410 (DW2) The value 46410 is stored in data

15 0
word DW2. Multiply this value by
ACCU 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0
23=8. Do so by shifting the bit
pattern of DW2 in ACCU 1 three
SLW 3 positions to the left.
371210
15 0
ACCU 1 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0
STL Explanation
L IW 124 Load the value of input word IW124 into ACCU 1.
SRW 4 Shift the bit pattern in ACCU 1 four positions to the right.
T QW 126 Transfer the result (contents of ACCU 1) to output word QW126.
Numeric Example
35210 (IW124) The value 35210 is stored in IW124.

15 0
Shift the corresponding bit pattern in
ACCU 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0
ACCU 1 four positions to the right to
divide the value 35210 by 24 = 16.
SRW 4
2210
15 0
ACCU 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
EWA 4NEB 812 6120-02 8-49

8.2.6 Conversion Operations
Conversion operations convert the values in ACCU 1. Table 8-16 provides an overview of the
conversion operations. Examples follow the table.
Table 8-16. Overview of Conversion Operations

CFW One's complement

The contents of ACCU 1 are inverted bit by bit.
CSW Two's complement

The contents of ACCU 1 are inverted bit by bit. Afterwards the word
0001H is added.
Processing Conversion Operations

Execution of these operations does not depend on the RLO nor does it affect the RLO.
The “CSW” operation sets the condition codes (see section 8.4).
STL Explanation
L DW 12 Load the contents of data word DW12 into ACCU 1.
CFW Invert all bits in ACCU 1.
T QW 20 Transfer the new contents of ACCU 1 to output word QW20.
Numeric Example
DW12 In a system, normally open contacts

15 0
ACCU 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0
have been replaced by normally
closed contacts. If the information in
data word DW12 is to maintain its
CFW previous effect, DW12 must be
15 0
inverted.
ACCU 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1
8-50 EWA 4NEB 812 6120-02

STL Explanation
L IW 12 Load the contents of input word IW12 into ACCU 1.
CSW Invert all bits and add a “1”.
T DW 100 Transfer the altered word to data word DW100.
Numeric Example
Form the negative value of the value

IW12 in input word IW12.
15 0
ACCU 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1
CSW +1
15 0
ACCU 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1
EWA 4NEB 812 6120-02 8-51

8.2.7 Decrement/Increment, for CPU 103 and Higher
The decrement/increment operations change the data loaded into ACCU 1. Table 8-17 provides an
overview of the decrement/increment operations. An example follows the table.
Table 8-17. Decrement/Increment Operations

D Decrement
Decrement the contents of the accumulator.
I Increment
Increment the contents of the accumulator.
The contents of ACCU 1 are either decremented or incremented by
the number indicated in the parameter.
Execution of the operation is unconditional and is limited to the
right-hand byte (without carry).
Parameter
0 to 255
Processing
Execution of the decrement and increment operations is independent of the RLO and does not affect
the RLO or the condition codes.
The parameter indicates the value by which the contents of ACCU 1 are to be changed.
The operations refer to decimal values; however, the result is stored in ACCU 1 in binary form.
Changes relate only to the low byte in the accumulator.
Increment the hexadecimal constant C DB 6 Call data block DB6.

1010H by 16 and store the result in L KH 1010 Load hexadecimal constant 1010H
data word DW8. into ACCU 1.
I 16 Increment the low byte of ACCU 1
by 16. The result, 1020H, is
located in ACCU 1.
In addition, decrement the incremen- T DW 8 Transfer the contents of ACCU 1
tation result by 33 and store the new (1020H) to data word DW8. Since
result in data word DW9. the incrementation result is still in
ACCU 1, you can decrement by 33
directly.
D 33 The result would be FFFH.
However, since the high byte of
ACCU 1 is not decremented along
with the low byte, the result in
ACCU 1 is 10FFH.
T DW 9 The contents of ACCU 1 are
transferred to DW9 (10FFH).
8-52 EWA 4NEB 812 6120-02

8.2.8 Disable/Enable Interrupt, for CPU 103 Version 8MA02 and Higher
The disable/enable interrupt operations affect interrupt-driven and time-controlled program scanning.
They prevent process or time interrupts from interfering with the processing of a sequence of state-
ments or blocks. Table 8-18 lists the disable/enable interrupt operations. An example follows the
table.
Table 8-18. Disable/Enable Interrupt Operations

IA Disable interrupt
RA Enable interrupt
Processing
Execution of the disable/enable interrupt operations does not depend on the RLO. These operations
do not affect the RLO or the condition codes. After the “IA” statement is processed, no more
interrupts are executed. The “RA” statement cancels the effect of “IA”.
Disable interrupt processing in a .

specific program section and then .
enable it again. .
.
.
= Q 1.0
IA Disable interrupt.
A I 0.0
.
.
.
JU FB 3 If an interrupt occurs, the program
. section between the “IA” and
. “RA” is scanned without
. interruption.
RA Enable interrupt.
. Interrupts that occurred in the
. meantime are processed after the
. “RA” operation.
EWA 4NEB 812 6120-02 8-53

8.2.9 “DO” Operation, for CPU 103 and Higher
Use the “DO” operation to process STEP 5 statements as indexed operations. This allows you to
change the parameter of an operand during control program processing (see Table 8-19).
Table 8-19. Overview of the “DO” Operation

DO Processing a flag word or data word

ID Parameter
FW 0 to 254
DW 0 to 255
“DO” Statements
“DO flag word or data word x” is a two-word statement that is unaffected by the RLO. “DO”
consists of the following two statements:
• The first statement contains the “DO” operation and a flag word or data word.
• The second statement defines the operation and the operand identifier you want the control
program to process. You must enter 0 or 0.0 as the parameter.
The control program works with the parameter that is stored in the flag word or data word. This
parameter is the one called up in the first statement. If you want to index binary operations, inputs,
outputs, or flags, you input the bit address in the high byte of this word. You input the byte address
in the low byte. In any other instance, the high byte must be “0”.
You can combine the following operations with the “DO” statement:
Table 8-20. Operations That Can Be Combined with the “DO” Statement
Operations Explanations
A1, AN, O, ON Boolean logic operations

S, R, = Set/reset operations
FR T, RT, SF T, SD T, SP T, SS T, SE T, Timer operations
FR C, RC, SC, CD C, CU C Counter operations
L, LD, T Load and transfer operations
JU=, JC=JZ=, JN=, JP=, JM=, JO= Jump operations
SLW, SRW Shift operations
D, I Decrement and increment
C DB, JU, JC, TNB Block calls
1 In combination with “DO FW,” the “A I” operation becomes the “A Q” operation if the byte address in
the data word or flag word is higher than 127.
! Caution
Damage to the system.
Performing operations that are not listed in Table 8-20 will damage your system.
Perform only those operations that are listed in Table 8-20.
8-54 EWA 4NEB 812 6120-02

Figure 8-6 shows how the contents of a data word determine the parameter of the next statement.
DB6 FBx Actual program

:C DB 6 :C DB 6
. .
. .
. .
:DO DW 12 .
DW 12 KH = 0108 :A I 8.1
:A I 0.0
DW 13 KH = 0001 :DO DW 13 .
:FR T 0 :FR T 1
Figure 8-6. Executing a “DO” Operation
The following example illustrates how new parameters are generated in every program scan.

Set the contents of data words :C DB 202 Call data block DB202.
DW20 to DW100 to signal state :L KB 20 Load constant number 20 in
“0”. The index register for the ACCU 1.
parameter for the data words is :T DW 1 Transfer contents from ACCU 1 to
DW1. data word DW1.
F 1 :L KH 0 Load hex constant 0 in ACCU 1.
:DO DW 1 DO data word DW1.
:T DW 0 Transfer the contents from ACCU 1

to the data word whose address is
stored in data word DW1.
:L DW 1 Load data word DW1 in ACCU 1.
:L KB 1 Load constant number 1 in ACCU 1.

Data word DW1 is shifted to
ACCU 2.
:+F ACCU 2 und ACCU 1 are added,
and the result is stored in ACCU 1
(data word address is higher).
:T DW 1 Transfer contents of ACCU 1 to data

word DW1 (new data word address).
:L KB 100 The constant number 100 is loaded
in ACCU 1 and the new data word
address is shifted to ACCU 2.
:<=F Compare the ACCUs for less than or

equal to: ACCU 2 ACCU 1.
:JC = F 1 Jump conditionally to label F1, if
ACCU 2 ACCU 1.
EWA 4NEB 812 6120-02 8-55

8.2.10 Jump Operations
Table 8.21 provides an overview of the jump operations. An example follows the table.
Table 8-21. Overview of Jump Operations

JU = Jump unconditionally
The unconditional jump is executed independently of conditions.
JC= Jump conditionally
The conditional jump is executed if the RLO is “1”. If the RLO is
“0”, the statement is not executed and the RLO is set to “1”.
JZ = Jump if the result is “zero”
The jump is executed only if CC 1 = 0 and CC 0 = 0
The RLO is not changed.
JN = Jump if the result is “not zero”

The jump is executed only if CC 1 CC 0
JP = Jump if the result is positive

JM = Jump if the result is negative
JO = Jump on overflow
The jump is executed if an overflow occurs. Otherwise the jump is
not executed. The RLO is not changed.
ID
Jump label (up
to 4 characters)
8-56 EWA 4NEB 812 6120-02

Processing Jump Operations

A symbolic jump destination (jump label) must always be entered next to a jump operation. This
jump label can have up to four characters. The first character must be a letter of the alphabet.
When programming, please be aware of the following items:

• The absolute jump displacement cannot exceed +127 or - 128 words in the program memory.
Some statements take up two words (e.g., “Load a constant”). For long jumps, insert an inter-
mediate destination.
• Jumps can be executed only within a block.
• Jumping over segment boundaries (“BLD 255”) is not permitted.
• Jump labels can be set only at the start of a series of scans for CPU 102.
If no bit of input word IW1 is AN0 :L IW 1 Load input word IW1 into
set, program scanning jumps to :L KH 0000 ACCU 1. If the contents of
the label “AN 1”. If input word :+F ACCU 1 equal zero1, jump to
IW1 and output word QW3 do :JZ= AN 1 the label “AN 1”. Otherwise
not agree, program processing :A I 0.0 process the next statement
jumps back to the label “AN 0”. . (I 0.0).
Otherwise input word IW1 and .
data word DW12 are compared. .
If input word IW1 is greater than .
or less than data word DW12, .
program scanning jumps to the .
“DEST” label. AN1 :L IW 1 Compare input word IW1 and
:L QW 3 output word QW3. If they are
:XOW not equal, set individual bits in
ACCU 1.
:JN = AN 0 If the contents of ACCU 1 are
:L IW 1 not zero, jump to the label
:L DW12 “AN 0”. Otherwise process the
:>< F next statements.
Compare input word IW1 and
data word DW12. If they are
not equal, set RLO to “1”.
:JC = DEST If the RLO = “1”, jump to the
. “DEST” label. If the RLO =
. “0”, process the next
. statement.
.
.
DEST :A I 0.1
.
.
1 The “L...” statement does not affect the condition codes. An addition (+F) is executed with the constant
0000H so that the “JZ” operation can evaluate the contents of the accumulator.
EWA 4NEB 812 6120-02 8-57

8.2.11 Substitution Operations, for CPU 103 and Higher
If you plan to process a program with various operands and without a lot of changes, it is advisable
to assign parameters to individual operands (see section 7.3.4). If you have to change the ope-
rands, you only need to reassign the parameters in the function block call.
These parameters are processed in the program as “formal operands”.

Special operations are necessary for this processing. However, these special operations are no
different in their effect than operations without substitution. A brief description of these operations
and examples follows.
Binary Logic Operations

Table 8-22 provides an overview of binary logic operations.
Table 8-22. Overview of Binary Logic Operations

A = AND operation
Scan a formal operand for “1”.
AN = AND operation
O = OR operation
ON = OR operation
Actual operands permitted Parameter Data

Formal operand type type
Inputs, outputs, and flags I, Q, F BI

addressed in binary form
Timers and counters T, C
8-58 EWA 4NEB 812 6120-02

Set/Reset Operations
Table 8-23 provides an overview of the set/reset operations. An example follows the table.
Table 8-23. Overview of Set/Reset Operations

S = Set a formal operand (binary).
RB = Reset a formal operand (binary).
= = Assign
The RLO is assigned to a formal operand.
Parameter Data
Formal operand Actual operands permitted
type type
Inputs, outputs, and flags I, Q, F BI

addressed in binary form
Example: FB30 is assigned parameters in OB1.
Call in OB1 Program in FB30 Executed Program

:JU FB 30 :A =ON 1 :A I 0.0
NAME :COMBINE :AN =ON 2 :AN I 0.1
ON 1 : I 0.0 :O =ON 3 :O I 0.2
ON 2 : I 0.1 :S =MOT 5 :S Q 1.2
ON 3 : I 0.2 := =OFF 1 := Q 1.0
VAL1 : I 0.3 :A =VAL 1 :A I 0.3
OFF1 : Q 1.0 :A =ON 2 :A I 0.1
OFF2 : Q 1.1 :ON =ON 3 :ON I 0.2
MOT5 : Q 1.2 :RB =MOT 5 :R Q 1.2
: BE := =OFF 2 := Q 1.1
:BE :BE
EWA 4NEB 812 6120-02 8-59

Load and Transfer Operations

Table 8-24 lists the various load and transfer operations. An example follows the table.

L = Load a formal operand.

LD = Load a formal operand in BCD code.
LW = Load the bit pattern of a formal operand.

T = Transfer to a formal operand.
Actual operands permitted Parameter Data

Formal operand type type
For L = Inputs, outputs, and flags I, Q, F BY, W

addressed in binary form PW*, PY*
Data DW, DR, DL
Timers and counters T, C
For LD = Timers and counters T, C
For LW = Bit pattern D KF, KH, KM,

KY, KS, KT, KC
For T = Inputs, outputs, data (DW, I, Q BY, W

DR, DL) and flags DW, DR, DL
addressed in binary form F, PW*, PY*
* Not for integral function blocks
Example: FB34 is assigned parameters in PB1.
Call in PB1 Program in FB34 Executed Program
:A =I 0 :A I 0.0
:JU FB 34 :L =L1 :L FW 10
NAME :LOAD/TRAN :S C 6 :S C 6
I0 : I 0.0 :A =I 1 :A I 0.1
I1 : I 0.1 :LW =LW1 :L KC 140
L1 : FW 10 :S C 7 :S C 7
LW1 : : KC 140 :A I 0.2 :A I 0.2
LC1 : C 7 :CU C 6 :CU C 6
T1 : QW 4 :CU C 7 :CU C 7
LW2 : : KC 160 :LD =LC1 :LD C 7
:BE :T =T1 :T QW 4
:A I 0.3 :A I 0.3
:R C 6 :R C 6
:R C 7 :R C 7
:LW =LW2 :L KC 160
:LD =LC1 :LD C 7
:!=F :!=F
:R C 7 :R C 7
:BE :BE
8-60 EWA 4NEB 812 6120-02

Timer and Counter Operations

Table 8-25 provides an overview of timer and counter operations. Examples follow the table.
Table 8-25. Overview of Timer and Counter Operations

FR = Enable a formal operand for a cold restart. (For a description,

see “FT” or “FC”, according to the formal operand).
RD = Reset a formal operand (digital).
SP = Start a pulse timer specified as a formal operand using the value

stored in the accumulator.
SD = Start an on-delay timer specified as a formal operand using the
value stored in the accumulator.
SEC = Start an extended pulse timer specified as a formal operand

using the value stored in the accumulator or set a counter
specified as a formal operand using the count specified in the
accumulator.
SSU = Start a stored on-delay timer specified as a formal operand using

the value stored in the accumulator or start the count up of a
counter specified as a formal operand.
SFD = Start an off-delay timer specified as a formal operand using the

value stored in the accumulator or start the count down of a
counter specified as a formal operand.
Formal operand Actual operands permitted Parameter Data

type type
Timers and counters1 T, C1
1 “SP” and “SD” do not apply to counters.
Specifying Times and Counts

As with the basic operations, you can specify a time or count as a formal operand. In this case, you
must distinguish as follows whether the value is located in an operand word or is specified as a
constant.
• Operand words can be of parameter type “I” or “Q” and of data type “W”. Use the
“L=” operation to load them into the accumulator.
• Constants can be of parameter type “D” and of data type “KT” or “KC”. Use “LW=” to load
these formal operands into the accumulator.
EWA 4NEB 812 6120-02 8-61

The following examples show how to work with timer and counter operations:
Example 1:
Function Block Call Program in Function Block (FB32) Executed Program
:AN =I 5 :AN I 0.0

:JU FB 32 :A =I 6 :A I 0.1
NAME :TIME :L KT 005.2 :L KT 5.2
I 5 : I 0.0 :SFD =TIM5 :SF T 5
I 6 : I 0.1 :A =I 5 :A I 0.0
TIM5 : T 5 :AN =I 6 :AN I 0.1
TIM6 : T 6 :L KT 005.2 :L KT 5.2
OFF6 : Q 1.0 :SSU =TIM6 :SS T 6
:BE :A =TIM5 :A T 5
:O =TIM6 :O T 6
:= =OFF6 := Q 1.0
:A I 0.2 :A I 0.2
:RD =TIM5 :R T 5
:RD =TIM6 :R T 6
:BE :BE
Example 2:
Function Block Call Program in Function Block (FB33) Executed Program

:A =I 2 :A I 0.0
:JU FB 33 :L KC 017 :L KC 017
NAME :COUNT :SEC =CNT5 :S C 5
I2 : I 0.0 :A =I 3 :A I 0.1
I3 : I 0.1 :SSU =CNT5 :CU C 5
I4 : I 0.2 :A =I 4 :A I 0.2
CNT5 : C 5 :SFD =CNT5 :CD C 5
OFF3 : Q 1.0 :A =CNT5 :A C 5
:BE := =OFF3 := Q 1.0
:A I 0.3 :A I 0.3
:RD =CNT5 :R C 5
:BE :BE
8-62 EWA 4NEB 812 6120-02

“DO” Operation
Table 8-26 and the example that follows explain the processing operation.
Table 8-26. “DO” Operation

DO = Process formal operand

The substituted blocks are called unconditionally.
Formal operands Actual operands permitted Parameter Data

type type
DB, PB, SB, FB1 B

1 As actual operands, function blocks cannot have block parameters.
Example:
Function Block Call Program in Function Block FB35 Executed Program

STL
:JU FB 35 :DO =D5 :C DB 5
NAME :DO :L =DW2 :L DW 2
D5 : DB 5 :DO =D6 :C DB 6
DW2 : DW 2 :T =DW1 :T DW 1
D6 : DB 6 :T =Q4 :T QW 4
DW1 : DW 1 :DO =MOT5 :JU FB 36
Q4 : QW 4 :BE :BE
MOT5 : FB 36
:BE
EWA 4NEB 812 6120-02 8-63

8.3 System Operations, for CPU 103 and Higher
System operations and supplementary operations have the following limitations:

• You can program them only in function blocks.
• You can program them only in the STL method of representation.
Since system operations access system data, only users with system knowledge should use them.
If you want to program system operations, you must select “SYS: OPS. Y” in the programmer
presets menu.
8.3.1 Set Operations
Like the supplementary bit operations, these set operations can change individual bits. Table 8-27
provides an overview of the set operations.
Table 8-27. Overview of Set Operations

SU Set bit unconditionally
A specific bit is set to “1” in the system data area.
RU Reset bit unconditionally
A specific bit is set to “0” in the system data area.
ID Parameter
RS 0.0 to 255.15
Processing Set Operations

Execution of set operations does not depend on the RLO.
8.3.2 Load and Transfer Operations
Use these load and transfer operations to address the entire program memory of the programmable
controller. They are used mainly for data exchange between the accumulator and memory locations
that cannot be addressed by operands. Table 8-28 provides an overview of the load and transfer
operations.
8-64 EWA 4NEB 812 6120-02


LIR Load the register indirectly
The contents of a memory word are loaded into the specified
register (ACCU 1, 2). The address is in ACCU 1.
TIR Transfer the register indirectly

The contents of the indicated register are transferred to a memory
location. The address is in ACCU 1.
Parameter
0 (for ACCU 1), 2 (for ACCU 2)
TNB Transfer a data field (byte-by-byte)

A memory area is transferred in the program memory as a field.
End address destination area: ACCU 1
End address source area: ACCU 2
T Transfer
A word is transferred to the system data area.
ID Parameter
RS 0 to 255
Loading and Transferring Register Contents

Both accumulators can be addressed as registers. Each register is 16 bits wide. Since the “LIR”
and “TIR” operations transmit data by words, the registers are addressed in pairs.
Loading and transferring register contents are independent of the RLO. The processor goes to
ACCU 1 to get the address of the memory location referenced during data exchange. Conse-
quently, make sure that the desired address is stored in ACCU 1 before this system operation is
processed.
STL Explanation
.
.
L KH 6100 Load the address 6100H into ACCU 1.
LIR 0 Load the information from the memory location with the address 6100H into
ACCU 1.
EWA 4NEB 812 6120-02 8-65

Processing a Field Transfer
A field transfer is processed independently of the RLO. The parameter indicates the length of the
data field (in bytes) that is to be transferred. The field can be up to 255 bytes long.
The address of the source field is in ACCU 2. The address of the destination field is in ACCU 1.
The higher address of each field must be specified because a field transfer takes place by
decrementing. The bytes in the destination field are overwritten during the transfer.
Transfer a 12-byte
data field from EE85
address F0A2H to Destination
address EE90H.
EE90
. .
. . TNB
. .
F097
Source
F0A2
STL Explanation
:L KH F0A2 Load the end address of the source field into ACCU 1.
:L KH EE90 Load the end adress of the destination field into ACCU 1. The
source address is shifted to ACCU 2.
:TNB 12 Transfer the data field to the destination field.
8-66 EWA 4NEB 812 6120-02

Transferring to the System Data Area

Example: Set the scan monitoring time to 100 ms after each mode change from “STOP” to
“RUN”. You can program this time in multiples of 10 ms in system data word 96. The
following function block can be called from OB21, for example.
STL Explanation
FB 11 Block number and type
L KF +10 Load ACCU 1 with the factor 10.
T RS 96 Transfer this value to system data word 96.
BE
! Caution
The TIR, TRS and TNB operations are memory-changing operations with which you can
access the user memory and the system data area. These accesses are not monitored
by the operating system. Improper use of the operations can lead to changes in the
program and to a programmable controller crash.
8.3.3 Arithmetic Operations

An arithmetic operation changes the contents of ACCU 1 by a specified value. The parameter re-
presents this value as a positive or negative decimal number. Table 8-29 shows the essential
features of the “ADD” operation. An example follows the table.
Table 8-29. Overview of the “ADD” Operation

ADD Add a constant
Add byte or word constants.
ID Parameter
BF -128 to +127
KF -32768 to +32767
Processing
An arithmetic operation is executed independently of the RLO. It does not affect the RLO or the
condition codes.
You can subtract by entering a negative parameter.
Even if the result cannot be represented by 16 bits, no carry is made to ACCU 2, i.e., the contents
of ACCU 2 are not changed.
EWA 4NEB 812 6120-02 8-67

Decrement the constant 1020H by 33 L KH 1020 The constant 1020H is loaded into
and store the result in flag word ACCU 1.
FW28. Afterwards add the constant ADD BF -33 The constant -330D is added to
256 to the result and store the sum in the ACCU contents.
flag word FW30. T FW 28 The new ACCU contents (0FFFH)
are stored in flag word FW28.
ADD KF 256 The constant 2560D is added to
the last result.
T FW 30 The new ACCU contents (10FFH)
are stored in flag word FW30.
8.3.4 Other Operations

Table 8-30 provides an overview of the remaining system operations.
Table 8-30. The “TAK” and “STS” Operations

TAK Swap accumulator contents

Swap the contents of ACCU 1 and ACCU 2 regardless of the
RLO. The RLO and the condition codes are not affected.
STS Stop immediately

The PLC goes into the STOP mode regardless of the RLO.
Processing the “STS” Operation

When the “STS” operation is executed, the programmable controller goes into the STOP mode
immediately. Program processing is terminated at this point. The STOP state can only be cancelled
manually (with the mode selector) or with the programmer function “PC START”.
8-68 EWA 4NEB 812 6120-02

8.4 Condition Code Generation

The processor of the programmable controller has the following three condition codes:
• CC 0
• CC 1
• OV (overflow)
The following operations affect the condition codes.

• Comparison operations
• Arithmetic operations
• Shift operations
• Some conversion operations
The state of the condition codes represents a condition for the various jump operations.
Condition Code Generation for Comparison Operations

Execution of comparison operations sets condition codes CC 0 and CC 1 (see Table 8-31). The
overflow condition code is not affected. Comparison operations do affect the RLO. When a
comparison is satisfied, the RLO is 1. This allows you to use the “JC” conditional jump operation
after a comparison operation.
Table 8-31. Condition Code Settings for Comparison Operations

Contents of ACCU 2 as Condition Codes Possible
Compared to Contents Jump Operations
of ACCU 1 CC 1 CC 0 OV
Equal to 0 0 JZ
Less than 0 1 JN, JM

Greater than 1 0 JN, JP
Condition Code Generation for Arithmetic Operations

Execution of arithmetic operations sets all condition codes according to the result of the arithmetic
operation (see Table 8-32).
Table 8-32. Condition Code Settings for Fixed-Point Arithmetic Operations
Result after Condition Codes Possible
Arithmetic Operation Jump Operations
is Executed CC 1 CC 0 OV
< - 32768 1 0 1 JN, JP, JO
- 32768 to - 1 0 1 0 JN, JM
0 0 0 0 JZ
+1 to +32767 1 0 0 JN, JP
> +32767 0 1 1 JN, JM, JO
(-) 65536* 0 0 1 JZ, JO

* This number is the result of the calculation -32768 - 32768
EWA 4NEB 812 6120-02 8-69

Condition Code Generation for Digital Logic Operations

Digital logic operations set CC 0 and CC 1. They do not affect the overflow condition code (see
Table 8-33). The setting depends on the contents of the ACCU after the operation has been pro-
cessed.
Table 8-33. Condition Code Settings for Digital Logic Operations

Contents Condition Codes Possible
of the
Jump Operations
ACCU CC 1 CC 0 OV
Zero (KH = 0000) 0 0 JZ

Not zero 1 0 JN, JP
Condition Code Generation for Shift Operations

Execution of shift operations sets CC 0 and CC 1. It does not affect the overflow condition code
(see Table 8-34). Code setting depends on the state of the last bit shifted out.
Table 8-34. Condition Code Settings for Shift Operations

Value of Condition Codes Possible
the Last Bit Jump Operations
Shifted Out CC 1 CC 0 OV
“0” 0 0 JZ
“1” 1 0 JN, JP
Condition Code Generation for Conversion Operations

The formation of the two's complement (CSW) sets all condition codes (see Table 8-35). The state
of the condition codes is based on the result of the conversion function.
Table 8-35. Condition Code Settings for Conversion Operations

Result after Condition Codes Possible
Arithmetic Operation
Jump Operations
is Executed CC 1 CC 0 OV
- 32768 * 0 1 1 JN, JM, JO
- 32767 to - 1 0 1 0 JN, JM
0 0 0 0 JZ
+1 to +32767 1 0 0 JN, JP
* This number is the result of the conversion of KH = 8000.
8-70 EWA 4NEB 812 6120-02

8.5 Sample Programs
Sections 8.5.1 through 8.5.3 provide a few sample programs that you can enter and test in all three
methods of representation on a programmer.
8.5.1 Momentary-Contact Relay/Edge Evaluation

On each leading edge of the signal at input I 0.0, the AND
condition “A I 0.0 and AN F 64.0” is satisfied; the RLO is “1”.
This sets flags F 64.0 and F 2.0 (“edge flags”).
In the next processing cycle, the AND condition “A I 0.0 and
I 0.0
AN F 64.0” is not satisfied since flag F 64.0 has already been I 0.0
set. F 64.0
Flag 2.0 is reset.
Therefore, flag F 2.0 is “1” for only one program run.
When input I 0.0 is switched off, flag F 64.0 is reset. F 2.0
This resetting prepares the way for evaluation of the next F 2.0
leading edge of the signal at input I 0.0.
STL CSF LAD
A I 0.0
AN F 64.0 I 0.0 & I 0.0 F 64.0 F 2.0 F 64.0
= F 2.0 F 2.0 F 64.0 (#) S
S F 64.0
F 64.0 (#) S I 0.0
AN I 0.0
R F 64.0 R Q
NOP 0 I 0.0 R Q
8.5.2 Binary Scaler/Binary Divider

This section describes how to program a binary scaler.
Example: The binary scaler (output Q 1.0) changes its state each time I 0.0 changes its signal
state from “0” to “1” (leading edge). Therefore, half the input frequency appears at the
output of the flip-flop.
EWA 4NEB 812 6120-02 8-71

Signal states
I 0.0
0 I 0.0
1 Q 1.0
0 Q 1.0
Time
STL CSF LAD
A I 0.0 I 0.0 &

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
I 0.0 F 1.0 F 1.1

AN F 1.0
= F 1.1 F 1.0 F 1.1 ( )
***
A F 1.1 F 1.0
S F 1.0 F 1.1 F 1.0
F 1.1 S
AN I 0.0 S
R F 1.0
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
I 0.0 R Q
NOP 0 I 0.0
***
R Q
A F 1.1
A Q 1.0 F 1.1 &
= F 2.0 F 1.1 Q 1.0 F 2.0
***
Q 1.0 F 2.0 ( )
A F 1.1
AN Q 1.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
AN F 2.0 F 1.1 F 1.1 Q 1.0 F 2.0 Q 1.0

S Q 1.0 &
Q 1.0 S
A F 2.0 Q 1.0
R Q 1.0 F 2.0 S F 2.0
NOP 0
R Q
*** F 2.0 R Q
Note
Output in CSF or LAD is possible only if you enter the segment boundaries “***” when
programming in STL.
8-72 EWA 4NEB 812 6120-02

8.5.3 Clock/Clock-Pulse Generator
This subsection describes how to program a clock-pulse generator.

Example: A clock-pulse generator can be implemented using a self-clocking timer that is followed
in the circuit by a binary scaler. Flag F 2.0 restarts timer T 7 each time it runs down,
i.e., flag F 2.0 is “1” for one cycle each time the timer runs down. The pulses of flag
F 2.0 applied to the binary scaler result in a pulse train with pulse duty factor 1:1 at
output Q 1.0. The period of this pulse train is twice as long as the time value of the
self-clocking timer.
Signal states
1 G F 2.0
0 F 2.0
F 3.0
1
Q 1.0
0
Q 1.0
Time
T T
STL CSF LAD
AN F 2.0
L KT 010.1
F 2.0
SD T 7 T 7 T 7
NOP 0 F 2.0 T 0 T 0
NOP 0
KT 10.1 TV TV BI
NOP 0 BI KT 10.1 DE
A T 7 DE
R Q F 2.0 F 2.0
= F 2.0
*** R Q ( )
Q 1.0
A F 2.0 F 2.0 &
S F 2.0 F 3.0 Q 1.0
AN F 3.0
F 3.0 S
S Q 1.0
A F 2.0
F 2.0 &
A F 3.0 R Q F 2.0 F 3.0
R Q 1.0 F 3.0 R Q
NOP 0 F 3.0
*** F 2.0 &
S F 2.0 Q 1.0
AN F 2.0 F 3.0
Q 1.0
A Q 1.0 S
S F 3.0 F 2.0 &
AN F 2.0 R Q
Q 1.0 F 2.0 Q 1.0
AN Q 1.0 R Q
R F 3.0
NOP 0
EWA 4NEB 812 6120-02 8-73

9 Integrated Blocks and Their Functions
9.1 Assigning Internal Functions to DB1,

for CPU 103 Version 8MA03 and Higher . . . . . . . . . . . . . . . . . . . . 9 - 1
9.1.1 Configuration and Default Settings for DB1 . . . . . . . . . . . . . . . . . . 9 - 1
9.1.2 Setting the Address for the Parameter Error Code in DB1 . . . . . . . . 9 - 2
9.1.3 Assigning Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.4 Rules for Setting Parameters in DB1 . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.1.5 How to Recognize and Correct Parameter Errors . . . . . . . . . . . . . . 9 - 6
9.1.6 Transferring DB1 Parameters to the Programmable Controller . . . . . 9 - 9
9.1.7 Reference Guide for Setting Parameters in DB1 . . . . . . . . . . . . . . . 9 - 10
9.1.8 Defining System Characteristics in DB1 .................... 9 - 11
9.2 Integrated Function Blocks,

9.2.1 Code Converter : B4 - FB240 - .......................... 9 - 12
9.2.2 Code Converter : 16 - FB241 - .......................... 9 - 12
9.2.3 Multiplier : 16 - FB242 - ............................... 9 - 13
9.2.4 Divider : 16 - FB243 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 13
9.2.5 Analog Value Conditioning Modules FB250 and FB251 . . . . . . . . . . 9 - 14
9.3 Integrated Organization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14

9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher . . . . . . . . . . . 9 - 14
9.3.2 Battery Failure OB34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14
9.3.3 OB251 PID Algorithm,
EWA 4NEB 812 6120-02

Figures
9-1 DB1 with Default Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1

9-2 Inputting the Address for the Parameter Error Code . . . . . . . . . . . . . . . . . . 9 - 3
9-3 Parameter Error Codes and Their Meaning . . . . . . . . . . . . . . . . . . . . . . . . 9 - 7
9-4 Erroneous Parameter Assignment in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8
9-5 Inputting the System Data Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
9-6 Calling Up the OB251 PID Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15
9-7 Block Diagram of the PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 16
9-8 Principle of Interval Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 21
9-9 Process Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 22
Tables
9-1 Parameter Blocks and Their IDs ............................... 9 - 2

9-2 Call and Parameter Assignments of FB240 . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
9-6 Legend for the Block Diagram of the PID Controller . . . . . . . . . . . . . . . . . . 9 - 16
9-7 Description of the Control Bits in Control Word ”STEU” ............... 9 - 17
9-8 Structure of the Controller DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 19
EWA 4NEB 812 6120-02

S5-100U Integrated Blocks and Their Functions
9 Integrated Blocks and Their Functions
9.1 Assigning Internal Functions to DB1, for CPU 103 Version 8MA03 and
Higher
You can program the following CPU functions:

• Using the integral real-time clock (see chapter 12)
• Exchanging data via SINEC L1 (see chapter 13)
• Changing polling interval for time-controlled program processing (OB 13) (see chapter 7)
• Assigning system parameters (see section 9.1.3)
• Setting the address for the parameter error code (see section 9.1.2)
To assign parameters to these functions, you must configure data block 1 (DB1).
9.1.1 Configuration and Default Settings for DB1

To make it easier for you to assign parameters, data block 1 is already integrated in the CPU with
default parameters. After performing an overall reset, you can load the default DB1 from the
programmable controller into your programmer and display it on the screen (see Figure 9-1). The
character string “DB1” must remain before the parameter blocks and be followed by at least one
filler (such as a blank space or a comma).
aaaaaaaa
aaaaaaaa
aaaaaaaa
0: KS = 'DB1 SL1: SLN 1 SF ';

12: KS = 'DB2 DW0 EF DB3 DW0 ';
24: KS = ' KBE MB100 KBS MB101 ';
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
36: KS = 'PGN 1 ; #CLP: CF 0 ';

48: KS = 'CLK DB5 DW0 STW ';
60: KS = 'MW102 STP Y SAV Y ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
108: KS = '000000:00:00 # ; SDP: WD';

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
120: KS = ' 500 ; TFB: OB13 100 ';

132: KS = ' ; END ';
Figure 9-1. DB1 with Default Parameters
This preset DB1 has one parameter block for each function. Each parameter block begins with a
block ID (shown in Figure 9-1 in the shaded background). The block ID is followed by a colon. The
individual parameters for each function are contained in these parameter blocks.
Each parameter block begins with a block ID followed by a colon. This colon must be followed by
at least one filler (such as a blank space or a comma). A semicolon must be at the end of each
parameter block with at least one filler between the semicolon and the next block ID.
EWA 4NEB 812 6120-02 9-1

Integrated Blocks and Their Functions S5-100U
The parameter blocks listed in Table 9-1 are used for the S5-100U.
Table 9-1. Parameter Blocks and Their IDs

Block ID Explanation/Default Setting
'DB1 '; Start ID
'SL1: '; SINEC L1: Parameter block for SINEC L1 configuration /

(see chapter 13)
’CLP: ’: Clock-Parameters: Parameter block for integral time clock/

clock function not activated (see chapter 12)
'SDP: '; System-Dependent Parameter: Parameter block for system specifications /

default setting for cycle time monitoring is 500 ms (see section 9.1.8)
'TFB: '; Timer Function Blocks: Parameter block for time-controlled program
processing: OB13 is called up every 100 ms. (see chapter 7)
'ERT: '; Error ReTurn: Address for parameter error code / no default setting (see
section 9.1.2)
'END '; END block ID for DB1
The sequence of the parameters in DB1 is not fixed. A semicolon must be at the end of each
parameter block with at least one filler between the semicolon and the next block ID.
The structure of the following parameter blocks is described here in detail.

• ERT: (Error code position)
• SDP: (System specifications)
The parameter blocks that are not discussed here are explained in the chapters that describe their
functions.
9.1.2 Setting the Address for the Parameter Error Code in DB1
For the following reasons, we recommend that you use this example when you start setting your
parameters:
• Parameter block “ERT:” is the only block with no default parameters in DB1. You must there-
fore enter all the parameters. We will explain the rules for assigning parameters step by step,
so that you can learn the rules quickly.
• The correctly input “ERT:” parameter block makes it easy for you to correct parameter setting
errors; therefore, you should complete this block in DB1 before you change or add other
parameters.
The error parameter block is only important during the start-up phase. You should erase it
during “normal” operation because it takes up a lot of memory space.
9-2 EWA 4NEB 812 6120-02

To help find parameter errors more easily and to help correct them, you can ask the programmable
controller to output error messages in a coded form. All you have to do is to tell the programmable
controller where it should store the error code. Make this input in parameter block “ERT:” of DB1.
The error code can be stored in either of the following locations:

• In flagwords
• In data words in a data block
How to Proceed:
1. Perform an overall reset on the programmable controller.

2. Display DB1 on the programmer.
3. Position the cursor on the E of the “END” ID at the end of the default DB1.
4. Enter the characters that are highlighted in Figure 9-2.
DB1 Explanation
0: KS = 'DB1 SL1: SLN 1 SF ';

12: KS = 'DB2 DW0 EF DB3 DW0 ';
24: KS = ' KBE MB100 KBS MB101 ';
36: KS = 'PGN 1 ; #CLP: CF 0 ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
108: KS = '000000:00:00 # ; SDP: WD';
120: KS = ' 500 ; TFB: OB13 100 '; The parameter error code is stored in flag
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
132: KS = ' ; ERT: ERR MW1 ; END '; word MW1 after start-up.
Figure 9-2. Inputting the Address for the Parameter Error Code
5. Use the following check list to make sure your entries are correct.
- Is the block ID “ERT:” terminated by a colon? ............................
- Is at least 1 filler (a blank space in Figure 9-2) added after the colon? . . . . . . . . . . . .
- Is the parameter name (ERR) entered correctly? . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does at least 1 filler (a blank space) follow the parameter name? . . . . . . . . . . . . . . .
- Is the argument (MW1) entered correctly? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does at least 1 filler (a blank space) follow the argument? . . . . . . . . . . . . . . . . . . . .
- Does a semicolon (;) indicate the block end? . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- Does DB1 end with the end ID “END” followed by a space? ..................
6. Transfer the changed DB1 to the programmable controller.
7. Switch the programmable controller from STOP to RUN.
- The programmable controller accepts the changed DB1.
If you did not store the parameter block “ERT:” in DB1, you can localize the error in the ISTACK if
there was an incorrect parameter setting. However, you will not know what type of error is present.
The same applies if you made an error when you input the parameter block “ERT:”
EWA 4NEB 812 6120-02 9-3

9-4
DB1:
9.1.4
aaaaaaaaaa aaaaaaaaaaaa aaaaaaaa
Note
aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaa
A block end symbol

aaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
DB1 consists of the following:

aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaa

3. Change or expand the parameters.

Changed DB1 parameters are accepted.

9.1.3 Assigning Parameters in DB1

One or more parameters

A parameter block consists of:

2. Position the cursor on the desired parameter block.

A parameter consists of:

Rules for Setting Parameters in DB1
lights up) even after a switch from STOP to RUN.


A start ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A block ID . . . . . . . . . . . . . . . . . . . . . . . . .
One or more parameter blocks . . . . . . . . . . . . . . . . . . . .

..............
A parameter name . . . . . . . . . . .
One or more arguments . . . . . . .

..............................
(for an explanation and possible parameter values see section 9.1.7)
A block end ID . . . . . . . . . . . . . . . . . . . . . . . . .
e.g.:
e.g.:
e.g.:
e.g.:
DB1
e.g.:
aaaaaaaaaa aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
1. Display the default DB1, with its parameter block “ERT:” on the programmer.
: END
STW
CLP:
aaaaaaaaaa aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
FW 102
: ; (Semicolon)
STW FW 102
As discussed in section 9.1.2, you use the following steps to change or expand the preset values of
If the CPU recognizes an error in DB1, then it remains in the STOP mode (red LED
CLP:STW FW102
aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaa aaaaa aaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaa
EWA 4NEB 812 6120-02

S5-100U
aaaaa aaaaaaaaaaaa
In the following section are the rules for changing or expanding entire parameter blocks. Follow
these steps or the CPU will not understand what you have entered.
1. Enter the start ID “DB1”, followed by a filler.

- DB1 must begin with the start ID “DB1”. Do not separate the three characters from each
other. After the start ID, there must be at least one filler. Use a blank space or a comma
as a filler.
2. Enter the block ID for the parameter block, followed by a filler.

- The start ID and filler are followed by the block ID for the parameter block. The sequence
of the parameter blocks in DB1 is random. The block ID identifies a block and its
corresponding parameter. The block ID “SL1”, for example, stands for the SINEC-L1
parameter. You must enter a colon immediately after the block ID. If the colon is missing,
then the CPU skips this block and displays an error message. You must add at least one
filler after the colon of a block ID.
3. Enter the parameter name, followed by a filler.

- The parameter name comes next. Parameter names are names for single parameters within
a parameter block. Within a block, the first four characters of a parameter name must be
different from each other. After the parameter name, you must add at least one filler.
4. Enter the argument that is attached to the parameter name, followed by a filler.
- At least one argument is attached to each parameter name. An argument is either a
number or a STEP 5 operand that you must enter. If several arguments belong to a
parameter name, then every argument must be followed by at least one filler (even the last
one).
5. Enter a semicolon (; ) to identify the block end, followed by a filler.

- After the semicolon, you must enter at least one filler. Leaving out the semicolon leads to
misinterpretation in the CPU.
6. Enter additional parameter blocks after the semicolon.

- (Use steps 2 through 5 to create additional parameter blocks.)
7. Enter the end ID “END”.

- This identifies the end of DB1. If you forget to enter an end ID, this leads to errors in the
CPU.
EWA 4NEB 812 6120-02 9-5

The preceding steps present the minimal requirements for setting the parameters. Beyond that,
there are additional rules that make it easier for you to assign parameters.
For example:
• You have the ability to add comments.
• You can expand the German mnemonics used as parameter names by using plain English text.
Comments can be added anywhere a filler is allowed. The comment symbol is the pound (#) sign.
The comment symbol must be placed at the beginning and at the end of your comment. The text
between two comment symbols may not contain an additional #.
Example: #Comment# . At least one filler must follow the comment.
In order to make it easier to read parameter names, you can add as many characters as you wish if
you add an underscore (_) after the abbreviated parameter name.
Example: SF becomes SF_SENDMAILBOX .
At the end of the input, you must add at least one filler.
There is a rule of thumb that will help you check DB1. You should include at least one filler in the
following instances:
• After the start ID
• Before and after the block ID, parameter name, argument, and semicolon
9.1.5 How to Recognize and Correct Parameter Errors
If an error occurs while assigning parameters and the programmable controller does not go to the
“RUN” mode, you have two possibilities for recognizing errors:
• By using a parameter error code
• By using the analysis function “ISTACK”
Both possibilities are described below.
Scanning the Parameter Error Code

If you have entered a start address for the parameter error code in parameter block “ERT:” of DB1
(see section 9.1.2), then you can retrieve the cause of the error, and the error location information
at this address.
The entire error code occupies 10 data words or 20 flag bytes. In the following examples and
tables, we assume that the error code is stored in a data block starting with data word 0. The error
code occupies DW0 through DW9. In the “Flag” operand area, this corresponds to FW0 through
FW19.
9-6 EWA 4NEB 812 6120-02

END
No error
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
S5-100U
Example:
Not defined
Not defined
10:
9:
8:
7:
6:
5:
4:
3:
2:
1:
0:
in an argument
Error in the date

Range exceeded
DB is not present
EWA 4NEB 812 6120-02

Error in inputting time
Syntax error - block ID
Irregular time format in

Error inputting weekday
Syntax error - argument
Not enough space in DB

Syntax error - parameter
Start or end ID is missing
Cause of the error

KH=
KH=
KH=
KH=
KH=
KH=
KH=
KH=
KH=
KH=
Comment not closed off correctly

(which error occurred?)
parameter blocks (24h/12h mode)

Parameter combination is not allowed

Before END; semicolon missing in front of

aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
aaaaaaaaaa
DL
left)
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Word
(Data
aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 6 0 3
CO DE
.
.
.
aaaaaaaa aaaa
99
11
09
06
03
02
01
00
F0
FF
DR
right)
Word
(Data
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
SL1:
TFB:
CLP:
ERT:
SDP:
to any block
to any block
SINEC L1
Error return
Figure 9-3. Parameter Error Codes and Their Meaning

Screen display with
parameter error codes
occur?)
Clock parameter
Timer function block

Error cannot be assigned
Location of error
Error can not be assigned

System data parameter
controller remains in the STOP mode. You suspect that the reason for this is a
parameter error. To find the error, display DB3 on the programmer. The entire
parameters to the programmable controller, you find out that the programmable
the screen display is a complete list of parameter error codes and their meanings.
continue to set parameters in DB1. While attempting to transfer the changed DB1
contents of DB3 appear on the screen. DW0 through DW9 contain the code for the
set in DB1 have already been transferred to the programmable controller. Then you
You entered the start address DB3 DW0 in parameter block “ERT:”. The parameters
parameter error. In the following figure, you see how your screen could look. Below
(in which parameter block did the error

9-7
•
•
9-8
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
132:
120:
108:
96:
84:
72:
60:
48:
36:
24:
12:
0:
000CH
addresses.
KS
KS
KS
KS
KS
KS
KS
KS
KS
KS
KS
KS
byte address
Hexadecimal
=
= 'OHE N
= 'MW102
12D
= ' ; END
= '12:10:00
= 'DB2 DW0
Decimal
The relative (error) address:

= 'CLK DB5 DW0
The absolute (error) address:

byte address
= '01.04. 13:00:00
= 'DB1 SL1: SLN 40
The error is due to a range violation.

EF DB3
TIS 4
STW
= 'PGN 1 ; #CLP: CF 0
the programmer displays a DB in words.

= ' KBE MB100 KBS MB101
Locating Parameter Errors in “ISTACK”

SF ';
';
= ' 500 ; TFB: OB13 100 ';
= '000000:00:00 # ; SDP: WD';
OHS ';
';
SET 4 01.04.92 ';
STP Y SAV Y ';
';
';
';
DW0 ';
12D
82F2H
000CH
:
The error causes ISTACK to display the following addresses.
2D =
6D
(relative SAC)
(absolute SAC)
contains the absolute error address as well as the relative error address.
characters (2 bytes).
Decimal
Figure 9-4. Erroneous Parameter Assignment in DB1
word address
Example: Your inputs into DB1 are as follows. The position shaded contains an error.
incorrect input or in front of the address that contains the incorrect input. These are byte
character that can be entered for that

represent the word address for the first
If the CPU recognizes an error in DB1 in the initial start-up, then the CPU remains in the STOP
The information displayed in the chart above shows that the error occurred after address 0 and
respective line. Each word consists of two
mode and stores a message in “ISTACK” describing where the error happened. The “ISTACK”
The STEP Address Counter (SAC) in the ISTACK points either to the address that contains the
So that you can locate the error in DB1 exactly, you must convert the relative byte address that is
before address 12. In Figure 9-4, argument 40 occupies address 6; the “40” is an incorrect entry.
displayed in hexadecimal format into a decimal word address. Decimal format is required because
The decimal numbers in front of each input line
EWA 4NEB 812 6120-02

S5-100U
9.1.6 Transferring DB1 Parameters to the Programmable Controller

Unlike other data blocks, DB1 is processed only one time. This occurs when a cold restart is
performed on the programmable controller. This was done so that DB1 could handle certain special
functions.
One such special function is the assignment of parameters in the programmable controller with the
help of DB1. Setting parameters means that you enter parameters in DB1 for those internal
functions that your programmable controller should work with.
The programmable controller's operating system accepts these inputs into DB1 only when there is a
cold restart. You must perform a cold restart anytime you make changes to DB1. You can perform a
cold restart by switching from Power OFF to Power ON or from STOP to RUN.
The programmable controller accepts the parameters from DB1 and stores them in the system data
area.
Note
The CPU remains in the STOP mode if a parameter assignment error is found during
start-up. The red LED lights up on the operator panel and ISTACK displays a DB1
addressing error.
EWA 4NEB 812 6120-02 9-9

9.1.7 Reference Guide for Setting Parameters in DB1
Parameter Argument Meaning
Block ID: SL1: SINEC L1 (SL1)

SLN p Slave number
SF DBx DWy Location of Send Mailbox
EF DBxDWy Location of Receive Mailbox
KBE MBy Location of Coordination Byte “Receive”
KBS MBy Location of Coordination Byte “Send”
PGN p Programmer bus number
p=1 to 3 x=2 to 255 y=0 to 255
Block ID:SDP: System-Dependent-Parameter (SDP)
WD p Number of timers being processed(Watch-Dog-Timer)

p=1 to 2550
Block ID: TFB: Timer-Funktions-Baustein (TFB)
OB13 p Intervals (ms) at which OB13 is called up and is
processed
p=0 to 655350 (State in 10-ms steps)
Block ID: CLP: ClockParameters (CP)
CF p Inputting the correction factor (Correction Factor)

CLK DBxDWy,MWz,EWv Location of the clock data (CLocK Data)
or AWv
STW DBxDWy,MWz,EWv Location of the status word (STatus Word)
or AWv
STP J/Y/N Updating the clock during STOP (SToP)
SAV J/Y/N Saving the clock time after the last change from RUN
to STOP or Power OFF (SAVe)
OHE J/Y/N Enabling the operating hours counter
(Operation Hour counter Enable)
SET wd dd.mm.jj Setting the clock time and date
hh:mn:ss1 AM/PM2
TIS wd dd.mm. Setting the prompting time (TImer Set)
hh:mn:ss1 AM/PM2
OHS hhhhhh:mn:ss1 Setting the operating hours counter
(Operation Hour counter Set)
wd =1 to 7 (weekday = Sun..Sat) p=– 400 to 400
dd =01 to 31 (day) v=0 to 126
mm =01 to 12 (month) x=2 to 255
yy =0 to 99 (year) y=0 to 255
hh =00 to 23 (hours) z=0 to 254
mn =00 to 59 (minutes) j/J=ja(yes)
ss =00 to 59 (seconds) y/Y=yes
hhhhhh =0 to 999999 (hours) n/N=no
1 If an argument such as seconds, for example, is not to be entered, input XX. The clock continues to run
with the updated data. The TIS parameter block does not acknowledge this argument..
2 If you input AM or PM after the clock time, the clock runs in the 12-hour mode. If you omit this
argument, the clock runs in the 24-hour mode. You must use the same time mode in the SET and TIS
parameter blocks.
9-10 EWA 4NEB 812 6120-02

9.1.8 Defining System Characteristics in DB1

Each cyclical program processing triggers the beginning of a monitoring period. If the cycle trigger
is not retriggered during the monitoring period, the programmable controller is forced into the STOP
mode and disables the output modules. The default for the monitoring time is set to 500 ms in
DB1. You can increase the cycle time monitoring in the parameter block SDP.
Example: You wish to increase the monitoring time to 700 ms since your user program is very
large.
How to Proceed:
1. Display DB1 on the programmer.
2. Change the parameter block “SDP” as shown in Figure 9.5.
- Position the cursor on the arguments for the parameter
- Overwrite the arguments
0: KS = 'DB1 SL1: SLN 1 SF ';

12: KS = 'DB2 DW0 EF DB3 DW0 ';
24: KS = ' KBE MB100 KBS MB101 ';
36: KS = 'PGN 1 ; #CLP: CF 0 ';
72: KS = 'OHE N SET 4 01.04.92 ';
84: KS = '12:10:00 TIS 4 ';
96: KS = '01.04. 13:00:00 OHS ';
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
108: KS = '000000:00:00 # ; SDP: WD';

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
120: KS = ' 700 ; TFB: OB13 100 ';

132: KS = ' ; END ';
Figure 9.5. Inputting the System Data Parameter

4. Switch the programmable controller from STOP to RUN. The programmable controller now
accepts the changed parameters.
You can also set the cycle monitoring time in OB31 (see section 9.3.1).
9.2 Integrated Function Blocks, for CPU 102 Version 8MA02 and Higher
Some standard function blocks are integrated in your S5-100U. You can call up these blocks in
your control program with the commands “JU FB” or “JC FB x”. The character “x” stands for the
block number.
Overview:
Block No. FB240 FB241 FB242 FB243 FB250 FB251

Block name COD:B4 COD:16 MUL:16 DIV:16 RLG:AI RLG:AQ
Call length 5 6 7 10 10 9
(in words)
Processing time
(in ms) < 0.6 < 1.0 < 0.9 < 2.1 2.4 4.8
EWA 4NEB 812 6120-02 9-11

9.2.1 Code Converter : B4 - FB240 -

Use function block FB240 to convert a number in BCD (4 tetrads) with sign to a fixed-point binary
number (16 bits).
You must change a two-tetrad number to a four-tetrad number before you convert it.
• If a tetrad is not in the BCD defined range, then FB240 displays the value “0”. An error bit
message does not follow.
Table 9-2. Call and Parameter Assignments of FB240
Parameter Meaning Type Assignment STL
BCD BCD number IW 0 to 9999 : JU FB240

-
SBCD Sign of the I BI “1” for “-” NAME : COD:B4
BCD number “0” for “+” BCD :
SBCD :
DUAL Fixed-point QW 16 bits “0” DUAL :
number (KF) or “1”
9.2.2 Code Converter : 16 - FB241-

Use function block FB 241 to convert a fixed-point binary number (16 bits) to a number in BCD code
with additional consideration of the sign. An eight-bit binary number must be transferred to a 16-bit
word before conversion.
DUAL Binary number I W -32768 to+32767

: JU FB241
SBCD Sign of the BCD I BI “1” for “-” NAME : COD:16
number “0” for “+” DUAL :
SBCD :
BCD2 BCD number 4th and Q BY 2 tetrads BCD2 :
5th tetrads BCD1 :
BCD1 BCD number tetrads QW 4 tetrads

0 to 3
9-12 EWA 4NEB 812 6120-02

9.2.3 Multiplier : 16 - FB242 -

Use function block FB 242 to multiply one fixed-point binary number (16 bits) by another. The pro-
duct is represented by two fixed-point binary numbers (16 bits each). The result is also scanned for
zero. An eight-bit number must be transferred to a 16-bit word prior to multiplication.
Z1 Multiplier I W -32768 to+32767

: JU FB242
Z2 Multiplicand I W -32768 to+32767 NAME : MUL:16
Z1 :
Z3=0 Scan for zero Q BI “0” : product is zero Z2 :
Z3=0 :
Z32 Product high-word QW 16 Bits
Z32 :
Z31 Product low-word QW 16 Bits Z31 :
9.2.4 Divider : 16 - FB243 -
Use function block FB 243 to divide one fixed-point binary number (16 bits) by another. The result
(quotient and remainder) is represented by two fixed-point binary numbers (16 bits each).
The divisor and the result are also scanned for zero. An eight-bit number must be transferred to a
16-bit word prior to division.
Parameter Explanation Type Assignment STL
Z1 Dividend IW -32768 to+32767

: JU FB243
Z2 Divisor IW -32768 to+32767 NAME : DIV:16
Z1 :
OV Overflow bit Q BI “1” : overflow Z2 :
OV :
FEH Q BI “1” : division by zero
FEH :
Z3=0 Scan for zero Q BI “0”: quotient is zero Z3=0 :
Z4=0 :
Z4=0 Scan for zero Q BI “0”: remainder is zero Z3 :
Z4 :
Z3 Quotient QW 16 bits
Z4 Remainder QW 16 bits
EWA 4NEB 812 6120-02 9-13

9.2.5 Analog Value Conditioning Modules FB250 and FB251

Function block FB250 reads in an analog value from an analog input module and outputs a value XA
in the scale range specified by the user.
Function block FB251 allows you to output analog values to analog output modules. Values from the
range between the “UGR” (lower limit) parameters and the “OGR” (upper limit) parameters are
converted to the nominal range of the selected module.
You will find more information on the following topics in section 11.6:
• Calling up and setting parameters in FB250.
• Calling up and setting parameters in FB251.
• An example of analog value processing with FB250 and FB251.
9.3 Integrated Organization Blocks
9.3.1 Scan Time Triggering OB31, for CPU 103 and Higher
A scan time monitor monitors the program scan time. If program scanning takes longer than the
specified scan monitoring time, the CPU goes into the STOP mode. This can happen when one of
the following errors occurs:
• The control program is too long.
• The program enters a continuous loop.
You can retrigger the scan time monitor at any point in the control program by calling up OB31.
Calling up this block restarts the scan time monitor.
Call up OB31
• Prerequisite: SYSTEM COMMANDS “YES” has been specified on the programmer.
• JU OB31 can be programmed at any point in the control program.
Programming
One statement in OB31 is sufficient, e.g. “BE” to make the retriggering effective. Other
statements are also possible.
9.3.2 Battery Failure OB34
The CPU constantly checks the status of the battery in the power supply. If a battery fails (BAU),
OB34 is processed before every cycle until the battery is replaced. You can program the reaction of
the programmable controller to battery failure in OB34. If OB34 is not programmed, there is no
reaction.
9-14 EWA 4NEB 812 6120-02

9.3.3 OB251 PID Algorithm, for CPU 103 Version 8MA02 and Higher
A PID algorithm is integrated in the operating system of the S5-100U. OB251 helps you use this
algorithm to meet your needs.
Before calling up OB251, you must first open a data block called the controller DB. It contains the
controller parameters and other controller specific data. The PID algorithm must be called up peri-
odically to generate the manipulated variable. The more closely the scan time is maintained, the
more accurately the controller fulfills its task. The control parameters specified in the controller DB
must be adapted to the scan time.
You should always call OB251 from the time OB (OB13). You can set time OBs at a call up interval
ranging between 10 ms and 655,350 ms. The PID algorithm requires no more than 1.7 ms to
process.
OB13 DBN
Time-Controlled Controller
Processing Data Block
C DB N OB251 DW 1
JU OB 251 PID Control .
. Algorithm .
. .
. .
. .
. .
BE DW 49
Figure 9-6. Calling Up the OB251 PID Algorithm
The continuous action controller is designed for controlled systems such as those present in
process engineering for controlling pressure, temperature, or flow rate.
The “R” variable sets the proportional element of the PID controller. If proportional action is
required, most controller designs use the value R = 1.
The individual Proportional action, Integral action, and Derivative action elements can be deactivated
via their parameters (R, TI, and TD) by presetting the pertinent data words to zero. This enables
you to implement all required controller structures without difficulty, e.g., PI, PD, or PID controllers.
You can forward the system deviation XW or, using the XZ input, any disturbance variable or the
inverted actual value X to the derivative action element. Specify a negative K value for a reverse
acting controller.
When the manipulated information (dY or Y) is at a limit, the integral action component is
automatically deactivated in order not to impair the dynamic response of the controller.
The switch settings in the block diagram are implemented by setting the respective bits in control
word “STEU”.
EWA 4NEB 812 6120-02 9-15

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Z STEU BGOG STEU

Bit 5 Bit 2
aaaaaaaa
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1 0
0
R Zk-Zk-1
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aaa
Y OG
Sum-
ming
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unit
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aaa
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- + + dY + 0 +
X TI K
Limiter
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aaa
XW + + + 1 + 0 YA,
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0 1 dY dYA
0
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aaa
TD 1
UG
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XZ 1 Manual 0
function
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STEU STEU STEU STEU

Bit 1 YH, dYH Bit 0 Bit 3 Bit 4 BGUG
Figure 9-7. Block Diagram of the PID Controller
Table 9-6. Legend for the Block Diagram of the PID Controller
Designation Explanation
K Proportional coefficient: K>0 direct acting
K<0 reverse acting
R R parameter (usually 1000)
TA Scan time
TN Integral-action time
TV Derivative-action time
TI Constant TI TI=Scan time TA/Integral action time TN
TD Constant TD TD=Derivative action time TV/Scan time TA
W Setpoint
STEU Control word
YH, dYH Output value: YH Control Word Bit 3=0
dYH Control Word Bit 3=1
Z Disturbance variable
XW System deviation
X Actual value
XZ Substitute value for system deviation
Y, dY Manipulated variable, manipulated increments
BGOG Upper limit of the manipulated variable
BGUG Lower limit of the manipulated variable
YA, dYA Output word : YA Control Word Bit 3=1
dYA Control Word Bit 3=0
9-16 EWA 4NEB 812 6120-02

Table 9-7. Description of the Control Bits in Control Word “STEU”
Control Signal
Name Description
Bit State
0 AUTO 0 Manual mode

The following variables are updated in Manual mode:
1) XK, XWK-1 and PWK-1
2) XZK, XZK-1 and PZK-1, when STEU bit 1=1
3) ZK and ZK-1, when STEU bit 5=0
Variable dDK-1 is set to 0: The algorithm is not computed.
1 Automatic mode
1 XZ EIN 0 XWk is forwarded to the derivative action element. The XZ input

1 is ignored. A variable other than XWk is forwarded to the derivative
action element .
2 REG AUS 0 Normal controller processing

1 When the controller is called up (OB251), all variables (DW18 to
DW 48 ) with the exception of K, R, TI, TD, BGOG, BGUG, YHk
and Wk are reset in the controller DB. The controller is
deactivated.
3 GESCHW 0 Positioning algorithm

1 Correction rate algorithm
4 HANDART 0 When GESCHW=0:

Following the transfer to Manual mode, the specified manipulated
variable value YA is adjusted exponentially to the manual value in
four sampling steps. Additional manual values are then forwarded
immediately to the controller output.
When GESCHW=1:
The manual values are forwarded immediately to the controller
output. The limiting values are in force in Manual mode.
1 When GESCHW=0:
The manipulated variable last output is retained.
When GESCHW=1:
Correction increment dYK is set to zero.
5 NO Z 0 With feedforward control

1 No feedforward control
6 and 7 - These bits are not assigned.
8 to 15 - The PID algorithm uses these bits as auxiliary flags.
The control program can be supplied with fixed values or parameters. Parameters are input via the
assigned data words. The controller is based on a PID algorithm. Its output signal can be either a
manipulated variable (positioning algorithm) or a manipulated variable modification (correction rate
algorithm).
EWA 4NEB 812 6120-02 9-17

Correction Rate Algorithm

The relevant correction increment dYk is computed at instant t= k • TA according to the following
formula:
• Without feedforward control (D11.5=1); XW is forwarded to the differentiator (D11.1=0)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XWk - 2XWk-1 + XWk-2) + dDk-1)]
= K (dPWkR + dIk + dDk)
• With feedforward control (D11.5=0); XW is forwarded to the differentiator (D11.1=0)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XWk - 2XWk-1 + XWk-2) + dDk-1)]+(Zk-Zk-1)
= K (dPWkR + dIk + dDk)+dZk
• Without feedforward control (D11.5=1); XZ is forwarded to the differentiator (D11.1=1)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XZk - 2XZk-1 + XZk-2) + dDk-1)]
= K (dPWkR + dIk + dDk)
• With feedforward control (D11.5=0); XZ is forwarded to the differentiator (D11.1=1)

dYk = K[(XWk - XWk-1) R+TI • XWk+ (TD (XZk - 2XZk-1 + XZk-2) + dDk-1)]+(Zk-Zk-1)
= K (dPWkR + dIk + dDk)+dZk
P element I element D element Z element k: kth element
When XWk is applied: XWk = W k - Xk

PWk = XWk - XWk-1
QWk = PWk - PWk-1
= XWk-2XWk-1+XWk-2
When XZ is applied: PZk = XZk - XZk-1

QZk = PZk - PZk-1
= XZk-2XZk-1+XZk-2
The result is: dPWk = (XWk- XWk-1)R

dIk = TI•XWk
dDk = (TD•QWk+dDk-1) when XW is applied
= (TD•QZk+dDk-1) when XZ is applied
dZk = Zk - Zk-1
Positioning Algorithm
The formula used to compute the correction rate algorithm is also used to compute the positioning
algorithm.
In contrast to the correction rate algorithm, however, the sum of all correction increments computed
(in DW 48), rather than the correction increment dYk is output at sampling instant tk.
9-18 EWA 4NEB 812 6120-02

At instant tk , manipulated variable Yk is computed as follows:

m=k
Yk= dYm
m=0
Initializing the PID Algorithm

OB251's interface to its environment is the controller DB. All data needed to compute the next
manipulated variable value is stored in this DB. Each controller has its own controller data block.
The controller-specific data are initialized in a data block that must comprise at least 49 data words.
The CPU goes to STOP with a transfer error (TRAF) if no DB is open or if the DB is too short.
! Caution
Make sure that the right controller DB is open before calling control algorithm OB251.
Table 9-8. Structure of the Controller DB
Data Word Name Comments
1 K Proportional coefficient (-32 768 to + 32 767) for controllers

without a derivative-action element
Proportional coefficient (- 1500 to +1500) for controllers with a
derivative-action element1
K is greater than zero when the control is direct acting, and less
than zero when the control is reverse acting; the specified value is
multiplied by a factor of 0.001.
3 R R parameter (- 32 768 to + 32 767) for controllers without

aderivative-action element
R parameter (- 1500 to + 1500) for controllers with a derivative-
action element1
Normally 1 for controllers with P element; the specified value is
multiplied with a factor of 0.0001
5 TI Constant TI (0 to 9999)
Sampling interval TA
TI=
Integral-action time
The specified value is multiplied by a factor of 0.001
3 Constant TD (0 to 999)
Derivative-action time TV
TD=
Sampling interval TA
9 W Setpoint (- 2047 to +2047)

11 STEU Control word (bit pattern)
12 YH Value for Manual operation (- 2047 to +2047)

14 BGOG Upper limit value (- 2047 to +2047)
16 BGUG Lower limit value (- 2047 to +2047)
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1 It is possible to have larger gains, if sudden incremental changes to the system deviation are small
enough. This is the reason you have to divide larger deviations into smaller ones such as adding
the setpoint via a ramp function.
EWA 4NEB 812 6120-02 9-19

Table 9-8. Structure of the Controller DB (continued)
Data
Name Comments
Word
22 X Actual value (- 2047 to +2047)
24 Z Disturbance variable (- 2047 to +2047)
29 XZ Derivative time (- 2047 to +2047)
48 YA Output variable (- 2047 to +2047)
All parameters (with the exception of the control word STEU) must be specified as 16-bit fixed point
numbers.
! Caution
The PID algorithm uses the data words that are not listed in Table 9-8 as auxiliary flags.
9-20 EWA 4NEB 812 6120-02

Initialization and Call Up of the PID Controller in a STEP 5 Program

Several different PID controllers can be implemented by calling up OB251 repeatedly. A data block
must be initialized prior to each OB251 call up. These DBs serve as data interface between the
controllers and the user.
Note
Important controller data are stored in the high-order byte of control word DW11 (DL11).
Therefore make sure that only T DR 11/SU D11.0 to D11.7 or RU D 11.0 to D11.7
operations are used to modify user-specific bits in the control word.
Selecting the Sampling Interval

In order to be able to use the known analog method of consideration for digital control loops, do not
select a sampling interval that is too large.
Experience has shown that a TA sampling interval of approximately 1/10 of the time constant
TRK, dom* produces a control result comparable to the equivalent analog result. Dominant system
time constant TRK, dom determines the step response of the closed control loop.
TA = 1/10 • TRK, dom
In order to ensure the constancy of the sampling interval, OB251 must always be called up in the
service routine for time interrupts (OB13).
x = Control variable
x
t = Time
TA = Sampling interval
TRK,dom TRK,dom= Dominant system
time constant of
the closed control
loop
xd w = Reference
variable / Setpoint
xd = Control deviation
w
t
aaaaaaaa
aaaaaaaa
TA
Figure 9-8. Principle of Interval Sampling
* TRK, dom = dominant system time constant of the closed control loop
EWA 4NEB 812 6120-02 9-21

Example for the Use of the PID Controller Algorithm:

A PID controller is supposed to keep an annealing furnace at a constant temperature.
The temperature setpoint is entered via a potentiometer.
The setpoints and actual values are acquired using an analog input module and forwarded to the
controller. The computed manipulated variable is then output via an analog output module.
The controller mode is set in input byte 0 (see control word DW11 in the controller DB).
You must use the well-known controller design procedure to determine how to tune the controller
for each controlled system.
IB32 Control byte (DR11) Manipulated

W PID Y variable
+ Channel0 Channel 0
X control
Channel1 algorithm
OB251 with S5-100U
controller DB
(call in OB13)
Setpoint
adjuster
Analog input module Analog output module
(e.g. 6ES5 460) (e.g. 6ES5 470)
Controlled
Actual system
value
= Temperature sensor
=
Annealing furnace Final control
Transducer element
Fuel gas flow
Figure 9-9. Process Schematic
The analog signals of the setpoint and actual values are converted into corresponding digital values
in each sampling interval (set in OB13). OB251 uses these values to compute the new digital
manipulated variable, from which, in turn, the analog output module generates a corresponding
analog signal. This signal is then forwarded to the controlled system.
9-22 EWA 4NEB 812 6120-02

Calling the Controller in the Program:
OB 13 STL Description
:
: JU FB 10 PROCESS CONTROLLER
NAME : CONTROLLER 1
: THE CONTROLLER'S SAMPLING INTERVAL
: DEPENDS ON THE TIME BASE USED
: TO CALL OB13 (SET IN DB1).
: THE DECODING TIME OF THE ONBOARD
: ANALOG INPUTS MUST BE TAKEN
: INTO ACCOUNT WHEN SELECTING
THE SAMPLING INTERVAL.
:
:
: BE
EWA 4NEB 812 6120-02 9-23

FB10 STL Description

NAME :CONTROLLER 1
:
:C DB 30 SELECT CONTROLLER'S DB
:
: **********************************
: READ CONTROLLER'S CONTROL BITS
: **********************************
:
:L PY 0 READ CONTROLLER'S
:T FY 10 CONTROL BITS
:T DR 11 AND STORE IN DR11
: NOTE CAREFULLY:
: DR11 CONTAINS IMPORTANT CONTROL
: DATA FOR OB251
: THE CONTROL BITS MUST
: THEREFORE BE TRANSFERRED WITH
: T DR11 TO PREVENT
: CORRUPTING DL11
:
: ********************************
: READ ACTUAL VALUE AND SETPOINT
: ********************************
:
:A F 12.0 FLAG 0 (FOR UNUSED FUNCTIONS
:R F 12.0 IN FB 250)
: AN F 12.1 FLAG 1
:S F 12.1
:
: JU FB250 READ ACTUAL VALUE
NAME : RLG: AI
BG : KF +8 MODULE ADDRESS
KNKT : KY 0,6 CHANNEL NO. 0, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR ACTUAL VALUE
UGR : KF - 2047 LOWER LIMIT FOR ACTUAL VALUE
EINZ : F 12.0 NO SELECTIVE SAMPLING
XA : DW 22 STORE SCALED ACTUAL VAL. IN CONTR. DB
FB : F 12.2 ERROR BIT
BU : F 12.3 RANGE VIOLATION
:
9-24 EWA 4NEB 812 6120-02

FB10 (continued) STL Explanation
:
: JU FB250 READ SETPOINT
NAME : RLG: AI
KNKT : KY 1,6 CHANNEL NO. 1, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR SETPOINT
UGR : KF - 2047 LOWER LIMIT FOR SETPOINT
EINZ : F 12.0 NO SELECTIVE SAMPLING
XA : DW 9 STORE SCALED SETPOINT IN CONTR. DB
FB : F 13.1 ERROR BIT
BU : F 13.2 RANGE VIOLATION
:
:A F 10.0 IN MANUAL MODE, THE SETPOINT IS
: JC =WEIT SET TO THE ACTUAL VALUE TO FORCE
:L DW 22 THE CONTROLLER TO REACT
:T DW 9 TO A SYSTEM DEVIATION, IF ANY,
: WITH A P STEP
: ON TRANSFER
: TO AUTOMATIC
: MODE
WEIT :
: ********************
: JU OB251 CALL CONTROLLER
: ********************
:
: **********************************
: OUTPUT MANIPULATED VALUE
: **********************************
: JU FB251
NAME : RLG:AQ
XE : DW 48
KNKT : KY 0,1 CHANNEL 0, FIXED-POINT BIPOLAR
OGR : KF +2047 UPPER LIMIT FOR ACTUATING SIGNAL
UGR : KF - 2047 LOWER LIMIT FOR ACTUATING SIGNAL
FEH : F 13.5 ERROR BIT WHEN LIMITING VAL. DEFINED
BU : F 13.6 MANIPULATED VARIABLE Y TO ANALOG
: OUTPUT
: BE RANGE VIOLATION
EWA 4NEB 812 6120-02 9-25

DB 30 STL Explanation
0: KH = 0000;
1: KF = +01000; K PARAMETER (HERE=1), FACTOR 0.001
2: KH = 0000; (VALUE RANGE: - 32768 TO 32767)
3: KF = +01000; R PARAMETER (HERE=1), FACTOR 0.001
4: KH = 0000; (VALUE RANGE: - 32768 TO 32767)
5: KF = +00010; TI=TA/TN (HERE=0.01), FACTOR 0.001
6: KH = 0000; (VALUE RANGE: 0 TO 9999)
7: KF = +00010; TD=TV/TA (HERE=10), FACTOR 1
8: KH = 0000; (VALUE RANGE: 0 TO 999)
9: KF = +00000; SETPOINT W, FACTOR 1
10: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
11: KM = 00000000 00100000; CONTROL WORD
12: KF = +00500; MANUAL VALUE YH, FACTOR 1
13: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
14: KF = +02000; UPPER CONT. LIMIT BGOG, FACTOR 1
15: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
16: KF = -02000; LOWER CONT. LIMIT BGUG, FACTOR 1
17: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
18: KH = 0000;
19: KH = 0000;
20: KH = 0000;
21: KH = 0000;
22: KF = +00000; ACTUAL VALUE X, FACTOR 1
23: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
24: KF = +00000; DISTURBANCE VARIABLE Z, FACTOR 1
25: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
26: KH = 0000;
27: KH = 0000;
28: KH = 0000;
29: KF = +00000; FEEDFORWARD XZ FOR DIFF.,
30: KH = 0000; FACTOR 1, (- 2047 TO 2047)
31: KH = 0000;
32: KH = 0000;
33: KH = 0000;
34: KH = 0000;
35: KH = 0000;
36: KH = 0000;
37: KH = 0000;
38: KH = 0000;
39: KH = 0000;
40: KH = 0000;
41: KH = 0000;
42: KH = 0000;
43: KH = 0000;
44: KH = 0000;
45: KH = 0000;
46: KH = 0000;
47: KH = 0000;
48: KF = +00000; CONTROLLER OUTPUT Y, FACTOR 1
49: KH = 0000; (VALUE RANGE: - 2047 TO 2047)
50:
9-26 EWA 4NEB 812 6120-02

10 Interrupt Processing, for CPU 103 Version 8MA02 and Higher
10.1 Interrupt Processing with OB2, for CPU 103

Version 8MA02 and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10.2 Calculating Interrupt Reaction Times . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
EWA 4NEB 812 6120-02

Figures
10-1 Possible Configuration of the Programmable Controller

with Bus Units Having Interrupt Capability . . . . . . . . . . . . . . . . . . . . . . . . 10 - 1
10-2 Program Interruptions by Process Interrupts . . . . . . . . . . . . . . . . . . . . . . . 10 - 2
10-3 Accessing the Process Image Tables from OB2 ................... 10 - 4
Tables
10-1 Additional Reaction Times ................................... 10 - 5
EWA 4NEB 812 6120-02

S5-100U Interrupt Processing
10 Interrupt Processing, for CPU 103 Version

8MA02 and Higher
Interrupt-driven program processing starts when a signal from the CPU causes the programmable
controller to interrupt cyclic or time-controlled program scanning in order to process a specific
program. Once this program has been scanned, the CPU returns to the point of interruption in the
cyclic or time-controlled program and resumes processing at that point.
Prerequisites for Interrupt-Driven Program Processing

Interrupt-driven program processing is possible only if the following conditions are met:
• The bus unit with interrupt capability is directly adjacent to the CPU (slots 0 and 1).
• Four-channel digital input modules or comparator modules must be mounted on the bus unit to
transfer process interrupts.
- You may plug other modules in, but these modules will have no interrupt handling capability.
• The programmable controller is in the Power ON state and in the RUN operating mode.
• Interrupt processing is not disabled by an IA operation in your program. See section 8.2.8.
• OB2 has been programmed.
Slot 0 1 2 3
° ° ° °
° ° ° °
° ° ° °
° ° ° °
CPU ° °
° °
° °
° °
4 8 4 8
DI DI DI DI
Bus unit with interrupt capability (but
acts only like a “normal” bus unit)
Interrupts are handled
only by this module
Bus unit with interrupt capability
Figure 10-1. Possible Configuration of the Programmable Controller with Bus Units
Having Interrupt Capability
10.1 Interrupt Processing with OB2, for CPU 103 Version 8MA02 and
Higher
For interrupt-driven processing, OB2 must have been programmed. OB2 is called up by a process
interrupt and interrupts in turn the cyclic or time-controlled program scanning. Other blocks can be
called from OB2. After the interrupt-driven program has been processed, the CPU resumes cyclic
or time-controlled program scanning.
EWA 4NEB 812 6120-02 10-1

Interrupt Processing S5-100U
Triggering an Interrupt
Interrupts can only be triggered by four-channel digital input modules and comparator modules that
are plugged into slots 0 and 1 on a bus unit with interrupt capability.
Interrupts are triggered by a change in the signal state (0 1=positive edge; 1 0=negative edge)
at the respective interrupt input. Then the programmable controller automatically branches to OB2.
If you have not programmed OB2, either the cyclic or time-controlled program resumes immediately
after the interrupt.
The cyclically processed program can be interrupted after every STEP 5 statement.
The processing of integral FBs can be interrupted at certain points (see section 9.2). The data cycle
(see section 2.2.2) can be interrupted after each data packet consisting of four data bits and a check
bit.
Cyclic or time-controlled Interrupt-driven

program processing program processing
. . . Interrupt PII
A I 0.2 OB2
S Q 14.0 L PY2
INTERRUPT!
. . . .
.
BE .
BE
Interrupt PIQ
Figure 10-2. Program Interruptions by Process Interrupts
Use the IA command to disable interrupt processing. Use the RA command to enable interrupt
processing. The default setting is RA (see section 8.2.8).
Note
Even for interrupt processing, you may not exceed the general block nesting depth of 16
levels.
Interrupt Priorities
If a second interrupt is triggered during an interrupt processing, the second interrupts is processed
at the end of the first interrupt processing.
Note
If both a positive and negative pulse edge occur at an interrupt input while the IA
operation is valid (disable interrupt), it is no longer possible to determine the channel that
has triggered the interrupt.
But after an RA operation, OB2 is still called up.
10-2 EWA 4NEB 812 6120-02

Reading Out the Interrupt PII
If a process interrupt occurs, only the signal states of the interrupt inputs in slots 0 and 1 are read
out to the interrupt PII.
This data in the interrupt PII is the only data provided to the interrupt-driven program for evaluation.
The interrupt PII can be scanned in OB2 by means of the following load operations:
Overview:
Operation Operand Description
L PY0 Load byte 0 of the interrupt PII into ACCU 1

L PY1 Load byte 1 of the interrupt PII into ACCU 1
L PW0 Load word 0 of the interrupt PII into ACCU 1
If you enter other parameters, the CPU goes into the STOP mode and enters the “NNN” error
message in the ISTACK (see section 5.2). When data is read into the interrupt PII, the normal PII is
not written to simultaneously.
Writing to the Interrupt PIQ
Data from time-controlled or interrupt-driven programs to I/O modules are written to the interrupt PIQ
and simultaneously to the “normal” PIQ.
After OB2 is finished, the data that has been transferred to the interrupt PIQ is output to the
peripheral I/Os in an interrupt output data cycle (before “normal” program processing).
After the OB1 program cycle, the PIQ is copied to the interrupt PIQ.
The interrupt output data cycle is executed only if the interrupt PIQ has been written to. Use
transfer statements to write data for I/O modules to the interrupt PIQ. When data is written to the
interrupt PIQ, data is written simultaneously to the normal PIQ.
Overview:
Operation Operand Description
T PY0 to 127 Transfer contents of ACCU 1 into the interrupt PIQ
T PW0 to 126 Transfer contents of ACCU 1 into the interrupt PIQ
EWA 4NEB 812 6120-02 10-3

Interrupt Processing S5-100U
Possibilities of Accessing Process I/O Image Tables

The following figure shows how data transfer between the process I/O image tables and ACCU 1
takes place when using various load and transfer statements in OB2.
Interrupt
PII PII
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aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
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aaaaaaaaaaaa
aaaaaaaaaaaa
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T IBX/T IW X L IBX/L IW X L PYX/L PY1/L PW0

ACCU 1
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T QBX/T QW X
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T PYX/T PW X
Interrupt
PIQ PIQ
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X=byte or word address
Figure 10-3. Accessing the Process Image Tables from OB2
Example of How OB2 Can Be Programmed

Binary statements can access only the normal PII and PIQ. In order to determine the channel that
triggered an interrupt, transfer the I/O byte or word, for example, to a flag byte or word and then
evaluate using binary statements.
Example STL OB2 Explanation
Two sensors are L PY 0 Load byte 0 of the interrupt PII into ACCU 1 and
connected on channels 0 T FY 0 transfer it to flag byte 0.
and 1 on a four-channel A F 0.0 Did a positive edge occur on channel 0?
digital input module on AN I 0.0 OR
slot 0. O
Branch to FB12 if sensor 1 AN F 0.0 Did a negative edge occur on channel 0?
(channel 0) triggers an A I 0.0
interrupt. JC FB 12 If a pulse edge has occurred, a branch is made
... to FB12.
Caution
Be sure to save the flags (in a data block, for example) if these flags are to be
overwritten during interrupt processing and are needed again in the cycle.
10-4 EWA 4NEB 812 6120-02

10.2 Calculating Interrupt Reaction Times
The total reaction time is is the sum of the following times:

• Signal delay of the module triggering the interrupt (= time from the input signal change
triggering the interrupt to the activation of the interrupt line)
• Interrupt reaction time of the CPU
• Execution time of the interrupt program (= sum of all STEP 5 statements in the interrupt
evaluation program)
Calculate the interrupt reaction times as follows:

CPU’s interrupt reaction time = basic reaction time + additional reaction times
The basic reaction time is 0.6 ms and is valid if the following conditions exist:
• No integrated FBs were used.
• No parameters for the integral clock are set.
• No programmer/OP functions are present.
• OB13 has not been programmed.
• No SINEC L1 is connected.
The additional reaction times are variable. They are listed in Table 10-1.
Table 10-1. Additional Reaction Times
Additional Running Functions of the Interrupt Reaction

Programmable Controller Times
Integrated FBs 0.5 ms

Parameters set for clock 0.2 ms
SINEC L1 bus to the programmer interface 8.0 ms

OP functions Depending on the number of bytes used
for loading the memory
Programmer functions:
Status block/Transfer block 0.5 ms

Output address 18 ms per kbyte
Compress
• If no blocks are moved • Depending on the number of blocks
present (after overall reset 31 ms)
• If blocks are moved • 600 ms per each 1kword of

instructions in the block to be
moved
EWA 4NEB 812 6120-02 10-5

11 Analog Value Processing
11.1 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1

11.1.1 Connecting Current and Voltage Sensors to Analog
Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1
11.2.1 Voltage Measurement with Isolated/Non-Isolated
Thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11.2.2 Two-Wire Connection of Voltage Sensors . . . . . . . . . . . . . . . . . . . 11 - 3
11.2.3 Two-Wire Connection of Current Sensors . . . . . . . . . . . . . . . . . . . 11 - 4
11.2.4 Connection of Two-Wire and Four-Wire Transducers . . . . . . . . . . . . 11 - 4
11.2.5 Connection of Resistance Thermometers . . . . . . . . . . . . . . . . . . . . 11 - 6
11.3 Start-Up of Analog Input Modules ......................... 11 - 7
11.4 Analog Value Representation of Analog Input Modules .......... 11 - 11
11.5 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19

11.5.1 Connection of Loads to Analog Output Modules . . . . . . . . . . . . . . . 11 - 19
11.5.2 Analog Value Representation of Analog Output Modules . . . . . . . . . 11 - 20
11.6 Analog Value Conversion: Function Blocks FB250 and FB251 . . . . . 11 - 22

11.6.1 Reading in and Scaling an Analog Value -FB250- . . . . . . . . . . . . . . 11 - 22
11.6.2 Output of Analog Value -FB251- . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
EWA 4NEB 812 6120-02

Figures
11-1 Voltage Measuring with Isolated Thermocouples

(6ES5 464-8MA11/8MA21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11-2 Voltage Measuring with Non-Isolated Thermocouples
(6ES5 464-8MA11/8MA21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 2
11-3 Two-Wire Connection of Voltage Sensors
(6ES5 464-8MB11, 464-8MC11, 466-8MC11) . . . . . . . . . . . . . . . . . . . . . . 11 - 3
11-4 Two-Wire Connection for Current Sensors (6ES5 464-8MD11) . . . . . . . . . . 11 - 4
11-5 Connection of Two-Wire Transducers (6ES5 464-8ME11) . . . . . . . . . . . . . 11 - 4
11-6 Connection for Four-Wire Transducers (6ES5 464-8ME11) ............ 11 - 5
11-7 Wiring Method for PT 100 (6ES5 464-8MF11/8MF21) . . . . . . . . . . . . . . . . 11 - 6
11-8 Wiring Possibilities for Input Modules (6ES5 464-8MF11) . . . . . . . . . . . . . . 11 - 6
11-9 Load Connection via a Four-Wire Circuit
(6ES5 470-8MA11, 6ES5 470-8MD11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19
11-10 Load Connection via a Two-Wire Circuit
(6ES5 470-8MB11, 6ES5 470-8MC11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 20
11-11 Scaling Schematic for FB250 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 22
11-12 Schematic for “Display of Tank Make-Up Quantity” .................. 11 - 23
11-13 Conversion of the Nominal Range into the Defined Range ............. 11 - 23
11-14 Schematic for “Display of Tank Contents” . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
11-15 Transformation of the Analog Value to the Nominal Range . . . . . . . . . . . . . 11 - 26
EWA 4NEB 812 6120-02

Tables
11-1 Operating Mode Switch Settings for Analog Input Modules 464-8 to 11 .... 11 - 7
11-2 Operating Mode Switch Settings for Analog Input
Module 464-8MA21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8/9
11-3 Operating Mode Switch Settings for Analog Input
Module 464-8MF21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 10
11-4 Representation of an Analog Input Value as Bit Pattern . . . . . . . . . . . . . . . . 11 - 11
11-5 Analog Input Module 464-8MA11, -8MF11, -8MB11
(Bipolar Fixed-Point Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 11
11-6 Analog Input Module 464-8MC11, -8MD11
(Bipolar Fixed-Point Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-7 Analog Input Module 464-8ME11, 4x4 to20 mA
(Absolute Value Representation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-8 Analog Input Module 464-8MF11, 2x PT 100 (Unipolar)
Analog Input Module 464-8MF21, 2x PT 100 “No Linearization”
(Unipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12
11-9 Analog Input Module 464-8MF21, 2x PT 100 “with Linearization”
(Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 13
11-10 Analog Input Module 464-8MA21, 4x±50 mV “with Linearization” and
“with Temperature Compensation” (Bipolar); Thermoelement Type K
(Nickel-Chromium/Nickel-Aluminium, according to IEC 584) . . . . . . . . . . . . . 11 - 14
“with Temperature Compensation” (Bipolar); Thermoelement Type J
(Iron/Copper-Nickel (Konstantan), according to IEC 584) . . . . . . . . . . . . . . . 11 - 15
“with Temperature Compensation” (Bipolar); Thermoelement Type L
(Iron/Copper-Nickel (Konstantan) according to DIN 43710) . . . . . . . . . . . . . 11 - 16
11-13 Analog Input Module 466-8MC11, 4x 0 to10 V . . . . . . . . . . . . . . . . . . . . . . 11 - 16
11-14 Representation of an Analog Output Value as a Bit Pattern ............ 11 - 20
11-15 Output Voltages and Currents for Analog Output Modules
(Fixed-Point Number Bipolar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21
11-16 Output Voltages and Currents for Analog Output Modules (Unipolar) . . . . . . 11 - 21
EWA 4NEB 812 6120-02

S5-100U Analog Value Processing
11 Analog Value Processing
11.1 Analog Input Modules
Analog input modules convert analog process signals to digital values that the CPU can process (via
the process image input table, PII). In the following sections, you will find information about the
operating principle, wiring methods, and start-up and programming of analog input modules.
11.2 Connecting Current and Voltage Sensors to Analog Input Modules
Observe the following rules to connect current and voltage sensors to analog input modules:
• When you have multi-channel operations, assign the channels in ascending order. This shortens
the data cycle.
• Use terminals 1 and 2 for the connection of a compensating box (464-8MA11 ) or for the supply
of two-wire transducers (464-8ME11).
- Terminals 1 and 2 cannot be used with the remaining analog input modules.
• Short-circuit the terminals of unused inputs.
• Set the reference potentials of the sensors to a common reference potential. Do this to prevent
the potential difference between the common references from exceeding 1 V.
EWA 4NEB 812 6120-02 11-1

Analog Value Processing S5-100U
11.2.1 Voltage Measurement with Isolated/Non-Isolated Thermocouples
Module 464-8MA11/8MA21 is recommended for voltage measurement with thermocouples. With

floating sensors (e. g., isolated thermocouples), the permissible potential difference VCM between
terminals of the inputs and the potential of the standard mounting rail must not be exceeded. To
avoid this, the negative potential of the sensor must be connected to the central ground point (see
Figure 11-1). Jumper terminals 1 and 2 together if you do not use compensation boxes.
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+ - + -+ -
Compen-
sating box
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Thermal
coupling
Figure 11-1. Voltage Measuring with Isolated Thermocouples (6ES5 464-8MA11/8MA21)
With non-floating sensors (e. g., non-isolated thermocouples), the permissible potential difference
VCM must not be exceeded (see maximum values of the individual modules).
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Compen-
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Thermal
sating box
coupling
Figure 11-2. Voltage Measuring with Non-Isolated Thermocouples

(Module 6ES5 464-8MA11/8MA21)
11-2 EWA 4NEB 812 6120-02

Connection of Thermocouples with Compensating Box to Module 464-8MA11/8MA21
The influence of the temperature on the reference junction (e. g., terminal box) can be compensated
for with a compensation box. Observe the following rules:
• The compensation box must have a floating supply.
• The power supply must have a grounded shielding winding.
• The compensation box must be connected to terminals 1 and 2 of the terminal block.
11.2.2 Two-Wire Connection of Voltage Sensors
You can use the following three modules for the connection of voltage sensors:
• Analog Input Module 464-8MB11 for voltages of±1 V
• Analog Input Module 464-8MC11 for voltages of±10 V
• Analog Input Module 466-8MC11 for voltages from 0 to 10 V
Figure 11-3 shows the two-wire connection of voltage sensors.

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+ -+ -+ -+ -
V V V V
Figure 11-3. Two-Wire Connection of Voltage Sensors

(6ES5 464-8MB11, 464-8MC11, 466-8MC11)
EWA 4NEB 812 6120-02 11-3

11.2.3 Two-Wire Connection of Current Sensors
You can use module 464-8MD11 for the two-wire connection of current sensors.
Figure 11-4 shows the two-wire connections of current sensors.
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Figure 11-4. Two-Wire Connection for Current Sensors (6ES5 464-8MD11)
11.2.4 Connection of Two-Wire and Four-Wire Transducers
Use the 24-V inputs 1 and 2 of analog input module 464-8ME11 to supply the two-wire transducers.
The two-wire transducer converts the supplied voltage to a current of 4 to 20 mA.
For wiring connections, see Figure 11-5.
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L+ M trans- trans-
ducer ducer
Figure 11-5. Connection of Two-Wire Transducers (6ES5 464-8ME11)
11-4 EWA 4NEB 812 6120-02

If you use a four-wire transducer connect it as shown in Figure 11-6.

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U Four-wire transducer
Figure 11-6. Connection for Four-Wire Transducers (6ES5 464-8ME11)
Four-wire transducers require their own power supply. Connect the “+” pole of the four-wire
transducer to the corresponding “-” pole of the terminal block (a connection technique that is the
opposite of the two-wire transducer). Connect negative terminals of the four-wire transducer to
terminal two of the terminal block.
Inputs 4, 6, 8, and 10 of the analog input module 464-8ME11 are connected internally via shunt
resistors. Because of the internal shunt resistors, broken wire signaling is not possible.
EWA 4NEB 812 6120-02 11-5

11-6
11.2.5
circuits.
(e.g., PT 100).
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6
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10
-
connection and short circuit the terminals IC+ and IC-.
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Connection of Resistance Thermometers

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(7/8):
(5/6):
(3/4):
10
(9/10):
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Terminal assignments:
Figure 11-7. Wiring Method for PT 100 (6ES5 464-8MF11/8MF21)

Figure 11-8. Wiring Possibilities for Input Modules (6ES5 464-8MF11)

inputs have a high resistance so that only a negligible current loss develops in the measuring
Measuring circuit M0
channel for voltage measurement (± 500 mV). In this case, use terminals M+/M- for the signal
Measuring circuits M1
drops in these “constant current circuits” do not affect the measurement results. The measuring
Analog input module 464-8MF11/8MF21 is suited for the connection of resistance thermometers
The resistance of the PT 100 is measured in a four-wire circuit. A constant current is supplied to
If you use only one channel for PT 100 measurement (e.g., channel 0), then you can use the other
the resistance thermometer via terminals 7 and 8 as well as via terminals 9 and 10, so that voltage
Constant current circuit IC 1

Constant current circuit IC 0
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EWA 4NEB 812 6120-02

S5-100U
11.3 Start-Up of Analog Input Modules

Set the intended operating mode using the switches on the front panel of analog input modules
464-8 through 11. These switches are located on the right side at the top of the front panel of the
module.
Power supply Set the switch to the available power supply frequency. This selects the inte-
frequency: gration time of the A/D converters for optimal interference voltage suppression.
Power frequency 50 Hz: Integration time 20 ms
Power frequency 60 Hz: Integration time 16.66 ms
Operation: Set the number of channels you wish to assign on the input module. If there are
fewer than four channels, less address space will be assigned and measured
values will be updated faster.
Broken wire: Once the broken wire signal has been activated, a break on one of the lines to
the sensor (thermocouple or PT 100) or of the sensor itself causes the red LED
above the function selection switch to light up. At the same time, the broken wire
error bit F (bit 1, byte 1) for the faulty channel is set.
The module “recognizes” a wire break by applying a conventional tripping current

to the input terminals and by comparing the resulting voltage to a limit value. If
there is a wire break in the sensor or the lines, the voltage exceeds the limit value
and a “wire break” signal is sent. When the signal at the input is measured with
a digital voltmeter, the tripping current pulses cause apparent fluctuations of the
signal. Deactivation of the wire break signal does not turn off the tripping current.
Additional operating mode switch selections possible with analog module 464-8MA21:
Table 11-1. Operating Mode Switch Settings for Analog Input Modules 464-8 to 11
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Function Settings for Operating Mode Switch
50 Hz 60 Hz
Power supply 4 4
3 3
frequency 2 2
1 1
1 channel 2 channels (channel 0 4 channels (channel 0

(channel 0) and channel 1) - channel 3)
Operation 4 4 4
3 3 3
2 2 2
1 1 1
With wire break signal No wire break signal
Wire break 4 4
3 3
2 2
1 1
EWA 4NEB 812 6120-02 11-7

Linearization: With this function, you can obtain a characteristic linearization of the thermo-
couples of type J, K, and L or of the resistance thermometer PT 100. With module
464-8MA21, the linearization must always be activated together with the
corresponding compensation of the reference point temperature.
Thermocouples:
Type J: - 200° C to +1200° C (-328° F to 2192° F)
Type K: - 200° C to +1369° C (-328° F to 2497° F)
Type L: - 199° C to + 900° C (-326° F to 1652° F) in steps each of 1° C (1.8° F)
Temperature For the thermocouples of type J, K, and L, you can compensate, on the one hand,
compensation: the temperature of the reference point using a compensating box.
(See Figure 11-1). On the other hand, it is possible to move the reference point to
the front of the module by activating the “temperature compensation” function.
When thermocouples are directly connected, an internal circuit on the module
causes the digital value “0” to be displayed independently of the temperature of
the terminal when the temperature at the measuring junction is 0° C (32° F). In
order to accomplish this, the terminals of the sensors have to be connected
directly to the module, i.e., without a copper extension cable.
Table 11-2. Operating Mode Switch Settings for Analog Input Module 464-8MA21
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Function Settings for Operating Mode Switch

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50 Hz 60 Hz
8 8
7 7
Power supply 6 6
5 5
frequency 4 4
3 3
2 2
1 1
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1 channel 2 channels (channel 0 4 channels (channel 0

(channel 0) and channel 1) - channel 3)
8 8 8
Operation 7 7 7
6 6 6
5 5 5
4 4 4
3 3 3
2 2 2
1 1 1
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With wire break signal No wire break signal

8 8
7 7
6 6
Wire break 5 5
4 4
3 3
2 2
1 1
11-8 EWA 4NEB 812 6120-02

•
•
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S5-100U
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Table 11-2.
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Characteristic
compensation
linearization of
EWA 4NEB 812 6120-02

thermocouples
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the following two settings:

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(continued)
“No temperature compensation”

without
1
2
3
4
5
6
7
8
linearization
1
2
3
4
5
6
7
8
compensation
without temperature
464-8MA21 functions just like module 464-8MA11.

type K
1
2
3
4
5
6
7
8
Linearization
1
2
3
4
5
6
7
8
sation for type K

Temperature compen-
type J
1
2
3
4
5
6
7
8
Linearization
Settings for Operating Mode Switch

1
2
3
4
5
6
7
8
Operating Mode Switch Settings for Analog Input Module 464-8MA21

type L
1
2
3
4
5
6
7
8
is 0° C (32° F). This means that with 0° C (32° F) at the measuring junction, the value “0” is dis-
box if you use the thermostat temperature in the application software to adjust the thermocouple
If you have set “Characteristic linearization” and “Temperature compensation” with the operating
When you set the switches to “no linearization” and “no temperature compensation”, then module
designed only for a certain type of thermocouple. It is possible to use a thermostat in the terminal
mode switches on module 464-8MA21 for the thermocouple used, then the reference temperature
Linearization
mixed thermocouples, or if you use thermocouples other than type J, K, or L, then you must choose
Temperature compen-
Compensation is then not possible even with a compensating box because the compensating box is
If you equip several channels with thermocouples, use the same type of thermocouple. If you select
sation for types J and L
11-9
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11-10
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PT 100:
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Function
frequency
Operation
Wire break
linearization
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for the PT 100

Power supply
Characteristic
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functions just like module 464-8MF11.

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1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
50 Hz
1 channel
1
2
3
4
5
6
7
8
(channel 0)
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-100° C to+850° C (-148° F to 1569° F)

With wire break signal
No linearization
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Position 1 and 2 on the operating mode switch have no function.

Set the switches on analog module 464-8MF21 as illustrated in Table 11-3.

The characteristic linearization is possible for the following temperature ranges.

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Settings for Operating Mode Switch

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(in steps of 0.5° C (0.9° F))

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
60 Hz
1
2
3
4
5
6
7
8
channel 1)
1
2
3
4
5
6
7
8
No wire break signal

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Table 11-3. Operating Mode Switch Settings for Analog Input Module 464-8MF21
Linearization for PT 100

2 channels (channel 0 and

If you set the switch to “no linearization” and “no temperature compensation”, module 464-8MF21
EWA 4NEB 812 6120-02

S5-100U
11.4 Analog Value Representation of Analog Input Modules

Each analog process signal has to be converted into a digital format, to be stored in the process
image input table (PII). The analog signals are converted into a binary digit that is written in one of
the following ways:
• In one byte (466-8MA11)
• In two bytes (the remaining analog input modules)
Each bit position has a fixed value in powers of two (see Tables 11-4 and 11-14). Analog values
are represented in two's complement.
The following tables show the analog value representations of the different analog inputs in 2-byte
format. You will need this information to program FB250 and FB251 (see section 11.6).
Table 11-4. Representation of an Analog Input Value as Bit Pattern

High Byte Low Byte
Bit Number 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Analog Value Represent. S 211 210 29 28 27 26 25 24 23 22 21 20 X E OV
Key: S Sign bit 0="+", 1="-"

X Irrelevant bits
E Error bit 0= no wire break; 1=wire break
OV Overflow bit 0= Measured value 4095 units at the most
1= Measured value greater than or equal to 4096 units
Analog value representation for analog input modules 464-8...
Table 11-5. Analog Input Module 464-8MA11, -8MF11, -8MB11 (Bipolar Fixed-Point Number)
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Measured Value
Units High Byte Low Byte Range
in mV
>4095 100.0 1000.0 2000.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow

4095 99.976 999.75 1999.5 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
2049 50.024 500.24 1000.48 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Overrange
2048 50.0 500.0 1000.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 25.0 250.0 500.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0.024 0.24 0.48 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0.0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
-1 - 0.024 -0.24 -0.48 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-1024 - 25.0 - 250.0 - 500.0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-2048 -50.0 -500.0 -1000.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-2049 -50.024 -500.24 -1000.48 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
-4095 -99.976 -999.75 -1999.5 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
<-4095 -100.0 -1000.0 -2000.0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Overflow
464-8MA11/-8MA21 “No linearization” (4x±50 mV)

464-8MF11 (2x±500 mV)
464-8MB11 (4x±1 V)
EWA 4NEB 812 6120-02 11-11

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Table 11-6. Analog Input Module 464-8MC11, -8MD11 (Bipolar Fixed-Point Number)
Measured Value
in V in mA
>4095 20.000 40.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow

4095 19.995 39.9902 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2049 10.0048 20.0098 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
2048 10.000 20.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 5.000 10.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0.0048 0.0098 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
-1 -0.0048 -0.0098 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-1024 - 5.000 -10.0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-2048 -10.000 -20.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-2049 -10.0048 -20.0098 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
-4095 -19.995 - 39.9902 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
<-4095 -20.000 -40.0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Overflow
464-8MC11 (4x±10 V)
464-8MD11 (4x±20 mA)
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Table 11-7. Analog Input Module 464-8ME11, 4x4 to 20 mA (Absolute Value Representation)
Measured Value
Units High Byte Low Byte Range*
in mA
>4095 > 32.769 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow
4095 31.992 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2561 20.008 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0
2560 20.0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2048 16.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
512 4.0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
511 3.992 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0
384 3.0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Transducer
-1 -0.008 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 failure?
<-4095 <-32.769 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
* Because of tolerances of components used in the module, the converted value can also be negative
(e.g. FFF8H Unit: -1).
Table 11-8. Analog Input Module 464-8MF11, 2x PT 100 (Unipolar)

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Analog Input Module 464-8MF21, 2x PT 100 “No Linearization” (Unipolar)

Resistance
in
>4095 400.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Overflow
4095 399.90 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Overrange
2049 200.098 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
2048 200.0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1024 100.0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Nominal range
1 0.098 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11-12 EWA 4NEB 812 6120-02

Table 11-9. Analog Input Module 464-8MF21, 2x PT 100 “with Linearization” (Bipolar)
Resis- Temperature in
tance in °C °F
>1766 >400 >883 >1531 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Overflow
1766 883 1531 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 1 Overrange*
1702 851 1564 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1
1700 390.26 850 1562 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0
1400 345.13 700 1292 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0
1000 280.90 500 932 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
600 212.02 300 572 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0
300 157.31 150 302 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0
200 138.50 100 212 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 Nominal range
2 100.39 1 34 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 100.00 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-40 92.16 -20 -4 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0
-80 84.27 -40 -40 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0
-200 60.25 -100 -148 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-202 -101 -150 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 Overrange*
-494 -247 -413 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1
<-494 <-247 <-403 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 Overflow
* In the overrange area, the current slope of the characteristic curve is maintained when leaving the linearized nominal range.
EWA 4NEB 812 6120-02 11-13

Table 11-10. Analog Input Module 464-8MA21, 4x±50 mV “with Linearization”

and “with Temperature Compensation” (Bipolar); Thermoelement Type K
(Nickel-Chromium/Nickel-Aluminium, according to IEC 584)
Thermal Temperature
Units Voltage High Byte Low Byte Range
in mV* °C °F
>2359 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 Overflow
Overrange**
1370 1370 2498 0 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1
1369 54.773 1369 2496 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0
1000 41.269 1000 1832 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
500 20.640 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
150 6.137 150 302 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0
100 4.095 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 Nominal range
1 0.039 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.039 1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -3.553 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-101 -3.584 -101 -150 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 Accuracy
-150 -4.912 -150 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0 2K
-200 -5.891 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-201 -201 -330 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 Overrange**
-273 1 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 1 0 Wire break
This value corresponds to the terminal temperature at wire break
* For a reference temperature of 0° C (32° F)

** In the overrange area, the current slope of the characteristic curve is maintained when leaving
the linearized nominal range.
11-14 EWA 4NEB 812 6120-02


and “with Temperature Compensation” (Bipolar); Thermoelement Type J
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(Iron/Copper-Nickel (Konstantan), according to IEC 584)

Thermal
Units Temperature
Voltage High Byte Low Byte Range
°C °F
in mV*
1485 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 Overflow
Overrange**
1201 1201 2194 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1
1200 69.536 1200 2192 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0
1000 57.942 1000 1832 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0
500 27.388 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
100 5.268 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
1 0.05 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Nominal range
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.05 -1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -4.632 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-150 -6.499 -199 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0
-199 -7.868 -200 -326 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
-200 -7.890 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0
-201 -201 -330 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 Overrange**
-273 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 F 0 Wire break
This value corresponds to the terminal temperature at wire break

** In the overrange area, the current slope of the characteristic curve is maintained when leaving the
linearized nominal range.
EWA 4NEB 812 6120-02 11-15


and “with Temperature Compensation” (Bipolar); Thermoelement Type L
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(Iron/Copper-Nickel (Konstantan), according to DIN 43710)

Thermal
Temperature
Units Voltage High Byte Low Byte Range
in mV* °C °F
1361 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 Overflow
Overrange**
901 901 1654 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 1
900 53.14 900 1652 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0
500 27.85 500 932 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
250 13.75 250 482 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0

100 +5.37 100 212 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 Nominal range
1 0.05 1 34 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-1 -0.05 -1 -30 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
-100 -4.75 -100 -148 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0
-150 -6.60 -150 -238 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 0
-190 -7.86 -190 -310 1 1 1 1 1 0 1 0 0 0 0 1 0 0 0 0
-199 -8.12 -199 -326 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
-200 -200 -328 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 Overrange**
-273 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 Overflow
X X X X X X X X X X X X X X X 0 1 0 Wire break
This value corresponds to the terminal temperature at wire

break
** In the overrange area, the current slope of the characteristic curve is maintained when leaving the
linearized nominal range.
Analog value representation of analog input module 466-8MC11
The 466-8MC11 analog input module stores each analog value in a single byte. The other analog
input modules store the analog values in words (see Table 11-4).
Table 11-13. Analog Input Module 466-8MC11, 4x 0 to 10 V
Units Voltage in mV Bit Representation
255 9961 1 1 1 1 1 1 1 1
254 9922 1 1 1 1 1 1 1 0
. . .
128 5000 1 0 0 0 0 0 0 0
. . .
1 39 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
11-16 EWA 4NEB 812 6120-02

If you want to read in the analog value with function block FB250 (analog value reading), you have to
pre-process the analog value before calling up FB250.
Example 1:
Analog input module 466-8MC11 is inserted in slot 1, which means that the module's start address
is 72.
The analog values are stored in four consecutive bytes:

1st analog value (channel 0) in IB72
2nd analog value (channel 1) in IB73
3rd analog value (channel 2) in IB74
4th analog value (channel 3) in IB75
Function block FB72, pictured below, reads in the analog values and pre-processes them for
function block FB250 (analog value reading).
FB72 Explanation
NAME :READ 466

READ IN ALL CHANNELS
0005 : OF AI 466
0006 :L IW 72 READ ALL FOUR CHANNELS
0007 :T FW 72 AND REARRANGE
0008 :L IW 74
0009 :T FW 74
000A :
000B :L FY 72 PROCESS EACH ANALOG VALUE
000C :SLW 3 AND REWRITE THEM IN
000D :T IW 72 THE PII SO THAT FB250
000E : CAN ACCESS THEM
000F :L FY 73 WITHIN THAT SCAN.
0010 :SLW 3
0011 :T IW 74
0012 :
0013 :L FY 74
0014 :SLW 3
0015 :T IW 76
0016 :
0017 :L FY 75
0018 :SLW 3
0019 :T IW 78
001A :
001B :BE
EWA 4NEB 812 6120-02 11-17

Example 2:
Analog input module 466-8MC11 is inserted in slot 0, which means that the module’s start address
is 64.
The analog values that are read in are stored in four consecutive bytes:
1st analog value (channel 0) in IB64
2nd analog value (channel 1) in IB65
3rd analog value (channel 2) in IB66
4th analog value (channel 3) in IB67
Function block 73, pictured below, reads in the analog values and pre-processes them for FB250.
The additional processing with FB250 is done just like module 464, however without an overflow bit.
FB73 Explanation
NAME :READ AI
0005 :
0006 :
0007 :L IB 67 Read in channel 3
0008 :SLW 3
0009 :T IW 70
000A :
000B :L IB 66 Read in channel 2
000C :SLW 3
000D :T IW 68
000E :
000F :L IB 65 Read in channel 1
0010 :SLW 3
0011 :T IW 66
0012 :
0013 :L IB 64 Read in channel 0
0014 :SLW 3
0015 :T IW 64
0016 :
0017 :
11-18 EWA 4NEB 812 6120-02

•
•
•
•
•
11.5
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EWA 4NEB 812 6120-02

S+
voltages or currents.
be compensated for.
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(4/8) (3/7)
L+
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1
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M
RL
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470-8MA11 (2x±10 V)
24 V DC
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2
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470-8MD11 (2x+1 to 5 V)
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3
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S+
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4
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QV
(5/9) (6/10)
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S- MANA
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5
S-
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Analog Output Modules

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MANA
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S+
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Unused outputs must be left open-circuited.

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Terminals
8
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Check the following items before connecting loads:
QV
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S-
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MANA
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11.5.1 Connection of Loads to Analog Output Modules
RL:
The load voltage 24 V DC must be connected to terminals 1 and 2.
S±:
QV:
Key:
MANA:
No adjustments are necessary if you want to connect loads to the analog outputs.
The maximum permissible potential difference between the outputs is 60 V AC.

Sensor line
Load resistor
Figure 11-9 shows how to connect loads to the voltage outputs of the following modules:
The sensor lines (S+ and S-) must be directly connected to the load, so that the voltage is
of the analog unit

Analog output modules convert the bit patterns that are output by the CPU into analog output
the load resistance. In such a case, connect terminal S+to terminal QV, and terminal S- to MANA.
Analog output "Voltage"
Chassis ground terminal

The sensor lines can be left out if the resistances of the QV and M lines are negligible compared to
measured and regulated directly at the load. In this manner, voltage drops of up to 3 V per line can
Figure 11-9. Load Connection via a Four-Wire Circuit (6ES5 470-8MA11 or 6ES5 470-8MD11)
11-19
S5-100U
•
•
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Key:
11-20
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Bit number
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L+
QI
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S
24 V DC
2
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3
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Analog value represent.

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470-8MB11 (2x±20 mA)
4
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sign bit
aaa
S
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5
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aaa
470-8MC11 (2x+4 to 20 mA).

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6
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irrelevant bits
210
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MANA
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(6/10)
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5
7
29
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8
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4
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28
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9
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3
27
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Terminals
10
High Byte
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26
1
25
Terminal assignment
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0
24
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QI:
Key:
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MANA:
7
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6
22
5
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21
4
20
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11.5.2 Analog Value Representation of Analog Output Modules

of the analog unit
3
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Low Byte
Table 11-14. Representation of an Analog Output Value as a Bit Pattern

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2
X
Figure 11-10 shows how to connect loads to the current outputs of the following modules.
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Analog output "Current"

Chassis ground terminal
1
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X
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0
Table 11-14 shows how the analog output value has to be stored in the process image output table
X
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Figure 11-10. Load Connection via a Two-Wire Circuit (6ES5 470-8MB11 or 6ES5 470-8MC11)
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EWA 4NEB 812 6120-02

Table 11-15 and 11-16 show the voltage and currents assigned to the bit patterns.
Table 11-15. Output Voltages and Currents for Analog Output Modules
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(Fixed-Point Number Bipolar)

Output Values
in V in mA
1280 12.5 25.0 0 1 0 1 0 0 0 0 0 0 0 0 x x x x Overrange

1025 10.0098 20.0195 0 1 0 0 0 0 0 0 0 0 0 0 x x x x
1024 10.0 20.0 0 1 0 0 0 0 0 0 0 0 0 0 x x x x
512 5.0 10.0 0 0 1 0 0 0 0 0 0 0 0 0 x x x x
1 0.0098 0.0195 0 0 0 0 0 0 0 0 0 0 0 0 x x x x
0 0.0 0.0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x
-1 -0.0098 -0.0195 1 1 1 1 1 1 1 1 1 1 1 1 x x x x Nominal range
-512 -5.0 -10.0 1 1 1 0 0 0 0 0 0 0 0 0 x x x x
-1024 -10.0 -20.0 1 1 0 0 0 0 0 0 0 0 0 0 x x x x
-1025 -10.0098 -20.0195 1 0 1 1 1 1 1 1 1 1 1 1 x x x x
-1280 -12.5 -25.0 1 0 1 1 0 0 0 0 0 0 0 0 x x x x Overrange
2x±10 V 6ES5 470-8MA11

2x±20 mA 6ES5 470-8MB11
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Table 11-16. Output Voltages and Currents for Analog Output Modules (Unipolar)
Output Values
in V in mA
1280 6.0 24.0 0 1 0 1 0 0 0 0 0 0 0 0 x x x x Overflow

1025 5.004 20.016 0 1 0 0 0 0 0 0 0 0 0 1 x x x x
1024 5.0 20.0 0 1 0 0 0 0 0 0 0 0 0 0 x x x x
512 3.0 12.0 0 0 1 0 0 0 0 0 0 0 0 0 x x x x Nominal range
1 1.004 4.016 0 0 0 0 0 0 0 0 0 0 0 1 x x x x
0 1.0 4.0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x
-1 0.996 3.984 1 1 1 1 1 1 1 1 1 1 1 1 x x x x
-256 0.0 0.0 1 1 1 1 0 0 0 0 0 0 0 0 x x x x
-512 -1.0 -4.0 1 1 0 0 0 0 0 0 0 0 0 0 x x x x Overrange
-1024 -3.0 -12.0 1 1 0 0 0 0 0 0 0 0 0 0 x x x x
-1280 -4.0 -16.0 1 0 1 1 0 0 0 0 0 0 0 0 x x x x
2x 1 to 5 V 6ES5 470-8MD11
2x 4 to 20 mA 6ES5 470-8MC11
EWA 4NEB 812 6120-02 11-21

11.6 Analog Value Conversion: Function Blocks FB250 and FB251

11.6.1 Reading in and Scaling an Analog Value - FB250 -
Function block FB250 reads in an analog value from an analog input module and outputs a value XA
in the scale range specified by the user.
Specify the type of analog value representation for the module (channel type) in the KNKT
parameter (see Table 11-17). Define the desired range using the “upper limit” (OGR) and "lower
limit” (UGR) parameters.
Parameter Explanation Type Assignment STL
BG Slot number D KF 0 to 7 : JU FB 250

NAME : RLG:AI
KNKT Channel number D KY KY = x,y
BG :
Channel type x = 0 to 3
KNKT :
y = 3 to 6
OGR :
3: Absolute value
UGR :
representation
EINZ :
(4 to 20 mA)
XA :
4: Unipolar represen-
FB :
tation
BU :
5: Bipolar absolute value
6: Bipolar fixed-point
number
OGR Upper limit of the output D KF -32767 to +32767
value
UGR Lower limit of the output D KF -32767 to +32767
value
EINZ Single scan I BI Not relevant
XA Output value QW Scaled analog value is “0”
on wirebreak
FB Error bit Q BI “1” on wirebreak, illegal
channel or slot number or
illegal channel type
BU Range violation Q BI “1” when nominal range is
exceeded
Scaled range Representation of

the analog input
module
User scaled range
UGR OGR
Figure 11-11. Scaling Schematic for FB250
11-22 EWA 4NEB 812 6120-02

Example: Display of Tank Make-Up Quantity

The make-up of a cylindrical tank holding 30 m3 is to be shown on a 3-digit display. The individual
digits must be set in BCD.
The level of the liquid in the tank is sensed by a SONAR-BERO®, range 80 to 600 cm, with analog
output (see Catalog NS3).
SONAR-BERO PS CPU
I=4 to 20 mA
AI AQ DQ DQ
80 cm
Gap
1 0. 5 m3
600 cm
Tank Tank level 3-digit BCD display
Figure 11.12 Schematic for “Display of Tank Make-Up Quantity”
The analog output of the SONAR-BERO delivers a constant current in the range 4 to 20 mA
proportional to the gap between sensor and liquid. This current is routed to the 4 to 20 mA
analog input module in slot 0, channel 0.
FB250 converts the range 4 to 20mA to the range 0 to 30.0 m3.

The value is stored in flag word 1 as a fixed-point number. Initialization takes place in the
calling block. FB241 converts the fixed-point number into a BCD number.
4 mA 12 mA 20 mA Nominal range of the

analog module
Range set by
user
0 m3 15.0 m3 30.0 m3
Figure 11-13. Conversion of the Nominal Range into the Defined Range
EWA 4NEB 812 6120-02 11-23

STL Explanation
JU FB 250 Unconditional call FB250

NAME : RLG:AI
BG : 0 Slot 0
KNKT : 0.3 Channel 0, channel type 3
OGR : 300 Upper limit: 30.0 m3
UGR : 0 Lower limit: 0.0 m3
EINZ : No meaning
XA : FW1 Make-up quantity stored in flag word 1 as fixed-point number
FB :F0.0 “1”, if wire break
BU :F0.1 “1”, if tank too full
JU FB 241 Conversion of fixed-point number into
. . . BCD number
The BCD number is stored in flag bytes 11 to 13. Output is via two 8-channel digital output
modules in slots 2 and 3. The BCD tetrads 5 and 6 stored in flag word 11 need not be output
since the number has only three digits.
STL Explanation
. . .
L FW12 Read tetrads 0 to 3 of the BCD number
T QW2 and transfer to output modules.
BE
11-24 EWA 4NEB 812 6120-02

11.6.2 Output of Analog Value - FB251 -

Analog values can be output to analog output modules using this function block. In doing so, values
from the range between the lower limit (UGR) and high limit (OGR) parameters are converted to the
nominal range of the module in question.
Parameter Explanation Type Assignment : JU FB 251

NAME : RLG:AQ
XE Analog value to be IW Input value (two's XE :
output complement) in the BG :
range UGR to OGR KNKT :
OGR :
BG Slot address D KF 0 to 7
UGR :
KNKT Channel number D KY KY = x,y FEH :
Channel type x = 0;1 BU :
y = 0;1
0: unipolar repre-
sentation
1: bipolar fixed-point
number
OGR Upper limit of the output D KF -32767 to +32767

value
UGR Lower limit of the output D KF -32767 to +32767
value
FEH Error in limit value Q BI “1” if UGR = OGR,
setting invalid channel or slot,
or invalid channel type
BU Input value exceeds Q BI “1” if XE lies outside
UGR or OGR limits (UGR; OGR).
XE assumes the limit
value
Example: Display of Tank Contents on an Analog Measuring Instrument
The make-up quantity of a 30 m3 tank is stored in flag word 1 as a fixed-point number (see example
FB250). The ± 20 mA analog output module in slot 1, channel 0, transfers the standardized value
to the measuring instrument. The value is displayed within the range 0 to 20 mA.
PS CPU
AQ
Figure 11-14. Schematic for “Display of Tank Contents”
EWA 4NEB 812 6120-02 11-25

The tank contents are determined from the make-up quantity.
STL Explanation
L KF +300 Maximum tank capacity

L FW 1 Make-up quantity
-F Calculate difference
T FW 20 Store tank contents in FW20
...
The UGR and OGR parameters of FB 251 refer to the nominal range of the analog output module.
For this reason, the UGR parameter must be assigned the value -30.0.
Tank contents
- 30.0 m3 0.0 m3 30.0 m3
- 20 mA 0 mA 20 mA
Figure 11-15. Transformation of the Analog Value to the Nominal Range
STL Explanation
...
JU FB251 Unconditional call-up FB251
NAME :RLG:AQ
XE :FW20 Tank contents
BG :1 Slot 1
KNKT :0.1 Channel 0, channel type 1
OGR :300 High limit 30.0 m3
UGR :-300 Low limit - 30.0 m3
FEH :F0.2 “1”, if wire break
BU :F0.3 “1”, if tank too full
BE
11-26 EWA 4NEB 812 6120-02

12 The Integral Real-Time Clock, for CPU 103 Version 8MA02 and Higher
12.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 1
12.2 Setting Parameters in DB1, for CPU 103 Version 8MA03

and Higher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.1 Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 2
12.2.2 Reading the Current Clock Time and the Current Date . . . . . . . . . . 12 - 3
12.2.3 DB1 Parameters Used for the Integral Real-Time Clock . . . . . . . . . . 12 - 4
12.3 Programming the Integral Real-Time Clock in DB1,

12.3.1 Setting the Clock in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 5
12.3.2 Setting the Prompt Time in DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6
12.3.3 Setting the Operating Hours Counter in DB1 . . . . . . . . . . . . . . . . . 12 - 7
12.3.4 Entering the Clock Time Correction Factor in DB1 ............. 12 - 7
12.4 Structure of the Clock Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 8
12.5 Structure of the Status Word and How to Scan it .............. 12 - 12
12.6 Setting Parameters for the Clock Data Area and the Status Word
in the System Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 15
12.7 Programming the Integral Real-Time Clock in the

User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.1 Reading and Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 21
12.7.2 Programming the Prompt Function . . . . . . . . . . . . . . . . . . . . . . . . 12 - 25
12.7.3 Programming the Operating Hours Counter . . . . . . . . . . . . . . . . . . 12 - 30
12.7.4 Entering the Clock Time Correction Factor . . . . . . . . . . . . . . . . . . . 12 - 35
EWA 4NEB 812 6120-02

Figures
12-1 DB1 with Default Parameters for Integral Real-Time Clock . . . . . . . . . . . . . 12 - 2

12-2 Example: Setting the Clock in DB1 to Monday, November 9, 1992, 15:30 . . . 12 - 5
12-3 Example: Setting the Prompt Time in DB1 to
Thursday, December 17, 1992, 8:00 o'clock ....................... 12 - 6
12-4 Setting the Operating Hours Counter in DB1 to 1600 Hours ............ 12 - 7
12-5 Entering a Correction Factor of +90s in DB1 . . . . . . . . . . . . . . . . . . . . . . . 12 - 7
12-6 How DB1 or the Control Program and the Clock Access the Clock
Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 8
12-7 Flowchart - Transferring Time and Date Settings to the Clock . . . . . . . . . . . 12 - 20
12-8 Flowchart - Transferring New Prompt Time Settings ................. 12 - 26
12-9 Flowchart - Transferring Settings to the Operating Hours Counter . . . . . . . . 12 - 31
Tables
12-1 Reading the Current Clock Time and Current Date . . . . . . . . . . . . . . . . . . . 12 - 3

12-2 DB1 Parameters for the Integral Real-Time Clock . . . . . . . . . . . . . . . . . . . . 12 - 4
12-3 Clock Data in the Clock Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 9
12-4 Range Definitions for Clock Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 10
12-5 Significance of Bits 0, 1, 2, and 3 of the Status Word . . . . . . . . . . . . . . . . . 12 - 13
12-6 Significance of Bits 4 and 5 of the Status Word . . . . . . . . . . . . . . . . . . . . . 12 - 13
12-7 Significance of the Operating Hours Counter Flags Bits 8, 9, and 10
of the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 14
12-8 Significance of the Prompting Time Flags Bits 12, 13, and 14 of the
Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 14
12-9 The System Data Area for the Integral Real-Time Clock . . . . . . . . . . . . . . . 12 - 15
12-10 FB1 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 17
12-11 OB21 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 18
12-12 OB22 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 18
12-13 DB75 Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 18
12-14 FORCE VAR Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 19
EWA 4NEB 812 6120-02

S5-100U The Integral Real-Time Clock
12 The Integral Real-Time Clock, for CPU 103

Version 8MA02 and Higher
12.1 Function
The integral real-time clock offers the following possibilities of controlling the process sequence:
• Clock and calendar function
- Used to configure clock-time dependent control, for example
• Prompt and alarm function
- Used to monitor the duration of a process, for example
• Operating hours counter
- Used to monitor inspection intervals, for example
The clock begins running when you supply voltage to the programmable controller. The default is
April 1, 1992, 12:00 o’clock. You set the clock by setting its parameters.
There are two possibilities.

• With CPU 103 version 8MA03, you can set the clock parameters in DB1 (see section 12.2).
• With CPU 103 version 8MA02 and higher, you can set the clock parameters in the system data
area (see section 12.6) and program the clock in the user program (see section 12.7).
The hardware clock requires a clock data area and a status word in order to function. The location
of both the clock data area and the status word must be stored in system data 8 to 10.
Operating Principle of the Clock

Data exchange between the integral real-time clock and the control program always goes through
the clock data area. The clock stores current values for time, date, and operating hours counter in
the clock data area. You can transfer into the clock data area the values for the time, date, prompt
time, and operating hours counter that you want the clock to use.
You can scan the status word to identify setting errors, for example. Or you can change certain
status word bits to deliberately disable or enable transfer or read operations.
Refer to sections 12.4 and 12.5 for additional information about the clock data area and the status
word. These sections are especially important if you want to set clock parameters in the system
data. If you are new to SIMATIC, you may prefer to set clock parameters in DB1.
EWA 4NEB 812 6120-02 12-1

The Integral Real-Time Clock S5-100U
12.2 Setting Parameters in DB1, for CPU 103 Version 8MA03 and Higher
Set the clock parameters in DB1 to be able to use the clock functions. Follow the same rules you
used in setting parameters for other functions. Refer to section 9.1.
Procedures for Setting Parameters in DB1

1. Perform an overall reset.
2. Output default DB1 to the programmer.
3. Use the cursor to jump into the clock parameter block.
4. Change the parameters.
Every time there is a change from STOP to RUN, the programmable controller accepts the new
clock data.
Note
The system data contents are deleted during an overall reset. The clock continues to run
internally with the current values.
The clock time is updated one second after the next cycle starts.
12.2.1 Defaults
The following values are preset in the parameter block when you output the default DB1.
36: KS ='PGN 01 ; #CLP: CF 0 ';

48: KS ='CLK DB5 DWO STW ';
60: KS ='MW102 STP Y SAV Y ';
72: KS ='OHE N SET 4 01.04.92 ';
84: KS ='12:00:00 TIS 4 ';
96: KS ='01.04. 13:00:00 OHS ';
108: KS ='000000:00:00 # ; SDP: WD';
Figure 12-1. DB1 with Default Parameters for Integral Real-Time Clock
After the CLP block ID for the integral real-time clock, the CLK parameter defines the location of the
clock data (in DB5 beginning with DW0, for example). The STW parameter specifies the location of
the status word (in flag word MW102, for example). You must specify both parameters if you want
to read the clock.
Section 12.2.2 describes the procedures you must follow to read the clock.
Section 12.2.3 lists all of the parameters that you can use for the integral clock.
12-2 EWA 4NEB 812 6120-02

12.2.2 Reading the Current Clock Time and the Current Date
Proceed as follows to see how and with which values the clock runs.
1. Perform an overall reset.
2. Output DB1 to the programmer.
3. Overwrite both (#) comment characters with a blank space.
4. Generate DB5 with DW0 to DW21. See Table 12-3 for information about storing the current
clock time and current date.
5. Switch the programmable controller from STOP to RUN. The clock accepts the values present
in DB1.
6. Enter DB5 and DW0 to DW3 on the programmer by using the FORCE VAR function.
7. Press the “ENTER” key twice. The clock runs using the current values.
Table 12-1. Reading the Current Clock Time and Current Date
Operand Signal States Explanation
DB 5
DW 0 KH = 0004 Wednesday
DW 1 KH = 0104 October 1
DW 2 KH = 9212 1992, 12:00
DW 3 KH = 0000
EWA 4NEB 812 6120-02 12-3

12.2.3 DB1 Parameters Used for the Integral Real-Time Clock
Table 12-2. DB1 Parameters for the Integral Real-Time Clock
Parameters Argument Meaning
Block ID: CLP: Clock Parameters
CF p Entering the correction factor (Correction Factor)
CLK DBxDWy, MWz,EWv Location of the clock data (CLocK Data)

or AWv
STW DBxDWy, MYz,EWv Location of the status word (STatus Word)

or AWv
STP J/Y/N Updating the clock during STOP (SToP)
SAV J/Y/N Saving the clock time after the last change
from RUN to STOP or Power OFF (SAVe)
OHE J/Y/N Enabling the operating hours counter

(Operating Hours counter Enable)
SET wd dd.mm.yy Setting the clock time and date

hh:mn:ss1 AM/PM2
TIS wd dd.mm. Setting the prompt time (TImer Set)

hh:mn:ss1 AM/PM2
OHS hhhhhh:mn:ss1 Setting the operating hours counter

(Operating Hours counter Set)
wd = 1 to 7 (weekday = Sun. - Sat.) p = – 400 to 400

dd = 01 to 31 (day) v = 0 to 126
mm = 01 to 12 (month) x = 2 to 255
yy = 0 to 99 (year) y = 0 to 255
hh = 00 to 23 (hours) z = 0 to 254
mn = 00 to 59 (minutes) j/J = yes
ss = 00 to 59 (seconds) y/Y = yes
hhhhhh = 0 to 999999 (hours) n/N = no
1 If an argument such as seconds, for example, is not to be entered, enter XX. The clock continues to run
with the current data. The TIS parameter block does not acknowledge this argument.
2 If you enter AM or PM after the clock time, the clock runs in the 12-hour mode. If you omit this argument,
the clock runs in the 24-hour mode. You must use the same time mode in the SET and TIS parameter
blocks.
12-4 EWA 4NEB 812 6120-02

12.3 Programming the Integral Real-Time Clock in DB1, for CPU 103
Version 8MA03 and Higher
Sections 12.3.1 to 12.3.4 contain examples for programming the clock in DB1. Adhere to the rules
described in chapter 9 for setting parameters when you enter these examples into the programmable
controller.
Note
If the programmable controller recognizes a parameter setting error in DB1, the
programmable controller remains in the STOP mode even after it has been switched
from STOP to RUN. The red LED is lit.
12.3.1 Setting the Clock in DB1
How to set the clock in DB1

2. Generate DB5 with DW0 to DW21.
4. Overwrite the comment characters (#) with a blank space.
5. Use the cursor to jump to the CLP parameter block.
6. Enter the example.
- Set the clock to the following date: Monday, November 9, 1992, 15:30.
Setting the Clock Explanation
36: KS ='PGN 01 ; CLP: CF 0 ';

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48: KS ='CLK DB5 DW0 STW '; The clock data is stored in data block 5 beginning
with data word DW0. The status word is located in
flag word MW 102.
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60: KS ='MW102 STP Y SAV Y '; The clock is updated when the programmable
controller is in the STOP mode. The clock time is
saved in the clock data area. See Table 12-3.
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72: KS ='OHE N SET 2 09.11.92 '; After the SET parameter, enter the weekday, the
date, and the clock time you want the clock to use
when it begins running. Be certain to include the
blank spaces.
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84: KS ='15:30:00 TIS 4 '; The clock runs in the 24-hour time mode since
you do not enter either AM or PM.
Figure 12-2. Example: Setting the Clock in DB1 to Monday, November 9, 1992, 15:30

Each time the programmable controller is switched from STOP to RUN, it accepts the new clock
data.
EWA 4NEB 812 6120-02 12-5

12.3.2 Setting the Prompt Time in DB1
How to set the prompt time in DB1

5. Use the cursor to jump into the CLP parameter block.
- Set the clock to the following prompt time: Thursday, December 17, 1992, 8:00 o’clock.
Setting the Prompting Time Explanation
36: KS ='PGN 01 ; CLP: CF 0 ';

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48: KS ='CLK DB5 DW0 STW '; The clock data is stored in data block 5 beginning
with data word DW0. The status word is located in
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60: KS ='MW102 STP Y SAV Y '; flag word MW 102.

The clock is updated when the programmable
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84: KS ='12:00:00 TIS 5 '; After the parameter for TIS, enter the weekday,
date and time to initiate the prompt time.
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96: KS ='17.12. 08:00:00 PM OHS '; You can enter the parameter for the clock mode.
The clock runs in the 24-hour time mode.
Figure 12-3. Example: Setting the Prompt Time in DB1 to Thursday, December 17,
1992, 8:00 o’clock

Each time the programmable controller is switched from STOP to RUN, it accepts the new clock
data.
12-6 EWA 4NEB 812 6120-02

12.3.3 Setting the Operating Hours Counter in DB1
How to set the operating hours counter in DB1

5. Use the cursor to jump to the CLP parameter block.
- You are setting the start value for the operation hours counter to 1600 hours.
Setting the Operating Hours Counter Explanation

36: KS ='PGN 01 ; CLP: CF 0 '; The clock data is stored in data block 5 beginning
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48: KS ='CLK DB5 DW0 STW '; with data word DW0. The status word is located in
flag word MW 102.
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60: KS ='MW102 STP Y SAV Y '; The clock is updated when the programmable
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72: KS ='OHE Y SET 4 01.04.92 '; The operating hours counter is enabled.
.
.
.
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96: KS ='01.04. 13:00:00 OHS '; After the OHS parameter, enter the start value for
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108: KS ='001600:00:00 ; SDP: WD'; the operating hours counter.

Figure 12-4. Setting the Operating Hours Counter in DB1 to 1600 Hours

Each time the programmable controller is changed from STOP to RUN, it accepts the new clock
data.
12.3.4 Entering the Clock Time Correction Factor in DB1

The exactness of the clock is temperature-dependent. You can configure a correction value to
increase the clock’s exactness. The correction value is output in s/month. You must measure how
many seconds per month the clock runs fast or slow. A month is defined as 30 days.
Example: Your measurements indicate the clock is 12 s too slow in 4 days. That would be 90 s
too slow in 30 days. The correction value is +90 s/month.
In addition to the changed clock parameters, enter the example into DB1 as follows:
Enter the Clock Time Correction Factor Explanation

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36: KS ='PGN 01 ; CLP: CF +90 '; The correction value of +90 s is loaded into the
clock.
Figure 12-5. Entering a Correction Factor of +90 s in DB1
EWA 4NEB 812 6120-02 12-7

12.4 Structure of the Clock Data Area
You need only to change the default values in DB1 to program the clock in DB1. See section 12.2.
During start-up, the DB1 interpreter writes all information into the system data area.
TIP: Do not attempt to set parameters in the system data, or to access directly from the user
program unless you have extensive knowledge of the system.
You must store the location of the clock data area in system data 8 and 9.
Data exchange between DB1 or the control program and the integral real-time clock is always
through the clock data area.
• The integral real-time clock stores current time, date, and operating hours counter values in the
clock data area (flag area, data block, input area, or output area).
• DB1 and the control program store the settings for prompt times and operating hours counters in
the same data area.
The control program can only read from or write to the clock data area. The control program can
never access the clock directly. Figure 12-6 illustrates the relationship between DB1 or the control
program, the clock data area, and the integral real-time clock.
Clock data area
Current clock
time/date
(words 0 to 3)
Settings
clock time/date
(words 4 to 7)
Prompt time
DB1/ (words 8 to 11)
Integral real-
Control
time clock
program
Current operating
hours count
(words 12 to 14)
Settings operating
hours counter
(words 15 to 17)
Clock time/date of
the last switch from
RUN to STOP
(words 18 to 21)
Reading clock data The clock writes clock data

in the clock data area
The clock accepts the settings

Transferring settings from the clock data area
Figure 12-6. How DB1 or the Control Program and the Clock Access the Clock Data Area
12-8 EWA 4NEB 812 6120-02

When you set the clock, you have to transfer only the data needed to implement a particular
function. For example, if you want to change only the clock function data, you do not have to enter
data for the time prompt function or for the operating hours counter.
The clock data area has the same structure wherever it is located: in the data block area, the flag
area, the input area, or the output area. Table 12-3 provides you with information about where
specific clock data is located within the clock data area. The explanations for Table 12.3 follow the
table.
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Table 12-3. Clock Data in the Clock Data Area

Clock Data
Area Meaning Left Flag Word Right Flag Word
(Data Word)
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0 Current clock Weekday

time/date ---
1 Day Month
2 Year AM/PM (Bit 7) Hour
3 Minute Second
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4 Settings for clock Leap year* Weekday

time/date
5 Day Month
6 Year AM/PM (Bit 7)** Hour
7 Minute Second
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8 Time prompt --- Weekday
9 Day Month
10 --- AM/PM (Bit 7)**Hour
11 Minute Second
12 Current operating --- Second

hours
13 Minutes Hour
14 Hours · 100 Hours · 10,000
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15 Settings for --- Second

operating hours
16 Minutes Hours
counter
Hours · 100 Hours · 10,000
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17
18 Clock time/date after --- Weekday
a switch from RUN to
19 STOP or Power OFF Day Month
20 (only if bit 5 in the Year AM/PM (Bit 7)** Hour

status word = 1)
21 Minute Second
* Relevant when programming the clock in the user program (see Table 12-4)
** Significant only in the 12-hour mode Bit 7=1 means PM, bit 7=0 means AM
EWA 4NEB 812 6120-02 12-9

Make certain you are aware of the following points when you make inputs into the clock data area.
• Entries into the clock data area must be in BCD code.
• The clock runs either in the 12-hour mode or the 24-hour mode depending on how you set bit 1
in the status word. See section 12-5 for additional information.
• The AM/PM flag (0 = AM, 1 = PM) is significant only for the 12-hour mode of the hardware
clock. The AM/PM flag corresponds to bit 7 in words 2, 6, 10, and 20.
- In the 12-hour mode, you have to set the hours and the AM/PM flag for both the clock and
prompt functions.
- In the 24-hour mode, if you set an AM/PM flag when you enter the values for the clock and
prompting time, then the program sets the relevant error bit.
• The clock settings you enter must be within the range defined in Table 12-4.
Table 12-4. Range Definitions for Clock Data

Variable Permissible Parameters Variable Permissible Parameters
Seconds 0 to 59 Day 1 to 31
Minutes 0 to 59 Month 1 to 12
Hours In the 24-hour mode: Year 0 to 99
0 to 23
Leap Year 0 to 3
In the 12-hour mode:
for AM: 1 to12 0 = Leap year is current
(12 = 12 o’clock noon) year
for PM: 81 to 92
1 = Leap year was last year
(81 = 1 o’clock PM)
0 to 999999 when 2 = Leap year was two
entering the operating years ago
hours
3 = Leap year was three
Weekday 1 to 7 years ago
1=Sunday
2=Monday
3=Tuesday
4=Wednesday
5=Thursday
6=Friday
7=Saturday
12-10 EWA 4NEB 812 6120-02

If your inputs differ from the ones described, the operating system outputs error messages that are
displayed in the status word. The operating system resets error messages displayed in the status
word the next time you set the clock, prompt time, or the operating hours counter, if the new
settings are within the definition range. See section 12.5.
If you do not wish to modify one of the setting values, you can enter at its place XX (ASCII code) in
DB1, or FF (hexadecimal code) when you are programming in the system data.
If the clock data area is located at the end of other areas (flags, data blocks, inputs, and outputs)
and there is insufficient memory space available for the clock data area, the amount of clock data
transferred is only as much as will fit in the area available. Settings are not accepted if they lie
outside of the available space.
• If clock data is located in the non-retentive flag area, then the following two events occur:
- All the settings are lost after Power OFF and cold restart.
- The time the last switch from RUN to STOP occurred is lost.
• Remember that you can decide where to locate the clock data area. The word numbers listed in
Table 12-3 are relative.
- If your clock data area is located in a data block and does not begin with data word DW0 but
DWX, then you must add the value X to the word number shown in Table 12-3.
Example: Your clock data area begins with DW124. The data for the time and date is then
stored in DW124 to DW127.
- If you locate your clock data area in the flag area beginning with flag word 0, then you must
multiply the appropriate data word number listed in Table 12-3 by a factor of 2 to obtain the
appropriate flag word address.
Example: You locate your clock data area in the flag operand area beginning with flag
word 0. Data for the operating hours counter is then stored beginning with the
FW24 address.
- If your clock data area does not begin at flag word 0, you have to add the beginning value to
the word number shown in Table 12-3.
EWA 4NEB 812 6120-02 12-11

12.5 Structure of the Status Word and How to Scan it
You can scan the status word to identify errors in the entered settings. You can deliberately change
certain bits in the status word to enable or disable transfer or read operations. You can use
designated flag bits to govern the clock’s behavior when the programmable controller is switched
from the RUN to the STOP mode or during Power OFF.
• The status word can be located in the flag area or in a data block. You must define the location
of the status word in DB1 or directly in system data 9 and 10. See section 12.6.
• The integral real-time clock runs independently of the set operating mode. Access to the clock
data area depends on the set operating mode and the signal states of bits 4 and 5 in the status
word. You can set or reset these bits using the “S” or “R” operations in the control program.
- If you use an operator panel, such as the OP 396, to monitor the program, it is an
advantage to have the programmable controller update the clock time (the current date)
even in the STOP mode.
• The operating system resets the “transfer settings” bits (bits 2, 10, and 14 in the status word)
under the following conditions.
- The settings have been transferred.
- The settings have not been transferred because they were outside of the permissible
range. The corresponding error bits (bits 0, 8, and 12 in the status word) are set.
• The operating system does not reset the “transfer settings” bits (bits 2, 10, and 14 in the status
word) under the following conditions.
- The system data for the clock is either incorrect or not available.
- The clock data area is too small.
- The clock is defective (hardware error).
• There are four types of bits in the status word.

- Clock flags
- Operating system flags
- Operating hours counter flags
- Prompt time flags
12-12 EWA 4NEB 812 6120-02

Tables 12-5 through 12-8 provide you with information about the significance of the signal states of
the respective flags.
Clock Flags
Table 12-5. Significance of Bits 0, 1, 2 and 3 of the Status Word

Bit Number Signal State Meaning
1 Error in setting entry
0
0 No error in setting entry
1 12-hour clock mode
1
0 24-hour clock mode
1 Transfer settings
2
0 Do not transfer settings
1 The clock time can be read
3
0 The clock time cannot be read
Operating System Flags
Table 12-6. Significance of Bits 4 and 5 of the Status Word

Bit Number Signal
Operating Meaning
Status State
Mode Word
STOP 4 1 The clock updates only words 0 to 3 (current time/date) in
the clock data area. You can set the clock by using the
FORCE VAR programmer function.
0 The clock does not update the clock data area. Words 0
to 3 contain the time at which the last switch from RUN to
STOP occurred.
5 1 Words 18 to 21 contain the time at which the last RUN to

STOP switch occurred or the time at which the last
Power OFF occurred if bit 4 is also set.
0 Words 18 to 21 are not used.
RUN 4 1/0 The clock continually updates the clock data area
(Words 0 to 17).
5 1 Words 18 to 21 contain the time at which the last switch

from RUN to STOP occurred or the time at which the last
Power OFF occurred.
0 Words 18 to 21 are not used.
EWA 4NEB 812 6120-02 12-13

Operating Hours Counter Flags
Table 12-7. Significance of the Operating Hours Counter Flags Bits 8, 9, and 10 of the
Status Word
8
1 Enable the operating hours counter
9
0 Disable the operating hours counter
1 Transfer the settings
10
0 Do not transfer the settings
Prompt Time Flags
Table 12-8. Significance of the Prompt Time Flag Bits 12, 13, and 14 of the Status Word

12
1 The set prompting time is reached
13
0 The set prompting time is not reached
1 Transfer the settings
14
0 Do not transfer settings
The operating system requires bit numbers 6, 7, 11, and 15. You can not use these bits.
Scanning the Status Word

In a data block, you can use the “P <data word number> <bit number>” operation to scan the
individual bits of a data word. In the flag area, you can scan the individual bits if you enter the
<byte address> and the <bit number>.
Example: The status word is stored in DW13. You are checking to see if the set prompt time has
been reached. The “P D 13.13” instruction triggers a scan. If the status word is stored
in FW12, then the same scan would be “A F 12.5”.
Backup of the Hardware Clock

If there is a backup battery, the clock continues to run even after Power OFF. If the programmable
controller does not have a backup battery, the clock values will be set at “April 1, 1992, 12.00.00
o’clock, weekday: 4” when the clock is initialized after a Power ON. The default is the 24-hour time
mode. You should install a battery only during Power ON; otherwise, you would lose the clock data.
12-14 EWA 4NEB 812 6120-02

12.6 Setting Parameters for the Clock Data Area and the Status Word in
the System Data Area
Table 12-9. The System Data Area for the Integral Real-Time Clock
Absolute System
Permissible
Address RAM Data Word Meaning
Parameters
8 Operand area for the clock data ASCII characters

EA10
I, Q, F, D
Start address for the clock data DB number
EA11
Operand area D DB2 to DBFFH
Operand Areas I, Q, F Byte address
9 Start address for the clock data DB word number
EA12
Relevant only for operand area D DW0 to DWFFH
Operand area for the status word ASCII characters

EA13
I, Q, F, D
10 Start address for the status word DB number

EA14
Operand area D DB2 to DBFFH
Operand areas I, Q, F Byte address
Start address for the status word DB word number

EA15
Relevant only for operand area D DW0 to DWFFH
11 Status for hardware1 “0”, “1”

EA16
(only bits 0 and 1 are relevant)
• If either bit 0 or bit 1 is set, the
clock chip is defective
• If no bit is set, the clock chip is
running
11 Incorrect correction value? “0”, “1”
EA16
(only bit 15 is relevant)
• If bit 15 is set, the correction value
is incorrect (>+400 or <- 400)
• If bit 15 is not set, the correction
value is correct
EA18 12 Correction value2 - 400 to 400
1 You can scan SD11 during start-up. You must call up an FB in OB21 or OB22 by using “L RS 11” to read
out and then continue processing SD11.
2 Always use the “L KF X” instruction to load the correction value in ACCU 1 since negative values can
also be specified.
EWA 4NEB 812 6120-02 12-15

The following section is intended to help you to start running the integral real-time clock as quickly
as possible by setting parameters in the system data. You need to be familiar with the clock data
area described in sections 12.4 and 12.5 in order to understand this section.
Note
The clock time is updated one second after the start of the next cycle.
Task:
You want to set the clock to the following values:

Wednesday, 12.02.92; 10:30:00
The status word is assigned to flag word FW12. Clock data is stored in DB75 beginning with DW0.
The two ways to transfer clock settings are as follows:
• Use the STATUS VAR programmer function when the programmable controller is in the RUN
mode.
• Use the FORCE VAR programmer function when the programmable controller is in the STOP
mode and status word bit 4 = 1.
The following example uses the first method. Proceed as follows:

1. Set the programmable controller to Power OFF.
3. Set the programmable controller to Power ON.
4. Perform an overall reset on the programmable controller. See section 4.1.3.
5. Use the following program to program the programmable controller.
6. Set the operating mode switch to RUN.
The integral real-time clock is running.
Program Structure:
The system data is defined during the change from

OB21 FB1 STOP to RUN.
The system data is defined when the programmable

OB22 FB1 controller is switched on.
FB1 DB75 Set the new date and time.
12-16 EWA 4NEB 812 6120-02

The Block Entry Sequence and a Programming Example:
The following procedure is suggested:

1. Program FB1 - Defining system data for the integral real-time clock
2. Program OB21 - Calling up FB1 during a change from STOP to RUN
3. Program OB22 - Calling up FB1 when the programmable controller is switched on
4. Generate DB75 - Storing clock data
5. Transfer new data to the clock using the FORCE VAR programmer function (programmable
controller in the RUN mode) .
The respective programming examples are shown in Tables 12-10 to 12-14.

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Table 12-10. FB1 Program
STL Meaning Explanation
FB 1
NAME: CLOCK
ASCII Code for the “D” character Clock data is

L KH 4 4 4 B located in
DB75
Block number “75D”
beginning
T RS 8 Storing in system data word 8 with DW0
DW0 is the start address for clock data
L KH 0 0 4 D
ASCII Code for the “M” Character

The status
T RS 9 Storing in system data word 9 word is
located in
Flag word Number “12D”
FW12
L KH 0 C 0 0
ASCII Code is irrelevant

T RS 10 Storing in system data word 10
BE
EWA 4NEB 812 6120-02 12-17

Table 12-11. OB21 Program
STL Explanation
OB 21
JU FB 1 The function block is called up once during a switch from STOP to
NAME: CLOCK RUN.
BE
Table 12-12. OB22 Program
STL Explanation
OB 22
JU FB 1 The function block is called up once when the programmable
NAME: CLOCK controller is switched on.
BE
Table 12-13. DB75 Program
STL Explanation
DB 75
0: KH = 0000; Define the number of data words. (Data words 0 to 7 are used in
1: KH = 0000; the example. See Table 12-3) . Define the numerical
2: KH = 0000; representation. Hex is used in the examples.
3: KH = 0000;
4: KH = 0000;
5: KH = 0000;
6: KH = 0000;
7: KH = 0000
12-18 EWA 4NEB 812 6120-02

Reading and Setting the Time and Date
After you enter the program, you can test it as follows.
1. Switch the programmable controller to the RUN mode.
2. Use the FORCE VAR programmer function to enter the following.

- Data block number
- Data words DW0 to DW7
- Clock data
- Status word
3. Begin status processing by pressing the ENTER key twice. Bit 2 in the status word is reset. The
clock runs with the new settings
Table 12-14. FORCE VAR Function
Operand Signal States Explanation
DB 75
DW 0 KH = 0003 Tuesday
DW 1 KH = 0110 October 1
DW 2 KH = 9112 1991, 12 o’clock
DW 3 KH = 0000 (reading current clock data)
DW 4 KH = 0002 Monday
DW 5 KH = 0212 December 2
DW 6 KH = 9210 1992, 10.30 o’clock
DW 7 KH = 3000 (writing new settings)
FW 12 KM = 00000000 00000100 If you set bit 2 in the status word to
“1”, the new settings are transferred
to the clock.
Note
Besides using the method described in Table 12-14 (with the FORCE VAR function), you
can also enter the new settings directly into the data block. In that case, store the new
settings in data words DW4 to DW7 of data block DB75.
See Table 12-13.
EWA 4NEB 812 6120-02 12-19

Write the settings into the

clock data area
Set transfer bit 2 in the

control program
*
Wait approximately two seconds
(entering a wait program)
Possible errors: yes

Status Word
- Clock is not
Bit 2=1
available.
- Clock system data
is incorrect or not no
available.
- Clock data area is
too small. Status Word yes
Incorrect settings
- Clock is defective. Bit 0=1
no
The clock cannot be The clock runs with The clock continues
used. the new settings. running with the old
Eliminate the errors. values.
* The lower portion of the flowchart has only a diagnostic function. There is nothing you must perform.
You can also implement the upper portion of the flowchart using the FORCE VAR programmer function
(programmable controller in the RUN mode) or using the FORCE function (the programmable controller
is in the STOP mode and bit 4 = 1 in the status word).
Figure 12-7. Flowchart - Transferring Time and Date Settings to the Clock
If you do not want a value (for example the minutes) in the settings to be transferred, enter the value
for relevant byte as either 255D or FFH. When you set the clock, the old value present in the clock is
retained.
Incorrect settings are displayed by a set bit 0 in the status word. The clock continues to run with the
old values.
In a similar manner, you can program new settings for the time prompt function and the operating
hours counter. However, the settings are located in other data words in the clock data area. See
section 12-4. You must set the respective bit to 1 in the status word so that the clock can accept
the new settings. See section 12-5.
12-20 EWA 4NEB 812 6120-02

12.7 Programming the Integral Real-Time Clock in the User Program
The programming of the clock in the user program should be performed only by users with extensive
knowledge of the system. For all other users, use of DB1 is recommended (see sections 12.2
and 12.3).
The following section provides you with information on how to access the clock through the user
program.
12.7.1 Reading and Setting the Clock

Example: Program for setting the time and date
Transfer of the settings for the time and date is triggered by input I 0.0. Before you set input I 0.0
(see OB1), you must transfer these settings to flag bytes FY120 to FY127. Values that you do not
want to change must be preset with “FFH”. You can define the clock mode with input I 1.0(1= 12-
hour mode). Input I 0.1 is the AM/PM bit that you use for setting the 12-hour mode.
The clock data area is in DB2 beginning with DW0, and the status word is FW10.
OB1 STL Explanation
: ================================
: SETTING THE TIME AND DATE
: ================================
: FIRST TRANSFER TIME AND DATE VALUES
: INTO FB120 TO FB127.
:A I 0.0 CLOCK SETTING TRIGGERED
:S F 20.0 BY SETTING F 20.0 (RESET IN FB10)
:JU FB 10
NAME :SET CLOCK (SETTING THE TIME AND DATE)
WDAY : FY 121 WEEKDAY
DAY : FY 122 DAY
MON : FY 123 MONTH
YEAR : FY 124 YEAR
HOUR : FY 125 HOUR
AMPM : I 0.1 AMPM-BIT (ONLY IMPORTANT IN 12-HOUR MODE)
MIN : FY 126 MINUTES
SEC : FY 127 SECONDS
ERR : F 12.1 ERROR BIT
MODE : I 1.0 12-HOUR MODE: I 1.0 = 1
:BE
EWA 4NEB 812 6120-02 12-21

FB10 STL Description

NAME :SET CLOCK SETTING THE CLOCK
DES :WDAY I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :DAY I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :MON I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :YEAR I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :HOUR I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :AMPM I/Q/D/B/T/C: I BI/BY/W/D: BI
DES :MIN I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :SEC I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :ERR I/Q/D/B/T/C: Q BI/BY/W/D: BI
DES :MODE I/Q/D/B/T/C: I BI/BY/W/D: BI
:A =MODE 24HR-MODE = 0, 12HR-MODE = 1

:= F 11.1 (CLOCK MODE STATUS WORD BIT 1)
:AN F 20.0 FLAG IS RESET IF SETTINGS ALREADY
:JC =M001 READ INTO CLOCK DATA AREA
:R F 20.0
:
:C DB 2 CLOCK DATA AREA
:L =WDAY STORE VALUE FOR WEEKDAY
:T DR 4
:L =DAY STORE VALUE FOR DAY
:T DR 5
:L =MON STORE VALUE FOR MONTH
:T DR 5
:L = YEAR STORE VALUE FOR YEAR
:T DL 6
:L =HOUR STORE VALUE FOR HOUR
:ON =AMPM IF 12-HOUR MODE IS SET, AND
:ON =MODE AM/PM BIT = 1 (AFTERNOON), THE
:JC =MORN RELEVANT BIT IN THE CLOCK AREA
:L KH 0080 IS SET
:OW
MORN :T DR 6
:L =MIN STORE VALUE FOR MINUTES
:T DL 7
:L =SEC STORE VALUE FOR SECONDS
:T DR 7
:AN F 11.2 TRANSFER SETTINGS
:S F 11.2 (STATUS WORD IS FW10)
:L KT 020.1 START MONITORING TIME
:SE T 10
M001 :A T 10 BEC, IF MONITORING TIME
:BEC NOT YET ELAPSED
.
12-22 EWA 4NEB 812 6120-02

FB10 STL (continued) Explanation

:AN F 11.2 HAVE SETTINGS BEEN TRANSFERRED?
:JC =M002 IF YES, JUMP TO M002
:S =ERR SET ERROR BIT IF THERE ARE ERRORS
:BEU
M002 :AN F 11.0 WERE THERE ERRORS WHILE ENTERING SETTINGS?
:RB =ERR IF NO, RESET ERROR BIT
:BEC IF NO ERROR, THEN BEC
:S =ERR IF AN ERROR, SET ERROR BIT
:BE
Example: Program for reading the current time and the current date
The time is stored in flag bytes FY30 to FY36, depending on an external event, simulated here by a
positive edge at input I 0.5. Flag F 13.1 indicates which mode the clock is operating in. Flag F 13.0
is the AM/PM bit in the 12-hour mode
The clock data area is in DB2 beginning with DW0, and the status word is FW10.
OB1 STL Explanation

: ================================
: READING TIME AND DATE
: ================================
:A I 0.5 TIME AND DATE ARE
:AN F 0.1 STORED IN FY30 TO FY36 IN CASE OF A
:= F 0.0 POSITIVE EDGE AT I 32.5.
:A I 32.5 (EXTERNAL EVENT)
:= F 0.1
:
:A F 0.0 EDGE TRIGGER FLAG
:JC FB 13
NAME :READ CLOCK (READING TIME AND DATE)
DAY : FY 31 DAY
MON : FY 32 MONTH
YEAR : FY 33 YEAR
HOUR : FY 34 HOUR
AMPM : F 13.0 F 13.0 = 1, AFTERNOON IN 12H-MODE
MIN : FY 35 MINUTES
SEC : FY 36 SECONDS
MODE : F 13.1 F 13.1 = 1, IN 12-HOUR MODE
:BE
EWA 4NEB 812 6120-02 12-23

FB13 STL Explanation

NAME :READ CLOCK READING THE CLOCK
DES :WDAY I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :DAY I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :MON I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :YEAR I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :HOUR I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :AMPM I/Q/D/B/T/C: Q BI/BY/W/D/:BI
DES :MIN I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :SEC I/Q/D/B/T/C: Q BI/BY/W/D/:BY
DES :MODE I/Q/D/B/T/C: Q BI/BY/W/D/:BI
:C DB 2
:L DR 0 WEEKDAY
:T =WDAY
:L DL 1 DAY
:T =DAY
:L DR 1 MONTH
:T =MON
:L DL 2 YEAR
:T =YEAR
:L DR 2 HOUR
:L KH 007F ERASE AM/PM BIT
:AW (ONLY RELEVANT IN 12-HOUR MODE)
:T =HOUR
:TB D 2.7 DISPLAY AM/PM BIT
:= =AMPM (ONLY RELEVANT IN 12-HOUR MODE)
:L DL 3 MINUTE
:T =MIN
:L DR 3 SECOND
:T =SEC
:A F 11.1 DISPLAY CLOCK MODE
:= =MODE MODE = 1, IN 12-HOUR MODE
:BE
12-24 EWA 4NEB 812 6120-02

Storing the Updated Time/Date after a RUN to STOP Switch
Note
This clock data area is only written to if the following requirements are met.
• Bit 5 in the status word is set to “1”.
• A RUN to STOP switch or a Power OFF has taken place.
• The necessary memory space is available in the operand area.
This enables you to detect a RUN to STOP switch or a Power OFF even if the programmable
controller has since gone back to RUN mode. The time and date of the last RUN to STOP switch or
Power OFF are in words 18 to 21 (see Table 12-3)
If several RUN to STOP switches have occurred before you read out this clock data area, you will
only be able to determine the time of the last switch.
If you do not have sufficient memory for this clock data area, you either cannot use this area or use
only part of it. This has no impact on anything else.
12.7.2 Programming the Prompt Function
Transferring Settings to the Clock

• You can store the settings in the clock data area by using transfer operations (see Table 12-3).
• The AM/PM flag (bit number 7) is only significant in 12-hour mode.
Bit 7=1 means PM
Bit 7=0 means AM
• You must transfer the clock data in BCD code.
TIP: The “KC” data format loads a BCD constant into ACCU 1 and is therefore especially
suitable.
• If you enter the value “255D” or “FFH” in a byte as the prompt time, this byte will be ignored
when evaluating “Prompt time reached”. This makes it easy to program, for example, an alarm
that is repeated daily by entering the value in the “255D” or “FFH”in the “Weekday”, “Date”
and “Month” settings.
• You can transfer the prompt time settings to the clock by initiating bit 14 in the status word.
• The settings are transferred 1 second after the start of the next cycle.
• Bit 12 in the status word displays incorrect settings.
EWA 4NEB 812 6120-02 12-25

Write the settings into

the clock data area
Set transfer bit 14

in the control program
*
Wait about two seconds
(entering wait program)
Possible errors: yes

- Clock is not Bit 14=1
available.
- Clock system data
is incorrect or not no
available.
yes Settings
too small. Bit 12=1
- Clock is defective. incorrect
no
The clock cannot Clock runs with Prompt time
be used. the new settings function is turned
Correct the error. for prompt time. off.
* The lower part of the flow chart has only a diagnostic function.
There is nothing you must perform.
Figure 12-8. Flowchart - Transferring a New Prompt Time
12-26 EWA 4NEB 812 6120-02

Prompt Time Sequence

• Bit 13 in the status word is set after the prompt time has elapsed.
• Bit 13 remains set until you reset it in the control program.
• The prompt time can be read at any time.
! Caution
If the prompt time is reached in the STOP mode or during Power OFF, the prompt time
cannot be evaluated. It is always deleted on restart.
Example: Setting and evaluating the prompt time
In the example program, the status of input I 0.6 determines whether the settings for the prompt time
are transferred. Before setting input I 0.6, you must transfer the settings to flag bytes FY130 and
FY135. Enter values that you do not wish to be evaluated as FFH.
You set the clock mode with input I 1.0. Use input I 0.1 to specify the the AM/PM bit for 12-hour
mode.
If the preset prompt time has been reached, set flag F 13.2. If errors are made while entering the
prompt time, the error bit, flag F 12.2, is set.
The clock data is stored in DB2 beginning with data word DW0, and the status word is flag word
FW10.
OB1 STL Explanation
: =========================================
: SETTING AND EVALUATING THE PROMPT TIME
: =========================================
: LOAD VALUES INTO FY130 TO FY135
: FIRST.
:A I 0.6 TRIGGER SETTING OF PROMPT TIME
:S F 20.1 BY SETTING F 20.1 (RESET IN FB11)
:JU FB 11
NAME :SET PROMPT TIME (SET AND EVALUATING PROMPT TIME)
DAY : FY 131 DAY
MON : FY 132 MONTH
HOUR : FY 133 HOUR
AMPM : I 0.1 AMPM-BIT (ONLY IMPORTANT IN 12-HOUR MODE)
ALRM : F 13.2 DISPLAYS THAT PROMPT TIME IS REACHED.
MODE : I 1.0 12-HOUR MODE: I 33.0 = 1
:BE
EWA 4NEB 812 6120-02 12-27


NAME :SET PROMPT TIME SETTING THE PROMPT TIME
DES :WDAY I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :DATE I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :MON I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :HOUR I/Q/D/B/T/C: I BI/BY/W/D: BY
DES :AMPM I/Q/D/B/T/C: I BI/BY/W/D: BI
DES :ALRM I/Q/D/B/T/C: Q BI/BY/W/D: BI
DES :MODE I/Q/D/B/T/C: I BI/BY/W/D: BI
:A =MODE 24 HOUR MODE = 0, 12 HOUR = 1

:= F 11.1 (SET CLOCK MODE)
:A F 10.5 DISPLAY PROMPT TIME REACHED
:S =ALRM (BIT 13 IN STATUS WORD)
:R F 10.5 RESET BIT AFTER EVALUATION
:
:AN F 20.1 FLAG IS RESET IF SETTINGS HAVE ALREADY
:JC =M001 BEEN READ INTO THE CLOCK DATA AREA
:R F 20.1
:
:L =WDAY STORE VALUE FOR WEEKDAY
:T DR 8
:L =DAY STORE VALUE FOR DATE
:T DL 9
:L =MON STORE VALUE FOR MONTH
:T DR 9
12-28 EWA 4NEB 812 6120-02

FB11 STL (continued) Description
:L =HOUR STORE VALUE FOR HOURS

:ON =AMPM IF AM/PM = 1 (AFTERNOON) AND
:ON =MODE 12-HOUR MODE IS SET, THE
:JC =MORN CORRESPONDING BIT IN THE CLOCK
:L KH 0080 DATA AREA IS SET
:OW
MORN :T DR 10
:T DL 11
:T DR 11
:S F 10.6 (BIT 14 IN STATUS WORD FW10)
:SE T 11
M001 :A T 11 BEC, IF MONITORING TIME NOT YET
:BEC ELAPSED
:S =ERR IF ERROR, SET ERROR BIT
:BEU
M002 :AN F 10.4 ERROR WHEN ENTERING SETTINGS?
:BEC BEC, IF NO ERROR
:BE
EWA 4NEB 812 6120-02 12-29

12.7.3 Programming the Operating Hours Counter
You can enable the operating hours counter with bit 9 of the status word. This allows you to
establish, for example, the number of hours a motor has been in operation. The operating hours
counter is active only in the RUN mode.
Transferring Settings to the Operating Hours Counter

You can preset the operating hours counter with a certain start value (e.g. after exchanging the
CPU).
• The clock data must be transferred in BCD code.

TIP: The “KC” data format loads a BCD constant into ACCU 1 and is therefore especially
suitable for entering the settings.
• If you do not want a value (for example minutes) to be transferred, entering the relevant byte as
“255D” or “FFH”. The current value for this variable is then retained.
• After you have transferred the settings to the clock data area, you must set bit 10 in the status
word for the clock to accept the clock data.
• Bit 8 in the status word displays incorrect settings.
12-30 EWA 4NEB 812 6120-02

Write the settings into

the clock data area
Set transfer bit 10

in the control program
*
Wait about two seconds
(entering a wait program)
Possible errors:
- Clock is not yes
Status word
available. Bit 10=1
- Clock system data
is incorrect or not
available. no
too small. yes
Status word Settings
- Clock is defective.
Bit 8=1 incorrect
no
The operating The operating The operating
hours counter hours counter hours counter
cannot be used. runs with the new continues to run
Correct the errors. settings. with old values.
* The lower part of the flow chart has only a diagnostic function.
There is nothing you must perform.
Figure 12-9. Flowchart - Transferring Settings to the Operating Hours Counter
EWA 4NEB 812 6120-02 12-31

Example: Setting the operating hours counter
The status of input I 0.7 determines whether the operating hours counter values are transferred.
You must transfer these values to flag bytes FY136 to FY140 before setting input I 0.7 (not
implemented in the example program). Values that are not to be changed should be preset
with FFH.
Errors are displayed in flag F 12.3. The clock data area is in data block DB2 beginning with data
word DW0, and the status word is flag word FW10.
OB1 STL Explanation
: ===================================
: SETTING THE OPERATING HOURS COUNTER
: ===================================
: LOAD VALUES INTO FY136 TO FY140
:
:A I 0.7 TRIGGER TRANSFER OF SETTINGS FOR
:S F 20.2 OPERATING HOURS COUNTER BY SETTING
: F 20.2
:JU FB 12
NAME :SET OPER. HOURS COUNTER (SETTING THE OPERATING HOURS COUNTER)
HOUR0: FY 138 HOURS
HOUR2: FY 139 HOURS X 100
HOUR4: FY 140 ERRORS X 10000
:BE
12-32 EWA 4NEB 812 6120-02


NAME :SET OPER. HOURS COUNTER SETTING THE OPERATING HOURS COUNTER
DES :HOUR0 I/Q/D/B/T/C: I BI/BY/W/D: BY
:AN F 20.2 FLAG IS RESET IF SETTINGS

:JC =M001 ALREADY READ INTO THE
:R F 20.2 CLOCK DATA AREA
:
:T DR 15
:T DL 16
:L =HOUR0 STORE VALUE FOR HOURS
:T DR 16
:L =HOUR2 STORE VALUE FOR HOURS X 100
:T DL 17
:L =HOUR4 STORE VALUE FOR HOURS X 1000
:T DR 17
:S F 10.2 (BIT 10 IN STATUS WORD FW 10)
:S F 10.1 ENABLE OPERATING HOURS COUNTER
: IF NOT ALREADY ENABLED
:SE T 12
M001 :A T 12 BEC IF MONITORING TIME NOT YET
:BEC ELAPSED
:BEU
M002 :AN F 10.0 ERROR WHEN ENTERING SETTINGS?
:BEC BEC IF NO ERROR
:BE
EWA 4NEB 812 6120-02 12-33

Reading the Current Operating Hours Counter

The current data is stored in words 12 to 14 of the clock data area. You can use load operations to
read out the data.
Example: Reading the operating hours counter
You need to switch off a machine for inspection after every 300 hours of operation. Flag F 12.4 is
set when the machine is switched off. After 300 hours of operation, a jump is made to PB5 to switch
the machine off (not programmed in the example).
The clock data area is in DB2 beginning with flag word FW0, and the status word is flag word FW10.
OB1 STL Explanation
:JU FB 14 EVALUATE OPERATING HOURS COUNTER

NAME :BETR-LES
:
:BE

NAME :BETR-LES READING THE OPERATING HOURS COUNTER
:C DB 2 DB IN WHICH THE CLOCK DATA IS LOCATED.

:A F 12.4 IF AUXILIARY FLAG 12.4 IS SET, OFF.
:BEC THE MACHINE IS ALREADY
: BLOCK END
:L DL 14 LOAD HOUR VALUE X 100 IN ACCU 1
:
:L KC 003 COMPARE TO 3 (=300 HOURS)
:><F
:BEC END IF 300 HOURS NOT YET
: REACHED
:S F 12.4 SET AUXILIARY FLAG
:JU PB 5 JUMP TO PB5 WHEN 300 OPERATING
: HOURS REACHED
:
:BE
12-34 EWA 4NEB 812 6120-02

12.7.4 Entering the Clock Time Correction Factor
You can configure a correction value that increases the exactness of the integral real-time clock.
The correction value is displayed in seconds/month. The month is defined as 30 days.
Absolute Address
Range System Data Word
RAM Memory
EA 18 - 400D to + 400D seconds/month 12
Example: You determined that the clock runs 12 seconds slow in a four day period. That would
be 90 seconds in 30 days. The correction value is+ 90 seconds/month.
Note
Use the data KF format to enter the correction value. You then do not have to convert
the value to other numbering systems.
STL Explanation
FB10
L KF + 90 LOAD THE + 90 SECONDS CORRECTION VALUE INTO ACCU 1 AND STORE IT
T RS 12 IN SYSTEM DATA WORD 12.
BE
Note
The correction value you have entered is read in after the next minute change. If an
error occurs when a setting is entered, bit 15 in system data word 11 is set.
EWA 4NEB 812 6120-02 12-35

13 Connecting the S5-100U to SINEC L1, for CPU 102 and Higher
13.1 Connecting the Programmable Controllers to the

L1 Bus Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2 Setting Parameters in the Programmable Controller

for Exchanging Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1
13.2.1 How to Program in a Function Block, for CPU 102 and Higher . . . . 13 - 2
13.2.2 Setting Parameters in DB1, for CPU 103 and Higher . . . . . . . . . . . 13 - 5
13.3 Coordinating Data Exchange in the Control Program . . . . . . . . . . . 13 - 7

13.3.1 Sending Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 8
13.3.2 Receiving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 9
13.3.3 Programming the Messages in a Function Block . . . . . . . . . . . . . . 13 - 11
EWA 4NEB 812 6120-02

Figures
13-1 Connection of the Bus Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 1

13-2 Programming Example for Setting Parameters in FB1 . . . . . . . . . . . . . . . . 13 - 4
13-3 Data Exchange between Sender and Receiver (Principle) . . . . . . . . . . . . . 13 - 7
13-4 Structure of the Send Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 8
13-5 Structure of the Coordination Byte Send (KBS) . . . . . . . . . . . . . . . . . . . . 13 - 8
13-6 Structure of the Receive Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 9
13-7 Structure of the Coordination Byte Receive (KBE) . . . . . . . . . . . . . . . . . . 13 - 10
13-8 Organization of Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 11
13-9 Programming “Message Processing” in FB2 . . . . . . . . . . . . . . . . . . . . . . 13 - 12
Tables
13-1 SINEC L1 Parameter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 2

13-2 Setting Parameters in the Coordination Byte . . . . . . . . . . . . . . . . . . . . . . 13 - 3
13-3 Setting Parameters for the SINEC L1 Interface . . . . . . . . . . . . . . . . . . . . . 13 - 6
EWA 4NEB 812 6120-02

S5-100U Connecting the S5-100U to SINEC L1
13 Connecting the S5-100U to SINEC L1,

for CPU 102 and Higher
SINEC L1 is a local area network that enables SIMATIC S5 programmable controllers to communi-
cate with each other. This option is available when you are using CPU 102 or higher. It operates
on the master-slave principle.
You will find more exact information on the SINEC L1 in the SINEC L1 manual. You need to
understand the SINEC L1 operating system before continuing with this chapter.
The S5-100U can be connected directly to the SINEC L1 as a slave. The information you need to
perform this operation is explained in this chapter.
13.1 Connecting the Programmable Controller to the L1 Bus Cable
Bus terminal BT 777 is the signal level converter that connects the programmable controller to the
L1 bus cable. The procedure is as follows:
1. Connect the L1 bus cable to bus terminal BT 777.
2. Insert the connector of the bus terminal cable into the PG/OP/SINEC L1 port.
0A 0B 0A 0B 0A 0B
1A 1B 1A 1B 1A 1B
2A 2B 2A 2B 2A 2B
3A 3B 3A 3B 3A 3B
4A 4B 4A 4B 4A 4B
Figure 13-1. Connection of the Bus Cable
13.2 Setting Parameters in the Programmable Controller for Exchanging

Data
The programmable controller requires the following information for the handling of data exchange via
the L1 bus:
• Location of the data to be sent (data block or flag area)
Name: Send Mailbox, abbreviated: SF
• Location of the data to be received (data block or flag area)
Name: Receive Mailbox, abbreviated: EF
EWA 4NEB 812 6120-02 13-1

Connecting the S5-100U to SINEC L1 S5-100U
• Storage location of the coordinating information for sending data (e.g., the message:
“Send Mailbox is enabled”)
Name: Coordination Byte Send, abbreviated: KBS
• Storage location of the coordinating information for receiving data (e.g., the message:
“Receiving data can be read”)
Name: Coordination Byte Receive, abbreviated: KBE
• Programmer number (necessary if you want to transmit programmer functions over the SINEC
L1 local area network), abbreviated: PGN
You can set parameters for the programmable controller for the CPU 102 in the function block, and
for the CPU 103 version 8MA03 in the integrated data block (DB1).
13.2.1 How to Program in a Function Block, for CPU 102 and Higher
You can program the SINEC L1 local area network by first setting the parameters and then
programming the “messages” in the control program (see section 13.3.3)
Setting Parameters in the Function Block

You must define the following in the program:
• Your own programmer number for the programmer bus functions
• Your own slave number
• The data or flag areas reserved by the send and receive mailboxes
• The location of the coordination bytes
You program in the function block by calling up one of the two restart organization blocks (OB21 or
OB22). You store the corresponding parameters in the system data area of the programmable
controller by using the “TNB” block transfer statement. The SINEC L1 parameter block begins at
system data word 57.
Table 13-1. SINEC L1 Parameter Block

System Data High Byte Low Byte Address in
Word System Data Area
SD57 Programmer number Slave number EA72H
(1 through 30) (1 through 30) EA73H
SD58 KBE KBE EA74H

Data identifier DB or flag byte EA75H
SD59 KBE KBS EA76H
Data word Data identifier EA77H
SD60 KBS KBS EA78H
DB or flag byte Data word EA79H
SD61 SF SF EA7AH
Data identifier DB or flag byte EA7BH
SD62 SF EF EA7CH
Data word Data identifier EA7DH
SD63 EF EF EA7EH
DB or flag byte Data word EA7FH
You define the position of the coordination bytes and the starting addresses of the send and receive
mailboxes in each case by three bytes.
13-2 EWA 4NEB 812 6120-02

Table 13-2. Setting Parameters in the Coordination Byte
Meaning Parameters Address in System Data Area
“Flag” data identifier (“F”) 4D EA74H
Flag byte 0 to 127 EA75H

EA76H
“Data word” identifier (“D”) 44 EA77H

Data block 2 to 63 EA78H
Data word 0 to 255 EA79H
The data identifier is in ASCII code.
Overflow
If data packets longer than 64 bytes are received, the information is not written beyond the end of
the receive mailbox. There is no overflow message. The end of the receive mailbox is flag byte
127 in the flag area or the last present data word (in the data block).
Example:
Setting parameters in the S5-100U as slave 1 in function block 1
Definitions:
• “Receive” coordination byte (KBE) Flag byte FY100
• “Send” coordination byte (KBS) Flag byte FY101
• Send mailbox (SF) Data block DB2 from DW0
• Receive mailbox (EF) Data block DB3 from DW0
• Flag bytes FY 64 to 77 are used as buffer areas.
EWA 4NEB 812 6120-02 13-3

STL Explanation
L KF 1 - Load slave number and

T FY 65 store it in flag byte 65
L KH 4D00 - Load “Flag” data identifier and store it
T FW 66 in flag byte 66
L KY 100,0 - Load flag byte 100 and store it
L KH 4D00 - Load “Flag” data identifier and store it
L KY 101,0 - Load flag byte 101 and store it
L KH 4400 - Load “Data word” identifier and store it
L KY 2,0 - Store DB number “2” and DW number “0”
T FW 73 in flag bytes 73 and 74
L KH 4400 - Load “Data word” identifier and store it
L KY 3,0 - Store DB number “3” and DW “0”
T FW 76 in flag bytes 76 and 77
- Transfer flag area FY64 to 67 to the system
data area:
L KH EE4D - Load upper source address
L KH EA7F - Load upper destination address
TNB 14 - Transfer a block of data 14 bytes long
Erase all buffer areas
L KH 0000 - Load hexadecimal number “0000”
T FW 64 - Set all bits of FY64 to 77 to “0”
T FW 66
T FW 68
T FW 70
T FW 72
T FW 74
T FW 76
Default setting of the KBE;
Data can be received from the bus.
L KH 0080 - Load binary number 1000 0000
T FY 100 - Set bit 7 to “1” and bits 6 to 0 to “0”
Default setting of the KBS;
Program has access to the send mailbox
L KH 0000 - Load binary number 0000 0000
T FY 101 - Set bits 7 to 0 to “0”
BE Block end
Figure 13-2. Programming Example for Setting Parameters in FB1
13-4 EWA 4NEB 812 6120-02

13.2.2 Setting Parameters in DB1, for CPU 103 and Higher

Set the parameters in DB1 as follows:
1. Display the default DB1 on the programmer (Transfer function, source: PC, target: FD (PG)
- A default DB1 is integrated into the programmable controller's operating system; it contains
default parameters for the data exchange via SINEC L1.
2. Look for the SINEC L1 parameter block with the block ID “SL1:” for the PG/OP/SINEC L1 port.
3. Overwrite the comment character (#) with a space.
Beginning of the L1 parameter block

SL1:
for PG/ OP/ SINEC L1 port
SLN 1
...
...
PGN 1 Last parameter
4. Edit the default parameters according to your requirements. Do not change the syntax.
Example:
The S5-100U participates in the SINEC L1 network as a slave with the slave number 2.
- Send Mailbox (SF) in DB2 beginning with data word 0
- Receive Mailbox (EF) in DB2 beginning with data word 10
- Coordination Byte Send (KBS) is flag byte 0 (MB0)
- Coordination Byte Receive (KBE) is flag byte 2 (MB2)
- Programmer bus number (PGN) is 1.
Table 13-3 shows how to change default parameters for the example given above and which
parameter settings are permitted.
5. Transfer the changed DB1 to the programmable controller. The default DB1 is overwritten.
If you now go from STOP to RUN or from Power OFF to Power ON (with a battery inserted), the
programmable controller accepts the changed parameters and stores them in the system data area.
EWA 4NEB 812 6120-02 13-5

Table 13-3. Setting Parameters for the SINEC L1 Interface
Default DB1: Valid

Modifications
Block: SINEC L1 to Parameters for
Explanation Necessary for the
PG/ OP/ SINEC L1 CPU 103 and
Example
Port Higher
...
SL1: Block ID “SINEC L1 to no modification —

Interface SL1” necessary
SLN 1 Slave number of the SLN 2 SLN x
PLC; default to 1 (x=1 to 30)
SF DB2DW0 Location of the Send SF DB2DW0 SF DBxDWy
Mailbox; default (x=2 to 255;
location: DB2 y=0 to 255) or
beginning with DW0 SF MBz
(z=0 to 255)
EF DB3DW0 Location of the EF DB2DW10 EF DBxDWy
Receive Mailbox; (X=2 to 255;
default location: DB3 y=0 to 255) or
beginning with DW0 EF MBz
(z=0 to 255)
KBE MB100 Location of the KBE MB2 KBE MBx

Coordination Byte (x=0 to 255)
Receive; default or
location flag byte 100 KBE DByDWx*
(MB100) (y=2 to 255;
z=0 to 255)
KBS MB101 Location of the KBS MB0 KBS MBx
Coordination Byte (x=0 to 255)
Send; default location or
flag byte 101 (MB101) KBS DByDWz*
(y=2 to 255;
z=0 to 255)
PGN 1 Programmer bus num- PGN 1 PGN x
ber (necessary if you no modification (x=1 to 30)
want to transmit necessary
programmer functions
over SINEC L1;
default 1)
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* The KBE/KBS is in the high-order byte of the given data word.
13-6 EWA 4NEB 812 6120-02

13.3
block.
S5-100U
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa
EWA 4NEB 812 6120-02

aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa
KBS
KBE
Figure 13-3.
L1 bus
Send Mailbox
RAM
Control program
Sender (source)
Receive Mailbox
aaaa
for data exchange

have set the parameters in DB1.

coordination bytes (see Figure 13-3).

Data
area or
flag area

KBS
KBE
Coordinating Data Exchange in the Control Program

Send Mailbox
RAM
Control program
Receive Mailbox
for data exchange
Receive (destination)
Data Exchange between Sender and Receiver (Principle)

Data
program relies on the coordination information that the operating system makes available in the
There is an example in section 13.3.3 of how you must program the data exchange in a function
area or
flag area
After you set the parameters, the control program for data exchange has to be created. The control
In the following paragraphs, you will learn how to control the sending and receiving of data after you
Connecting the S5-100U to SINEC L1
13-7
13.3.1 Sending Data

The prerequisites for sending data are as follows:
• The parameters are set in DB1 for the location of the Send Mailbox (see section 13.2.2).
• The data to be sent, additional information (length of the send data “net data”), and destination
slave number are then transferred to the Send Mailbox.
Figure 13-4 shows which information has to be stored in what part of the Send Mailbox.
Example: Example:
Send Mailbox in the flag area Send Mailbox in the data block
(beginning with flag byte 1) (beginning with data word DW1)
DL DR
Flag byte 1 Length of the “net data” DW1 Length of the “net Number of the
(0 to 64 bytes) data” destination slave*
Flag byte 2 Numb. of the dest. slave* DW2 1st data byte 2nd data byte
Flag byte 3 Data (“net data”)
maximum of 64 bytes
Flag byte 66 DW33 63rd data byte 64th data byte

aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
* Number of the receiver: 0 = Master

1 to 30 = Slaves
31 = Broadcast
Figure 13-4. Structure of the Send Mailbox
Structure of the Coordination Byte Send (KBS)

Figure 13-5 shows the structure of the Coordination Byte Send (KBS).
KBS
Bit 7 6 5 4 3 2 1 0
0: No error
1: Error during last data transfer
0: No express transmission
1: Request a bus interrupt for this
transmission (express transmission)
0: Program is able to process Send

Mailbox (operating system has no
access)
1: Send Mailbox is enabled (program has
no access)
Figure 13-5. Structure of the Coordination Byte Send (KBS)
13-8 EWA 4NEB 812 6120-02

The control program for sending data should be structured as follows:

1. Check bit 7 in the KBS to see if data is currently being sent.
- If the programmable controller is sending data, bit 7 is set. During this phase, the Send
Mailbox can not be modified and no transmission can be started.
2. When bit 7 in the KBS has been reset, you can start the transmission by setting bit 7.
3. When bit 7 has been reset by the operating system after data has been sent, you can evaluate
possible errors.
You achieve the following by setting bit 4 in the KBS (express transmission):
• The sending programmable controller treats this message preferentially (possibly by overwriting
a telegram not yet sent).
• The receiver treats the message as an express transmission.
In case of an error, the operating system sets bit 0 of the KBS. The error message is not valid until
bit 7 has been reset in the KBS.
13.3.2 Receiving Data
The prerequisites for receiving data are as follows:

The parameters for the location of the Receive Mailbox and the Coordination Byte Receive (KBE)
(see section 13.2.2) have been set in DB1. Figure 13-6 shows you which information has to be
stored in what part of the Receive Mailbox.
Example: Example:
Receive Mailbox in the flag area Receive Mailbox in a data block
(beginning with flag byte 1) (beginning with data word 1)
DL DR
Flag Byte 1 Length of "net data" (in DW1 Length of the "net Source slave
bytes) data" number *
Flag Byte 2 Source slave number* DW2 1st data byte 2nd data byte
DW3 3rd data byte 4th data byte

Flag Byte 3 Data ("net data")
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
* Number of the sender: 0 = Master

1 to 30 = Slave
Figure 13-6. Structure of the Receive Mailbox
EWA 4NEB 812 6120-02 13-9

Structure of the Coordination Byte Receive (KBE)

Figure 13-7 shows the structure for receiving data (KBE).
KBE
Bit 7 6 5 4 3 2 1 0
0: No error
1: Error during last data transfer
0: No slave failed
1: At least one slave failed
0: Bus in STOP mode
1: Bus in RUN mode
0: No message
1: Data arrives as express transmission
0: Program can access the Receive

Mailbox
(operating system can not access)
1: Operating system accepts data into the
Receive Mailbox
(program can not access)
Figure 13-7. Structure of the Coordination Byte Receive (KBE)
Structure of the Control Program for Receiving Data:

1. Check bit 7 of the KBE to see if it is possible to read the data from the Receive Mailbox. Bit 7
must be set to “0” so that the Receive Mailbox can be read.
2. In addition, you can scan through the KBE for the following errors and operating conditions:
- At least one slave has failed.
- The bus is in RUN (STOP) mode.
- The received data pack comes as an express transmission.
Special Features
If you have reserved too little memory for the Receive Mailbox, the available memory area is filled
up completely (flag area FY0 to FY255, DW0 to DW255). Therefore, the remaining receive data
cannot be stored. In this case, the programmable controller does not generate an overflow
message.
You can find sample programs for sending and receiving data in the SINEC L1 manual (in the
chapter on “Programming”).
13-10 EWA 4NEB 812 6120-02

13.3.3 Programming the Messages in a Function Block

The control program must execute the following tasks:
• Enable the send and receive mailboxes and process the data contained in them.
• Manage the coordination bytes (e.g. send request, error evaluation).
Example:
Data traffic with the master as slave 1
Definitions:
• Slave 1 receives three bytes from Master 0.
• The information is stored in the process output image table (QB0, QB1, QB2).
• Slave 1 sends three bytes (IB0, IB1, IB2) to the master.
• Parameters are set in FB1 as shown in Figure 13-2.
Programming the individual blocks:
STL Explanation
OB22:
JU FB1 OB22 is processed once only following power up. It calls FB1,
which assigns the parameters to the slave.
BE
OB1:
.
.
JU FB2 OB1 is scanned cyclically, and calls FB2, which services the send
. and receive mailboxes.
.
.
BE
Figure 13-8. Organization of Program Execution
EWA 4NEB 812 6120-02 13-11

STL Explanation
C DB3 Receive mailbox (DB3)

A F100.7 Check whether access to receive mailbox is permissible.
KBE/Bit 7=0: Access permitted
KBE/Bit 7=1: Access not permitted
JC =M001 Skip receive mailbox evaluation if access not permitted
L DR0 Check whether the number of the source (master 0) is in
L KF+0 byte 2 of the receive mailbox
><F
JC =M002 Skip receive mailbox evaluation if source No. 0
L DL1
T QB0
L DR1 Transfer receive mailbox
T QB1 to the PIQ
L DL2
T QB2
M2: AN M100.7 Set KBE/Bit 7=1, i.e. permit PLC access.
Program access is not permitted again until the
S F100.7 PLC has reset this bit.
M1: A F101.7 Check whether access to the send mailbox is permitted.
KBS/Bit 7=0: Access permitted
KBS/Bit 7=1: Access not permitted
JC =M003 Skip send mailbox evaluation if access not permitted.
C DB2 Set send mail box (DB2)
L KF+3 Specify length of the data packet in byte 1
T DL0 of the send mailbox
L KF+0 Load destination number 0 (master) into byte 2 of the
T DR0 send mailbox
L IB3
T DL1 Load input bytes 3, 4 and 5
L IB4 into the send mailbox
T DR1
L IB5
T DL2
AN F101.7 Set KBS/bit 7, i.e. programmable controller has access to the send
S F101.7 mailbox
M3: NOP 0
BE
Figure 13-9. Programming “Message Processing” in FB2
13-12 EWA 4NEB 812 6120-02

14 Module Spectrum
14.1 General Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 1
14.2 Power Supply Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 2
14.3 Central Processing Units ............................... 14 - 4
14.4 Bus Units .......................................... 14 - 7
14.5 Interface Modules .................................... 14 - 11
14.6 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 13

14.6.1 Digital Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 13
14.6.2 Digital Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 22
14.6.3 Digital Input/Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 32
14.7 Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 34

14.7.1 Analog Input Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 34
14.7.2 Analog Output Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 52
EWA 4NEB 812 6120-02

S5-100U Module Spectrum
14 Module Spectrum
14.1 General Technical Specifications
Electromagnetic Compatibility (EMC)

Climatic Environmental Conditions
Noise Immunity
Temperature Radiated electromagnetic to IEC 801-3

Operating field test field strength 3 V/m
- horizontal design 0 to+60° C (32 to 140° F) Fast transient burst to IEC 801-4,
- vertical design 0 to+40° C (32 to 104° F) class III
(Air-intake temperature, Power supply
measured on the underside modules
of the module) - Supply voltage 24 V DC 1 kV
Nonoperating - 40 to +70° C - Supply voltage 115/230 V AC 2 kV
(- 40 to +150° F) - Analog input/output modules 1 kV
Temperature change - Digital input/output modules
- operating max. 10° C/h (50° F/h) for V = 24 V 1 kV
- nonoperating max. 20° C/h (68° F/h) for V > 24 V 2 kV
Relative humidity to DIN 40040 Communications
15 to 95% (indoors), interface 1 kV
noncondensing
Atmospheric pressure
- operating 860 to 1060 hPa
- nonoperating 660 to 1060 hPa
Pollutants
- SO2 0.5 ppm,
(rel. humidity 60%,
noncondensing)
- H2S 0.1 ppm,
(rel. humidity 60%,
noncondensing)
Mechanical Environmental Conditions IEC/VDE Safety Information
Vibration to IEC 68-2-6 Degree of protection to IEC 529

- tested with 10 to 57 Hz, - Type IP 20
(const. ampl. 0.15 mm) - Class to IEC 536
Insulation rating to VDE 0160
57 to 150 Hz,
- between electrically (05. 1988)
(const. accel. 2 g)
independent circuits
Shock to IEC 68-2-27 and
- tested with 12 shocks with circuits connected
(semisinusoidal to a central grounding
15 g /11 ms) point to VDE 0160
- between all circuits (05. 1988)
Free-fall to IEC 68-2-31
and
- tested with height of fall 50 mm
a central grounding point
(standard mounting rail) to VDE 0160
Electromagnetic Compatibility (EMC) (05. 1988)
Noise Immunity Test voltage sine, 50 Hz
for a rated voltage
Electrostatic discharge to IEC 801-2 Vinput of the circuits (AC/DC)
test (Discharge on all parts that Vinput= 0 to 50 V 500 V
are accessible to the oper- Vinput= 50 to 125 V 1250 V
ator during normal operation) Vinput= 125 to 250 V 1500 V
- Test voltage 2.5 kV
(rel. humidity
30 to 95%)
EWA 4NEB 812 6120-02 14-1

Module Spectrum S5-100U
14.2 Power Supply Modules

Power Supply Module PS 930 115/230 V AC; 24 V DC / 2 A (6ES5 930 -8MD11)
Technical Specifications
Input voltage
- rated value 115/230 V AC
- permiss. range 92 to 132 V/
187 to 264 V
Line frequency
- rated value 50/60 Hz
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
SIMATIC S5-100U - permiss. range 47 to 63 Hz

PS 930
Input current at
115/230 V
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
VOLTAGE - rated value 0.35/0.18 A

SELECTOR
- Input current max. 6/3 A
Power consumption 33 W
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
115/230V AC
24V DC 2A Output voltage
6ES5 930-8MD11 - rated value 24 V DC
- Permiss. range 18 to 34 V1)
- Open-circuit voltage max. 39 V
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaa
L1 Output current
- rated value 1A
aaaaaa
aaaaaa
aaaaaa
aaa
115/230V AC
N
Short-circuit 3Afast fuse
Fault LED none

Protection class class 1
Galvanic isolation yes

aaaaaaaaaaaaaaaa
aaaaaaaaaaaaa
L+
aaaaaa
aaa
24V DC
Conductor cross sectional area
M - stranded 2) 2×0.5 to 1.5 mm2
- solid 2×0.5 to 2.5 mm2

aaaaaaaaaa
aaaaaaaaaa
F
3A Insulation rating VDE 0160
Rated insulation voltage

(+24 V to L1) 250 V AC
- insulation group 2×B
- tested with 1500 V AC
Ri specification A to VDE 0871

Dimensions
W×H×D in mm 45.4×135×120
in. 1.8 x 5.3 x 4.7
aaaaaaaa
aaaaaaaa
aaaa
Power loss of the

module typ. 7.5 W
aaaaaaaaaaaaaa
aaaaaaa
L1 Weight approx. 1040 g (2.4 lbs)

N
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
2×4,7 nF 1) For this reason, can only be used with the S5-100U
aaaaaaaa
aaaaaaaa
CPUs
L+
2) With core and sleeves
aaaaaaaa
aaaa
14-2 EWA 4NEB 812 6120-02

Power Supply Module PS 931 115/230 V AC; 24 V DC / 2 A (6ES5 931-8MD11)
Technical specifications
Input voltage
- rated value 115/230 V AC
- permiss. range 92 to 132 V/
187 to 264 V
Line frequency
- rated value 50/60 Hz
- permiss. range 47 to 63 Hz
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aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
SIMATIC S5-100U Input current at

PS 931 115/230 V
- rated value 0.9/0.6 A
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
VOLTAGE Efficiency approx. 85%

SELECTOR
Power consumption approx. 60 W
Output voltage
- rated value 24 V DC
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
115/230V AC - permiss. range 22.8 to 25.2 V

24V DC 2A - open-circuit voltage yes
6ES5 931-8MD11
Output current
- rated value 2A
aaaaaaaaaaaaaaaa
aaaaaaaa
L1 Permiss. ambient
aaaaaa
aaaaaa
aaaaaa
115/230V AC temperature of PLC

N - horizontal arrangement 0 to 60 °C
(32 to 140 °F)
- vertical arrangement 0 to 40 °C
(32 to 104 °F)
Buffering of line
voltage dips
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaa
L+ - duration of voltage dips 20 ms at 187 V/2 A

aaaaaa
24V DC - repetition rate 1s

M
Short-circuit protection power limiting,
electronic cutoff,
non-latching
Fault LED no
Protection class class 1

Conductor cross-sectional area

- stranded * 2×0.5 to 1.5 mm2
- solid 2×0.5 to 2.5 mm2
Insulation rating VDE 0160 and
VDE 0805
(transformer)
(+24 V to L1) 250 V AC
aaaaaaaaaa
aaaaaaaaaa
aaaaa
1,6 A - insulation group 2×B

aaaaaaaaaaaaaa
aaaaaaa
L1
N Dimensions
W×H×D in mm 45.4×135×120
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
2×4,7 n
in. 1.8 x 5.3 x 4.7
aaaaaaaa
aaaaaaaa
L+ Power loss of the

module typ. 8.5 W
aaaaaaaa
aaaa
M
Weight approx. 500 g (1.1 lbs.)
* with core end sleeves
EWA 4NEB 812 6120-02 14-3

14-4
14.3
aaaaaaaa
aaaaaaaa
L+
aaaaaaaa
M
CPU 100
aaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaa aaaaaaaaaaaa
aaaaaaaa
aaaaaaaa
LOW
OFF/
SIEMENS
aaaaaaaaaaaa aaaaaaaa
aaaaaaaa aaaa
BATTERY
aaaa aaaaaa aaaaaaaaaaaaaaaaaa
18 ...
Module Spectrum
34 V
PS
aaaaaaaa
L+
5,0 V
aaaaaaaa aaaa aaaaaa aaaaaaaaaaaa
aa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
24 V DC
aaaaaaaaaa aaaaaaaa
+5,2 V
RUN
RUN
STOP
STOP
COPY
aaaaaaaa aaaaaaaaaa aaaaaaaa
aaaaa aaaaaaaaaaaaaaaaaaaaaa
6ES5 100-8MA02
aaaaaaaa aaaaaaaa
CPU
aaaaaaaa aaaaaa
aaa aaaaaaaa
aaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
CPU 100
SIMATIC S5-100U
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+9 V
Data
GND
Central Processing Units
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Flags
- solid
Weight
module
- from V 2
- from V 1
- integrated
Data blocks
- Service life
Input voltage
Digital inputs,
- Backup time
- CPU module
- V 1 (for I/Os)
Analog inputs,
Digital outputs
Output current
Output voltage
Backup battery
Analog outputs
- nominal value
Function blocks
Program blocks
Protection class
- programmable
Execution times
- permiss. range
Sequence blocks
- internal memory
Galvanic isolation
Power losses of the

Organization blocks
- per word operation
- memory submodule
Memory configuration
- vertical arrangement
- V 2 (for programmer)
Short-circuit protection
- horizontal arrangement
Counters: Number/range
Power supply (internal)

in.
Dimensions (WxHxD) in mm
- memory submodule approx.

approx.
Number of operations approx.
Connector cross-sectional area

together max.
together max.
Current consumption from +24 V
Permissible ambient temperature

8
no
60
256
1A
+9 V
none
none
- per binary operation approx. 70 µs
+5.2 V
2 to 63
0 to 63
0 to 63
approx. 125 µs
class 1
0.65 A
Scan monitoring time approx. 300 ms
DC 24 V
typ. 10.7 W
[77 °F])
electronic
1A
EPROM/EEPROM
18 to 34 V
[77 °F] and

uninterrupted
16; 8 retentive
91.5×135×120
RAM 1024 statements
Lithium Battery
(3.6 x 5.3 x 4.7)

min. 1 year (at 25 °C
backup of CPU)
0.1 kg (0.2 lbs)

approx. 5 years (at 25 °C
(3.4 V/ 850 mAh)
0.65 kg (1.4 lbs)

Timers: Number/range approx. 16; 0.01 to 9990 s
0 to 999 (up/down)
2×0.5 to 1.5 mm2

- stranded, with core end sleeves 2×0.5 to 1.5 mm2
0 to 40 °C (32 to 104 °F)
0 to 60 °C (32 to 140 °F)
1024; 512 retentive
OB1, 21, 22, and 34

(6ES5 100-8MA02)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
EWA 4NEB 812 6120-02

S5-100U
aaaaaaaaaa
aaaaaaaaaa
S5-100U
CPU 102
L+
aaaaaaaa aaaaaaaaaa
M
aaaaaaaa
aaaa aaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
LOW
OFF/
SIEMENS
aaaaaaaaaaaa aaaaaaaaaa
aaaaa
BATTERY
aaaaaaaa aaaaaaaaaaaaaaaaaa
18 to
aaaaaa
L+
34 V
PS
aaaaaaaa aaaaaaaaaaaa
5,0 V
EWA 4NEB 812 6120-02

aaaaaa
aaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaa
24 V DC
RUN
RUN
+5,2 V
STOP
STOP
COPY
aaaaaaaa aaaaaaaaaa aaaaaaaaaa
6ES5 102-8MA02
aaaaaaaa aaaaa aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaa
CPU
aaaaaaaa aaaaaaaa
aaaa aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa
CPU 102
aaaaaaaaaaaaaaaaaa
SIMATIC S5-100U
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Flags
- solid
Weight
module
- from V 2
- from V 1
- integrated
Data blocks
- Service life
Input voltage
Digital inputs,
- Backup time
- CPU module
- V 1 (for I/Os)
Analog inputs,
Digital outputs
Output current
Output voltage
Backup battery
Analog outputs
- nominal value
Function blocks
Program blocks
Protection class
- programmable
- permiss. range
Sequence blocks
- internal memory
Galvanic isolation
Power losses of the

Organization blocks
- memory submodule
- memory submodule

in.
Execution times Normal/Test
Number of operations approx.
approx.
approx.
no
60
together max. 16
together max. 256
1A
+9 V
none
Permissible ambient temperature of PC

+5.2 V
2 to 63
0 to 63
0 to 63
class 1
0.65 A
Scan monitoring time approx. 350 ms
[77 °F])
- per binary operation approx. 7/70 µs
and 251
DC 24 V
typ. 11.4 W
electronic
approx. 40/125 µs
1A
EPROM/EEPROM
18 to 34 V
[77 °F] and

uninterrupted
32; 8 retentive
RAM 2048 statements
Lithium Battery
backup of CPU)
91.5×135×120
240 to 243, 250,
0.1 kg (0.2 lbs)

(3.4 V/ 850 mAh)
(3.6 x 5.3 x 4.7)
0.65 kg (1.4 lbs)

Timers: Number/range approx. 32; 0.01 to 9990 s
0 to 999 (up/down)
2×0.5 to 1.5 mm2

0 to 40 °C (32 to 104 °F)
0 to 60 °C (32 to 140 °F)
1024; 512 retentive
OB1, 21, 22, and 34

(6ES5 102-8MA02)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Module Spectrum
14-5
14-6
aaaaaaaa
aaaaaaaa
L+
M
CPU 103
aaaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
aaaaaaaaa aaaaaaaa
LOW
OFF/
SIEMENS
aaaaaaaa aaaaaaaaaaaa aaaaaaaa
aaaaaa aaaaaaaaaaaa aaaa
18 to
BATTERY
34 V
Module Spectrum
PS
aaaaaaaa aaaaaaaa
5,0 V
L+
aaaaaaaa aaaaaa aaaaaaaaaaaa
aaa aaaaaaaaaa aaaaaaaa
24 V DC
aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
+5,2 V
RUN
RUN
aaaaaaaa
STOP
STOP
COPY
aaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
6ES5 103-8MA03
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
CPU
aaaaaaaa aaaaaa aaaaaaaa
aaa aaaaaaaa
aaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
CPU 103
aaaaaaaaaaaaaaaa
SIMATIC S5-100U
aaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Flags
- solid
Weight
module
in °C)
- from V 2
- from V 1
Processor
- Accuracy
- integrated
Data blocks
- service life
Input voltage
- backup time
Digital inputs,
- CPU module
- V 1 (for I/Os)
Analog inputs,
Digital outputs
Output current
Output voltage
Backup battery
Analog outputs
- nominal value
Real-time clock
Function blocks
Program blocks
Protection class
- programmable
Execution times
- permiss. range
Sequence blocks
- internal memory
Galvanic isolation
Power losses of the

Organization blocks
- memory submodule
- memory submodule
Scan monitoring time

- e.g. tolerance at 40 °C

(TA ambient temperature

in.

Timers: Number/range approx.
Permissible ambient temperature

no
together max. 32
Number of operations approx. 180

251
together max. 256
1A
+9 V
- Variation due to temperature changes
- per binary operation approx. 0.8 µs

+5.2 V
approx. 100 µs
class 1
0.65 A
[77 °F])
±2s/day
2 to 255
0 to 255
0 to 255
0 to 255
DC 24 V
typ. 11.6 W
Byte/bit processor
electronic
1A
EPROM/EEPROM
18 to 34 V
[77 °F] and

approx. 0 to -4s/day
uninterrupted
91.5×135×120
Lithium Battery
-3.5x(TA-15)2ms/day
128; 8 retentive
(3.6 x 5.3 x 4.7)

31, 34, and 251
backup of CPU)
RAM 10240 statements
240 to 243, 250,
approx. 0.1 kg (0.2 lbs)

(3.4 V/ 850 mAh)
approx. 0.65 kg (1.4 lbs)

0 to 999 (up/down)
500 ms, selectable
2×0.5 to 1.5 mm2

±2s-3.5x(40-15)2ms/day
128; 0.01 to 9990 s
0 to 40 °C (32 to 104 °F)

0 to 55 °C (32 to 131 °F)
OB1, 2, 13, 21, 22,
2048; 512 retentive

(6ES5 103-8MA03)
EWA 4NEB 812 6120-02

S5-100U
14.4
aaaaa
1
1
2
aaaaaaaaaaaaaaaaaaaaaaaaa aaaa aaaaaa
2
S5-100U
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaa
3
3
4
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaa
4
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
5
aaaaa aaaa aaaaaaa
5
6
aa aaaaaaaaaaaaaaaaaaaaaaa
6
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaa
7
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
EWA 4NEB 812 6120-02

8
+9V
GND
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Bus Units
aaaaaaaa
9
aaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
10
aaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaa
Data
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
1 nF
1
aaaaaaaa aaaaaaaaaa aaaaa
aaaaa aaaaaa
1
2
aaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaa
2
aaaaaaaaaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
SIEMENS
3
aaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
3
4
aaaa aaaaaaaaaaaaaaaaaaaaaaaaa
4
aaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa
aa aaaaaa aaaaaaaaaaaaaaaaaaaaaa
5
aaaaaaaaaa
5
6
aaaa aaaaaaaaaaaaaaaaaaaaaa
6
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa aaaa aaaaaaaaaa
7
aaaaa aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
8
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
Bus Unit (SIGUT Screw-type Terminals)

aaaaa
9
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
10
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
aaaaa aaaaaaaaaaaaaaaaaaaa
aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
- solid
Weight
(+9 V to
bus units
controller
- stranded *
Dimensions
- tested with
)
sectional area
in.
Insulation rating
Conductor cross
W×H×D in mm
- insulation group
- from +9 V (CPU)
per programmable
Type of connection
Number of bus units
Number of terminals
Current consumption
* with core end sleeves

Connection between two
Number of plug-in modules

typ.
max.
approx.
16
1×B
1 mA
12 V AC
terminals
500 V AC
flat ribbon
VDE 0160
10 per slot
3.6×6.4×1.5
91.5×162×39
300 g (10.6 oz.)

2×0.5 to 2.5 mm2

2×0.5 to 1.5 mm2
SIGUT screw-type
(6ES5 700-8MA11)
Module Spectrum
14-7
14-8
1
2
aaaaaaaaaaaaaaaa aaaa
aaaaaaaaa aaaaaaaaaaaaaa aaaa
aaa aa
3
4
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaa aaaaaa
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaa
5
6
aaaaaaaaaaaaaaaaaa aa
Module Spectrum
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+9V
aaaaaaaaaaaaaa
GND
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
aaaaaaa aaaaaaaaaaaaaaaaaa
aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa
aaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
Data
aaaaaaaaaa
1 nF
1
2
aaaaaaaaaa aaaaa aaaaaaaaaaaaaaaa aaaa
aaaaa aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
SIEMENS
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaa
3
4
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa aaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa
5
6
aaaaaaaaaaaaaaaaaa aa aaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
Bus Unit (Crimp Snap-in Connections)

aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aa
aaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Weight
(+9 V to
bus units
controller
- stranded
Dimensions
- tested with
)
sectional area
in.
Insulation rating
Conductor cross
W×H×D in mm
- insulation group
- from +9 V (CPU)
per programmable
Type of connection
Number of bus units
Number of terminals
Current consumption

Number of plug-in modules

typ.
max.
approx.
16
1×B
1 mA
12 V AC
500 V AC
flat ribbon
VDE 0160
10 per slot
3.6×5.3×1.5
91.5×135×39
Crimp snap-in
250 g (8.8 oz.)

0.5 to 1.5 mm2
(6ES5 700-8MA21)
EWA 4NEB 812 6120-02

S5-100U
1
aaaa
1
2
aaaaaaaaaaaaaaaa aaaaaaaa aaaa
2
aaaaaa aaaaaaaa aaaa aa
S5-100U
aaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaa
CPU
3
aaaaaa aaaa
3
4
aaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaaaaa aaaaa aaaaa
4
aaaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
5
aaaaaa
5
6
ALARM
aaaaaaaaaaa aaaaaaaaaaaaaaaa aaa aaaaaaaaaaaaaaaa aaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaa aa
6
aaaaaaaaaaa aaaaaaaa
7
aaaaaa aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaaaaaaaaaaa
+9V
8
EWA 4NEB 812 6120-02

aaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Alarm
GND
9
aaaaaa aaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaa
10
aaaaaa aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Data
1 nF
aaaaaa aaaaaaaa aaaa
1
aaa aaaa
1
2
aaaaaaaaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaa
2
aaaaaaaaaaaaaaa aaaaaaaa a a a a aaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
SIEMENS
3
aaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaa
3
4
aaaaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaaaaaaaaaa
(SIGUT Screw-type Terminals)
4
aaaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaaaaaaa
aaaaaaaa
aaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa
5
aaaa aaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa
5
6
ALARM
Bus Unit with Interrupt Capability
6
aaaaaaaaaaaa aaaaaaaa aaaaaaaa
a a a a aaaaaaaaaaa
aaaa
7
aaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
8
aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
9
aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
9
8 1 0
10
aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaa aaaa
aaaa aaaaaaaaaaaaaaaaaa
aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
*
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
units
- solid
Weight
controller
Dimensions
(+9 V to )
- tested with
- stranded **
bus modules
sectional area
in.
Insulation rating
Conductor cross-
(WxHxD) in mm
- Insulation group
- from+9 V (CPU)
Number of plug-in
per programmable
Type of connection
Number of terminals
Current consumption
Number of bus modules

** With core and sleeves

2
10
max. 16 *
1×B
typ. 11 mA
12 V AC
500 V AC
flat ribbon
terminals)
VDE 0160
91.5×162×39
approx. 320 g (9.8 oz)

3.6 x 6.4 x 1.5
adjacent to the CPU has interrupt capability

2×0.5 to 2.5 mm2

2×0.5 to 1.5 mm2
input modules or comparator modules) directly

SIGUT (screw-type
Only the bus unit (and only with 4-channel digital

(6ES5 700-8MB11)
Module Spectrum
14-9
14-10
aaaaaaaaaa
1
2
aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaa aaaa
aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaa aaa
aaaaa aaaaa aaaaa
3
4
aaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaa aa aaaaaaaaaaaaaa aaaaaaaaaa aaa
CPU
ALARM
aaaaaa a a a a a a a a a a a a a a a a a a a a a a
5
6
aaa aaaaaaaaaaaaaaaaaa aaaaa aaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
Module Spectrum
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
8 1
aaaaaa a a a a aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
0
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaa
+9V
aaaaaa aaaaaaaaa
Alarm
GND
aaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaa a a a a a a a a aaaaaaaa aaaaaaaaaaaaaaaa aaaa
1
2
aaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaa
Data
1 nF
SIEMENS
aaaaaaaa aaaaaaaaaaaaaaaaa aaaaaaaa
(Crimp Snap-in Connections)

aaaaaa aaaa aaaaaaaaaaaaaaaa aaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
3
4
aaaaaaaaaaaaaaaaaa a a a a a a a a aaaaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaa aa aaaaaaaa aaaaaaaa
a a a a a a a a a a a a a a aaaa aaaaaaaaaaaaaaaaaaaaaa
ALARM
Bus Unit with Interrupt Capability
5
6
aaaaaaaaaaaaaaaaaa aaaaaaaa aa aaaaaaaaaaa
a a a a a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
7
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa
a a a a aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaa
9
8 1 0
aaaaaaaaaaaaaaaaaaa aaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
*
units
Weight
(+9 V to
controller
- stranded
Dimensions
- tested with
)
bus modules
sectional area
in.
Insulation rating
Conductor cross-
(WxHxD) in mm
- insulation group
- from+9 V (CPU)
Number of plug-in
per programmable
Type of connection
Number of terminals
Current consumption
Number of bus modules

2
max. 16 *
1×B
typ. 11 mA
12 V AC
500 V AC
flat ribbon
VDE 0160
10 per slot
91.5×135×39
3.6 x 5.3 x 1.5
Crimp-snap-in
adjacent to the CPU has interrupt capability

0.5 to 1.5 mm2
approx. 270 g (9.5 oz)

input modules or comparator modules) directly

Only the bus unit (and only with 4-channel digital
(6ES5 700-8MB21)
EWA 4NEB 812 6120-02

S5-100U
14.5 Interface Modules

IM 315 Interface Module (6ES5 315-8MA11)
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
OUT
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaa
SIEMENS
SIMATIC S5
aaaaaaaaaa
aaaaa
INTERFACE MODULE
IN
6ES5 315-8MA11
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
MADE IN GERMANY
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
aaaaaaaa
+9V
aaaaaaaaaaaa
GND
Data Current supply to the
expansion unit max. 1A
Number of interface
modules per PLC max. 1
aaaaaaaa
aaaaaaaa
aaaa
1 nF
Permissible potential
difference between
(IM 315) and central
ground point (CPU) ±1 V
Insulation rating VDE 0160
aaaaaaaaaa
aaaaaaaaaa
aaaaa

input (+9 V to ) 12 V AC
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa

output
Dimensions
W×H×D in mm 2×(45.4×135×39)
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaa
aaaaaaaa
in. 2×(1.8×5.3×1.5)
+9V
aaaaaaaaaaa
GND Current consumption

Data - from +9 V (CPU) typ. 1 mA
Weight approx. 280 g (9.8 oz.)
aaaaaaaa
aaaaaaaa
aaaa
1 nF
EWA 4NEB 812 6120-02 14-11

14-12
aaaaaaaa aaaaaaaaaaaaaa
Module Spectrum
IN
aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaa aaaaaaaa
OUT
aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaa aaaaaaaa
SIMATIC S5
SIEMENS
1 nF
6ES5 316-8MA12
IM 316 Interface Module
MADE IN GERMANY
aaaaa
INTERFACE MODULE
aaaaaaaaaa
GND
aaaaaaaaaaaaaaaa
Data
+9V
aaaaaaaaaa
aaaaa aaaaaaaaaaaaa
aaaaa
aaaaaaaa aaaaaaaaaa
input
aaaaaaaa aaaaaaaaaa
output
aaaaaaaa aaaaaaaaaa
aaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
IM 316
Weight
Dimensions
(+9 V to )
(10 m/33 ft.)

expansion unit
(2.5 m/8.2 ft.)

(0.5 m/1.6 ft.)
in.
Insulation rating
(5.0 m/16.4 ft.)
W×H×D in mm
- insulation group
modules per PLC
- from +9 V (CPU)
- Cable connector
- Cable connector
- Cable connector
- Cable connector
difference between
ground point (CPU)

Number of interface
(IM 316) and central

Permissible potential
Current consumption
Current supply to the

Cable insulation in ducts
Cable connectors for the
typ.
max.
max.
approx.
4
1A
1×B
±1 V
27 mA
12 V AC
VDE 0160
permissible
1.8×5.3×1.5
45.4×135×39
120 g (4.2 oz.)

6ES5 712-8BF00
6ES5 712-8AF00
6ES5 712-8CB00
6ES5 712-8BC50
(6ES5 316-8MA12)
EWA 4NEB 812 6120-02

S5-100U
14.6
S5-100U
L+
aaaaaaaaaa
1
aaaaaaaaaa
1
aaaa aaaaaaaaaaaaaaaaaaaa
2
M
3
.7
.3
.6
.2
.5
.1
.4
.0
aaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaa
X.0
aaaa aaaaaaaaaaaaaaaaaaaa aaaaa aaaaa aaaaa aaaaa
4
aaaaaaaa
4
EWA 4NEB 812 6120-02

5
aaaa aaaaaaaaaaaa
4 x 24 V DC
aaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
9
8
7
6
5
4
3
2
1
6ES5 420-8MA11
aaaaaaaa aaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
5
10
X.1
6
180 K
aaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaa
4
M
DIGITAL INPUT
aaaaaaaa aaaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaa
L+
6
aaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaa
aaa
X.2
aaaaaaaa aaaaaaaa
aaaaaaaa
Digital Modules
8
aaaaaaaa aaaaaa a a
X.3
aaaa
Digital Input Module 4×24 V DC

aaaaaaaa
10
aaaa aaaaaaaaaaaa
aaaa
14.6.1 Digital Input Modules

aaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
signal
Weight
module
(+9 V to
- ”1” signal
- ”0” signal
- unshielded
)
- rated value
- in groups of
Inherent delay
- from ”1” to ”0”

- from ”0” to ”1”
Fault LED (red)

Length of cable
Insulation rating
Input voltage L+
- residual current
Number of inputs
Power loss of the

- insulation group
Galvanic isolation
- from +9 V (CPU)
(for ET 100U only)
Input current at ”1”
Permissible ambient
Address designation
Connection of 2-wire
Current consumption
temperature of module
BERO proximity switches

Rated insulation voltage *
typ.
typ.
typ.
typ.
typ.
max.
approx.
4
4
no
1×B
4 DI
5 ms
7 mA
0.8 W
16 mA
2.5 ms
1.5 mA
0 to 5 V
no input
possible
12 V AC
24 V DC
0 to 40 °C
0 to 60 °C
VDE 0160
13 to 33 V
voltage L+
(32 to 104 °F)

(32 to 140 °F)
205 g (7.2 oz.)

100 m (330 ft.)
* Relevant only for isolated assembly in the ET 100U

(6ES5 420-8MA11)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Module Spectrum
14-13
Digital Input Module 8×24 V DC (6ES5 421-8MA12)
Address designation
(for ET 100U only) 8 DI
Number of inputs 8
Galvanic isolation no
aaaaa
aaaaaa
aaa
L+
1 - in groups of 8
F
Input voltage L+
aaaaaa
aaaaaa
aaa
2
M - rated value 24 V DC
aaaaaa
aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaa
.0 4
- ”0” signal 0 to 5 V
- ”1” signal 13 to 33 V
3
aaaaaa aaaaaaaa aaaaaa aaaaaa
aaa aaaa aaa aaa
.1
6 signal typ. 7 mA at 24 V
.2
.3 5 Inherent delay
- from ”0” to ”1” typ. 2.3 ms
8
- from ”1” to ”0” typ. 4.5 ms
.4
Length of cable
aaaaaa aaaaaa
aaa aaa
.5 7 - unshielded max. 100 m (330 ft.)

a
aaaa
a
.6 10 Insulation rating VDE

a a
Rated insulation voltage *

aaaaaa
aaa
9
.7 (+9 V to ) 12 V AC
Fault LED (red) no input voltage
aaaaaa
4 L+/M
Permissible ambient
- horizontal arrangement 0 to 60 °C
DIGITAL INPUT (32 to 140 °F)

8 x 24 V DC - vertical arrangement 0 to 40 °C
6ES5 421-8MA12 (32 to 104 °F)
1 2 3 4 5 6
BERO proximity switches possible
- residual current 1.5 mA
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
+9 V
Data
from +9 V (CPU) typ. 34 mA
Power loss of the

module typ. 1.6 W
aaaaaaaa
aaaaaaaa
aaaa
180 K Weight approx. 190 g (6.7 oz.)

aaaaaaaa aaaa
aaaa
aaaa aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaaaaaaaaaaaa
1 3 5 7 9
aaaaaaaa
aaaaaaaa
2 4 6 8 10
aaaaaaaa
L+ M
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
14-14 EWA 4NEB 812 6120-02

Digital Input Module 4 × 24 to 60 V DC (6ES5 430-8MB11)
Address designation
Number of inputs 4
Galvanic isolation yes (optocoupler)
- in groups of 4
aaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaa
L+
1
F M Input voltage L+
2 - rated value 24 to 60 V DC
3
aaaaaaaaaa
aaaaa
.0 - ”1” signal 13 to 72 V
.4 4 - ”0” signal - 33 to 8 V
aaaaaaaaaaaa
5
aaaaaaaaaa
aaaaa
signal typ. 4.5 to 7.5 mA

.1
.5 6
Inherent delay
- from ”0” to ”1” typ. 3 ms (1.4 to 5 ms)
- from ”1” to ”0” typ. 3 ms (1.4 to 5 ms)
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
7
.2
.6 8 Fault LED (red) no input voltage L+
Connection of 2-wire BERO
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
aaaaaa
9 proximity switches possible

.3 - residual current 1.5 mA
.7 10
Permissible ambient
(32 to 140 °F)
aaaaaa
4
(32 to 104 °F)
Length of cable
- unshielded max. 100 m (330 ft.)
DIGITAL INPUT Insulation rating VDE 0160

4 x 24 - 60 V DC
6ES5 430-8MB11
1 2 3 4 5 6 (+9 V to ) 12 V AC
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V Rated insulation voltage

GND (+9 V to L+) 60 V AC
Data
Current consumption
- from +9 V (CPU) 5 mA
- from L+ max. 35 mA
Power loss of the

module max. 2W
Weight approx. 200 g (7 oz.)

aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaa
aaaaaaaaaaaaa
1 3 5 7 9
aaaaaaaa
aaaa
4 6 8 10
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
L+ M X.0 X.1 X.2 X.3
EWA 4NEB 812 6120-02 14-15

Digital Input Module 4×115 V AC (6ES5 430-8MC11)
Address designation
Number of inputs 4
- in groups of 4
aaaaaaaaaaaaaaaaaa
aaa aaaaaa
L1
1 Input voltage L1
aaaaaa
aaa
N - rated value 115 V AC/DC

2 - ”0” signal 0 to 40 V
aaaaaaaaaa
aaaaa
3
.0 - ”1” signal 85 to 135 V
.4 4 - frequency 47 to 63 Hz

aaaaaaaaaaaa
aaaaaa
5
aaaaaaaaaa
aaaaa
.1 signal typ. 14 mA at 115 V AC

.5 6 typ. 6 mA at 115 V DC
Inherent delay
aaaaaaaaaaaaaa
aaaaaaa
- from ”0” to ”1” typ. 10 ms

aaaaaaaaaa
aaaaa
7
.2 - from ”1” to ”0” typ. 20 ms
.6 8
Length of cable
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
9
.3
.7 Insulation rating VDE 0160
10
(+9 V to L1) 125 V AC
aaaaaa
2
(+9 V to ) 12 V AC
DIGITAL INPUT Permissible ambient

4 x 115 V AC
6ES5 430-8MC11 temperature of module
1 2 3 4 5 6
(32 to 140 °F)
(32 to 104 °F)
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
+9 V Connection of 2-wire
GND BERO proximity switches possible
Data - residual current 5 mA
Current consumption
- from +9 V (CPU) typ. 16 mA
Power loss
of the module typ. 2.8 W
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
1 3 5 7 9
2 4 6 8 10
aaaaaaaa
aaaaaaaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
L1 N X.0 X.1 X.2 X.3
14-16 EWA 4NEB 812 6120-02

Digital Input Module 4×230 V AC (6ES5 430-8MD11)
Address designation
Number of inputs 4
- in groups of 4
aaaaaaaaaaaa
aaaaaaaaaaa
L1 Input voltage L1
aaaa
1
N - rated value 230 V AC
2 - ”0” signal 0 to 70 V
3
aaaaaaaaaa
aaaaa
.0 - ”1” signal 170 to 264 V

.4 4 - frequency 47 to 63 Hz

aaaaaaaaaaaa
5 signal typ. 16 mA at 230 V

aaaaaaaaaa
aaaaa
.1
.5 6
Inherent delay
- from ”0” to ”1” typ. 10 ms
- from ”1” to ”0” typ. 20 ms
aaaaaaaaaaaa
7
aaaaaaaaaa
aaaaa
.2
.6 8 Length of cable
aaaaaaaaaaaa
aaaaaa
9 Insulation rating VDE 0160

aaaaaaaaaa
aaaaa
.3
.7 10 Rated insulation voltage
(+9 V to L1) 250 V AC
aaaaaa
2 (+9 V to ) 12 V AC
Permissible ambient
DIGITAL INPUT temperature of module

4 x 230 V AC - horizontal arrangement 0 to 60 °C
6ES5 430-8MD11
(32 to 140 °F)
1 2 3 4 5 6 - vertical arrangement 0 to 40 °C
(32 to 104 °F)
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
+9 V - residual current 5 mA
GND
Data
Current consumption
Power loss
aaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
1 3 5 7 9
2 4 6 8 10
aaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
L1 N X.0 X.1 X.2 X.3
EWA 4NEB 812 6120-02 14-17

Digital Input Module 8 x 24 V DC (6ES5 431-8MA11)
Address designation
Number of inputs 8
aaaaaaaaaaaaaaa
aaa aaaaaa
- in groups of 8
aaa aaa aaaa aaa aaaaaaaaa aaaaaa
1 L+
M Input voltage L+
2 - rated value 24 V DC
aaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaaaa
aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaa
.0 4 - "0" signal 0 to 5 V
- "1" signal 13 to 33 V
3
.1
Input current at
6 "1" signal typ. 8.7 mA
.2
Inherent delay
.3 5 - from "0" to "1" typ 5.5 ms
- from "1" to "0" typ. 4 ms
.4 8
Length of cable
aaaaaa aaaaaaaa aaaaaa
aaa aaaa aaa
7
.5
a
aaaa

a
10
a
.6
a

9 (+ 9 V to ) 12 V AC
.7
- insulation group 2xB
aaaaaa
4
(+ 9 V to L+) 30 V AC
Permissible ambient
DIGITAL INPUT temperature of module

8 x 24 V DC
6ES5 431-8MA11
(32 to 140 °F)
1 2 3 4 5 6 - vertical arrangement 0 to 40 °C
(32 to 104 °F)
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V
GND
Data Current consumption
- from + 9 V (CPU) typ. 32 mA
Power loss of
the module typ. 2W

aaaa
aaaaaaaa aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaa
aaaaaaaaaaaa
1 3 5 7 9
aaaa aaaa
aaaa
2 4 6 8 10
aaaaaaaa
aaaaaaaa
L+ M
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
14-18 EWA 4NEB 812 6120-02

Digital Input Module 8×115 V AC (6ES5 431-8MC11)
Address designation
Number of inputs 8
- in groups of 8
aaaaaaaa aaaaaa aaaaaaaa aaaaaaaa aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaa aaaaaa
L1
aaaaaaaa aaa aaaa aaaa aaa aaaaaaaaaa aa
1
aaaaaa
aaa
Input voltage L1
N - rated value 115 V AC/DC
2
- ”0” signal 0 to 40 V
aaaaaa
aaaaaa
.0 4
- ”1” signal 85 to 135 V
- frequency 47 to 63 Hz
aaaaaaaa
aaaaaaaa
3
.1
6
aaaaaa
aaaaaa

typ. 2.5 mA at 115 V DC
aaaaaaaa
aaaaaaaa
5
.3
Inherent delay
- from ”0” to ”1” typ. 10 ms
aaaaaa
aaaaaa
8
.4 - from ”1” to ”0” typ. 20 ms
7
aaaaaa
aaaaaa
.5 Length of cable
aaaaaa
aaaaaa
10
.6
aaaaaa
aaa
9
aaaaaa
aaaaaa
.7 Rated insulation voltage

(+9 V to L1) 125 V AC
aaaaaa
aaa
2
(+9 V to ) 12 V AC
aaaaaaaaaa
DIGITAL INPUT
8 x 115 V AC Permissible ambient
6ES5 431-8MC11 temperature of module
1 2 3 4 5 6 - horizontal arrangement 0 to 60 °C
(32 to 140 °F)
(32 to 104 °F)
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
+9 V
GND Connection of 2-wire
Data BERO proximity switches possible
- residual current 4 mA
Current consumption
Power loss
aaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaa
aaaaaaaaaa
1 3 5 7 9
2 4 6 8 10
a
a
a
N
a
L1
a
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
a
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
EWA 4NEB 812 6120-02 14-19

Digital Input Module 8×230 V AC (6ES5 431-8MD11)
Address designation
Number of inputs 8
aaaaaaaa aaa aaaa aaaa aaa aaaaaaaaaaaaaaaaaaaaa
aaa aaa
L1
- in groups of 8
aaaaaaaa aaa aaaa aaaa aaa aaaaaaaaaaaaa
1
aaaaaa
aaa
N Input voltage L1
2 - rated value 230 V AC/DC
aaaaaa
aaaaaa
.0 4 - ”0” signal 0 to 95 V
- ”1” signal 195 to 253 V
3 - frequency 47 to 63 Hz
aaaaaa
aaaaaa
.1
6 Input current at ”1”
aaaaaaaa
aaaaaaaa

5
typ. 1.8 mA at 230 V DC
aaaaaa
aaaaaa
.3
Inherent delay
aaaaaa
aaaaaa
8 - from ”0” to ”1” typ. 10 ms

.4
- from ”1” to ”0” typ. 20 ms
7
aaaaaa
aaaaaa
.5 Length of cable
aaaaaaaa
aaaaaaaa
10
.6
aaaaaa
9
aaaaaa
aaaaaa
.7
(+9 V to L1) 250 V AC
aaaaaa
2
(+9 V to ) 12 V AC
DIGITAL INPUT
8 x 230 V AC
6ES5 431-8MD11 Permissible ambient
1 2 3 4 5 6
(32 to 140 °F)
(32 to 104 °F)
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
+9 V
GND
Data Connection of 2-wire
- residual current 5 mA
Current consumption
Power loss

aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaa
1 3 5 7 9
2 4 6 8 10
a
a
a
N
aaa
L1
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
14-20 EWA 4NEB 812 6120-02

Digital Input Module 8 x 5 to 24 V DC (6ES5 433-8MA11)
Address designation
Number of inputs 8
- in groups of 8
aaaaa
aaaaaa
aaa
L+
1 Input voltage L+
- rated value 5 to 24 V DC
aaaa aaa aaaa aaa aaaa aaa aaaaaaaaaa
aaa
M - "0" signal Vin approx. 25% L+

aaaaaaaa aaa aaaa aaa aaaa aaa aaaaa
2
- "1" signal Vin approx. 45% L+
aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa
aaa aaaa aaa aaaa aaa
.0 4
Permissible range 4.5 to 30 V

.1 3
Input resistance 4.7 k to L+ or M;
6 reversible on the back
.2
of the module *
.3 5
The LED displays
8 the evaluated signal
.4
Inherent delay approx. 1 ms or 10 ms;
aaaaaa aaaaaa
aaa aaa
7 reversible on the back

.5
of the module *
10
.6
Length of cable
aaaaaa

aaaaaaaaaaaaaa
aaaaaaaaaaaa
9
.7
aaaaaaaaaa
aaaaaaaa
1- L+
2- M
aaaaaa
aaa
8 (+ 9 V to L+) 30 V AC

aaaaaaaaaa
DIGITAL INPUT (+ 9 V to ) 12 V AC
8 x 5 ... 24 V DC - insulation group 2xB
6ES5 433-8MA11 - tested with 500 V AC
1 2 3 4 5 6
Permissible ambient
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
+9 V (32 to 140 °F)

GND
Data - vertical arrangement 0 to 40 °C
(32 to 104 °F)
Current consumption
- from L+ typ. 60 mA
aaaaaa
aaa
S2
Power loss of the
module typ. 2.4 W
aaaaaa
aaa
S1
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
4.7 k
* reversible in groups of 8
aaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
1 3 5 7 9
2 4 6 8 10
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
EWA 4NEB 812 6120-02 14-21

14.6.2 Digital Output Modules
Digital Output Module 4×24 V DC/0.5 A (6ES5 440-8MA11)
Address designation
(for ET 100U only) 4 DQ
Number of outputs 4
- in groups of 4
Load voltage L+
aaaaaaaaaaaaaaaaa
aaaaaaaaa
aaa
L+ - permissible range 20 to 30 V
1
F M (including ripple)
2 - value at t<0.5 s 35 V
aaaaaaaaaa
aaaaa
3
.0 Output current
.4 4 for ”1” signal
- rated value 0.5 A
- permissible range 5 to 500 mA
aaaaaaaaaaaa
aaaaaa
aaaaaaaaaa
aaaaa
5 - lamp load max. 5 W

.1
.5 6 Residual current
at ”0” signal max. 0.5 mA
aaaaaaaaaaaaaa
aaaaaaa
Output voltage
aaaaaaaaaa
aaaaa
7
.2 - ”1” signal max. L+ (- 1.2 V)
.6 8
Short-circuit protection short-circuit protected
output with autom.
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
9 switch on when the

.3
.7 10
short-circuit does not
exist any more
Fault LED (red) short-circuit/no
load voltage L+
Error diagnostics possible
aaaaaa
aaa
5
Voltage induced on circuit
interruption (internal) limited to - 15 V
Switching frequency
- resistive load max. 100 Hz
aaaaaaaaaa
DIGITAL OUTPUT - inductive load max. 2 Hz

4 x 24 V DC/0.5 A
6ES5 440-8MA11 Total permissible
1 2 3 4 5 6
current of outputs 2A
Driving of digital input possible

Paralleling of outputs possible
- maximum current 0.8 A
+9 V
GND Permissible ambient
Data
temperature
(32 to 140 °F)
(32 to 104 °F)
Length of cable
Rated insulation voltage * 12 V AC
(+9 V to )
aaaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaa
aaaaaaaaaaaaa
Current consumption
1 3 5 7 9
aaaaaaaa
aaaa
2 4 6 8 10
- from L+(without load) typ. 25 mA
aaaaaaaaaa
aaaaaaaaaa
aaaaa
aaaaaaaaaa
aaaaaaaaaaaaa
Power loss
L+ M of the module typ. 3W
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
X.0 X.1 X.2 X.3

14-22 EWA 4NEB 812 6120-02

Digital Output Module 4×24 V DC/2 A (6ES5 440-8MA21)
Address designation
Number of outputs 4
- in groups of 4
Load voltage L+
aaaaaaaaaaaaaaaaaa
aaaaaaaaa
aaa
L+ - permissible range 20 to 30 V
1
F M
2 Output current
3
aaaaaaaaaa
aaaaa
.0 for ”1” signal

.4 4 - rated value 2A
- permissible range 5 mA to 2 A
- lamp load max. 10 W
aaaaaaaaaaaa
aaaaaa
5
aaaaaaaaaa
aaaaa
.1 Residual current at
.5 6 ”0” signal max. 1 mA
Output voltage
- ”1” signal max. L+ (- 1.5 V)
aaaaaaaaaaaa
aaaaaa
7
aaaaaaaaaa
aaaaa
.2
.6 8 Short-circuit protection short-circuit protected
output with autom.
switch on when the
aaaaaaaaaaaa
aaaaaaaaaaaa

aaaaaaaaaa
aaaaa
9
.3 exist any more
.7 10
Fault LED (red) short-circuit/no
load voltage L+
aaaaaa
aaa
5 interruption (internal) limited to - 15 V

Switching frequency
- inductive load max. 2 Hz
aaaaaaaaaaa
DIGITAL OUTPUT Total permissible

4 x 24 V DC/2 A current of outputs 4A
6ES5 440-8MA21
1 2 3 4 5 6
Paralleling of outputs possible
Permissible ambient
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V
GND - horizontal arrangement 0 to 60 °C
Data (32 to 140 °F)
(32 to 104 °F)
Length of cable
Rated insulation voltage*
(+9 V to ) 12 V AC
Current consumption
- from L+ (without load) typ. 25 mA
aaaa
aaaaaa aaaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaaa
aaaaaaaaaaaaaa
aaa aaaaa
aaaaa
1 3 5 7 9
2 4 6 8 10
Power loss
aaaaaa
aaaaaa
aaa
L+ M Weight approx. 200 g (7 oz.)

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
X.0 X.1 X.2 X.3 * Relevant only for isolated assembly in the ET 100U
EWA 4NEB 812 6120-02 14-23

Digital Output Module 8×24 V DC/0.5 A (6ES5 441-8MA11)
Address designation
Number of outputs 8
- in groups of 8
Load voltage L+
aaa aaa aaa aaa aaa aaa aaa aaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
L+ - rated value 24 V DC
aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaa aaaaaa
1 - permissible range 20 to 30 V
M (including ripple)
2
- value at t<0.5 s 35 V
4
aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa
aaaa aaa aaa aaa aaa aaa aaa aaa
.0
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
3 ! Warning
.1
6 Capacitor remains loaded
.2 after switch off of L+
5
.3 Output current for
8 ”1” signal
.4 - rated value 0.5 A at 60 °C (140 °F)/
7
1 A at 30 °C (86 °F)
.5 - permissible range 5 mA to 1 A
10
”0” signal max. 1.0 mA
9
.7 Output voltage
- ”1” signal max. L+ (- 1.2 V)
Short-circuit protection none
aaaaaa
aaa
5 Voltage induced on circuit

Switching frequency
aaaaaaaaaa
DIGITAL OUTPUT - inductive load max. 2 Hz

8 x 24 V DC/0.5 A
6ES5 441-8MA11
Total permissible
current of outputs 4A
1 2 3 4 5 6
Paralleling of 2 outputs possible
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V
Data temperature of PLC
(32 to 140 °F)
(32 to 104 °F)
Length of cable
Rated insulation voltage*
(+9 V to ) 12 V AC
aaaaaa
aaaaaa aaaaaaaaaaaaa
C
Current consumption
aaaaaaaa
aaaaaaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaaaaaaaaaa
1 3 5 7 9 - from +9 V (CPU) typ. 14 mA

aaa aaaa
aaaaaaaa
aaaa
2 4 6 8 10 - from L+(without load) typ. 15 mA

Power loss
aaaaaa
aaaaaa
aaa
L+ M
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6
14-24 EWA 4NEB 812 6120-02

Digital Output Module 4×24 to 60 V DC/0.5 A (6ES5 450-8MB11)
Address designation
Number of outputs 4
- in groups of 4
aaaaaaaaaaaaaaaaa
aaaaaaaaa
aaa
L+ Load voltage L+
1
F M - rated value 24 to 60 V DC
2 - permissible range 20 to 72 V
3
aaaaaaaaaa
aaaaa
.0 Output current for

.4 4
”1” signal
- rated value 0.5 A
- permissible range 5 mA to 0.5 A
aaaaaaaaaaaa
aaaaaa
5
aaaaaaaaaa
aaaaa
.1 - lamp load max. 5 to 12 W

.5 6
Residual current at
”0” signal max. 1 mA
Short-circuit protection short-circuit protected
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
aaaaaa
7
.2 output with autom.
.6 8 switch on when the
exist any more
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
9
.3 Fault LED (red) short circuit/
.7 10 no load voltage L+
aaaaaa
5 Switching frequency
Total permissible current
of outputs 2A
DIGITAL OUTPUT
4 x 24 - 60 V DC/0.5A Driving of digital input possible
6ES5 450-8MB11
Paralleling of 2 outputs possible
1 2 3 4 5 6 - maximum current 2×0.4 A
Permissible ambient
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
+9 V - horizontal arrangement 0 to 60 °C
GND (32 to 140 °F)
(32 to 104 °F)
Length of cable
- (+9 V to L+) 60 V AC
(+9 V to ) 12 V AC
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaa
aaaaaaaaaaaaa

aaaaaaaa
aaaaaaaa
aaaa
1 3 5 7 9 - tested with 500 V AC

2 4 6 8 10
Current consumption
aaaaaa
aaaaaa
aaa
aaa
aaaaaaaaaaaa
L+ M - from L+ (without load) typ. 30 mA (at 60 V)

aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
X.0 X.1 X.2 X.3

Power loss of the
module typ. 5W
EWA 4NEB 812 6120-02 14-25

Digital Output Module 4×115 to 230 V AC/1 A (6ES5 450-8MD11)
Address designation
Number of outputs 4
- in groups of 4
Load voltage L1
aaaaaa aaaaaa
aaa aaa
L1 - rated value 115 to 230 V AC

1 - frequency max. 47 to 63 Hz
aaaaaa
aaa
F N - permissible range 85 to 264 V

2
3 Output current for
aaaaaaaaaa
aaaaa
.0
.4 4 ”1”signal
- rated value 1A
- permissible range 50 mA to 1 A
aaaaaaaaaaaa
5 - lamp load max. 25/50 W

aaaaaaaaaa
aaaaa
.1
.5 6 Contact current closing
rating: determined by the
size of the fuse
aaaaaaaaaa
aaaaa
aaaaaaaaaaaa
7
.6 8 ”0” signal max. 3/5 mA
Output voltage
- ”1” signal max. L1 (- 7 V)
aaaaaaaaaa
aaaaa
aaaaaa
aaaaaaaaaa aaaaaaaaaaaa
9
.3 Signal status display only with load
.7 10 (green LEDs) connected
Short-circuit protection fuse
aaaaaaaaaa
FF
10A (10 A extra fast)
(Wickmann No.
19231, or
aaaaaa
aaa
3 6ES5 980-3BC41)
Fault LED (red) fuse blown *
Switching frequency max. 10 Hz
Permissible current
aaaaaaaaaa
DIGITAL OUTPUT of all outputs 4A

4x115/230V AC/1A
6ES5 450-8MD11 Driving of digital input possible
1 2 3 4 5 6 Paralleling of outputs not possible
Permissible ambient
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
+9 V (32 to 140 °F)

GND
(32 to 104 °F)
Length of cable
(+9 V to L1) 250 V AC
(+9 V to ) 12 V AC
aaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaaaaaaaaaaaa

aaaaaaaa
aaaaaaaa
aaaa
1 3 5 7 9
2 4 6 8 10 Current consumption
Power loss of the
aaa
aaaaaaaaaa
aaaaaa
aaaaaa
aaaaaaaaaaaa
L1 N module typ. 3.5 W

aaaaaaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
aaaaaaaa
aaaaaaaa
aaaa
X.0 X.1 X.2 X.3 Weight approx. 315 g (11 oz.)
* Indication only given if load voltage is

applied and at least one load is connected
14-26 EWA 4NEB 812 6120-02

Digital Output Module 8 x 24 V DC/1 A (6ES5 451-8MA11)
Address designation
Number of outputs 8
- in groups of 8
Load voltage L+
aaaaaa aaaaaa
aaaaaa aaaaaa
aaa
L+ - permissible range
aaaaaa aaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaa aaaaaa
1
(including ripple) 20 to 30 V
F M - value at t<0.5 s 35 V
2
aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaa
aaaa aaa aaa aaa aaa aaaa aaa aaa
.0 "1" signal
3 - rated value 1A
.1 - permissible range 5 mA to 1A
6
5
"0" signal max. 1.0 mA
.3 Output voltage
- at "1" signal max. L+ (- 0.8 V)
8
.4 Short-circuit
protection short-circuit protected
7
.5 output with autom.
switch on when the
10 short-circuit does not
.6
exist any more
9 Fault LED (red) short-circuit
.7
Voltage induced on
circuit interruption
(internal) limited to -15 V
aaaaaa
5
Switching frequency
Permissible current
aaaaaaaaaa
DIGITAL OUTPUT
8 x 24 V DC/1 A of all outputs 6A
6ES5 451-8MA11 Driving of
1 2 3 4 5 6 digital input possible
Paralleling of 2
outputs possible
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V
Data
(32 to 140 °F)
(32 to 104 °F)
Length of cable
(+ 9 V to L+) 24 V AC
aaaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaaaaaa
aaaaa
aaaaaaaaaaaaa
aaaaa
aaaaaaaaaaaaa
1 3 5 7 9 Rated insulation voltage

aaaaaaaa
aaaa
2 4 6 8 10 (+ 9 V to ) 12 V AC
Current consumption
aaaaaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaa
aaaaaa
aaa
aaaaaaaa
aaaaaaaa
aaaa
L+ M X.1 X.0 X.3

X.2 X.5 X.4 X.7 X.6
- from L+ (without load) typ. 200 mA
Power loss
of the module typ. 4W
Weight approx. 230g (8 oz.)
EWA 4NEB 812 6120-02 14-27

Digital Output Module 8×115 to 230 V AC/0.5 A (6ES5 451-8MD11)
Address designation
Number of outputs 8
- in groups of 8
Load voltage L1
aaaaaa aaaaaa
aaaaaa aaaaaa
L1 - rated value 115 to 230 V AC

aaaaaa aaaaaaaaaaaaaaaaaa
1
- frequency max. 47 to 63 Hz
aaaaaa
aaa
2 N - permissible range 85 to 264 V

aaaaaa aaaaaa
aaa aaa
.0
”1” signal
3 - rated value 0.5 A
.1 - permissible range 50 mA to 0.5 A
- lamp load max. 25/50 W
aaaaaa aaaaaa
6
aaaaaa aaaaaa aaaaaaaa aaaaaa
aaa aaa aaaa aaa
.2
Contact current
5 closing rating: determined by the
.3 size of the fuse
aaaaaa
8 Residual current at
.4
”0” signal max. 3/5 mA
aaaaaa
7 Output voltage
.5
- at ”1” signal max. L1 (-7 V)
aaaaaa aaaaaaaaa
10
aaaaaa
aaa
.6 Signal Status Display only with load

(green LEDs) connected
9
aaaaaaaaaaaaaaa
aaaaaa
.7 Short-circuit protection fuse

aaaaaaaaaaaa
(10 A extra fast)

FF
(Wickmann No.
10A
19231, or
aaaaaa
3 6ES5 980-3BC41)
Permissible current
of all outputs 4A
aaaaaaaaaa
DIGITAL OUTPUT Driving of digital input possible

8 x 115/230 V AC/0.5 A
6ES5 451-8MD11 Paralleling of outputs not possible
1 2 3 4 5 6
Permissible ambient
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V (32 to 140 °F)

GND - vertical arrangement 0 to 40 °C
Data (32 to 104 °F)
Length of cable
(+9 V to L1) 250 V AC
(+9 V to ) 12 V AC
aaaaaaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaa
aaaaaaaaaaaa
aaaaaaaa
aaaaaaaaaaaaaa
1 3 5 7 9
aaaaaaaa
aaaa
2 4 6 8 10
Current consumption
Power loss of the
aaaaaaa
aaaaaaaaaaaaaa
module typ. 3.5 W

aaaaaa
aaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
aaaaa
L1 N X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6 Weight approx. 270 g (9 oz.)
14-28 EWA 4NEB 812 6120-02

S5-100U
L+
aaaaaaaaaa
aaaaaaaaaa
1
aaaaa aaaaaaaaaaaaaaaaaaaa
M
2
aaaaaaaaaaaaaaaaaaa
1 2
aaaaaaaa aaaaaa aaaaaaaaaaaaaaaaaaaa
43 V
aaaaaaaaaaaaaa
3
aaaaaaaa aaaaa aaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa
.7
.6
.5
.4
.3
.2
.1
.0
EWA 4NEB 812 6120-02

aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa
4
2
1
4
aaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa
aaaaaaaaaa
5
9
7
8
5
6
3
4
10
M
5
L+
aaaaaaaa aaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaa
6ES5 453-8MA11
aaa aaa aaa aaa aaa
6
aaaaaaaa aaaaaaaaaaaaaaaaaaaa
8 x 5...24 V DC/0,1 A
aaa aaa aaaaaaaaaaaa
6
8
aaaaaaaaaaaaaaa aaaaaa
DIGITAL OUTPUT
aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaa
7
aaaaaaaa aaaaaaaaaa aaaaaaaaaa
aaaaa
8
aaaaaaaa aaaaaaaaaa
aaaaaaaa
9
aaaaaaaa aaaaa
X.1 X.0 X.3 X.2 X.5 X.4 X.7 X.6

10
aaaaaaaa aaaaaaaaaaaaaaa
aaaa aaaaa aaaaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
Digital Output Module 8×5 to 24 V DC/0.1 A

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Weight
module
”1” signal
2 outputs
- from L+
(+9 V to )
- tested with
- unshielded
- rated value
- rated value
Paralleling of
- in groups of
- resistive load
Output voltage
- inductive load
(without load)
Length of cable
Insulation rating
Load voltage L+
- value at t<0.5 s
Power loss of the

- insulation group
Output current for

Galvanic isolation
(including ripple)
- from +9 V (CPU)
(for ET 100U only)
Number of outputs
- permissible range
Switching frequency
Permissible ambient
Address designation
Current consumption
switching to M potential
typ.
typ.
typ.
max.
max.
max.
interruption (internal) limited to
* transistor with open collector,

approx.
8
8
yes
1W
1×B
2 Hz
35 V
none
8 DQ
28 mA
20 mA
100 Hz
100 mA
possible
12 V AC
500 V AC
0 to 40 °C
0 to 60 °C
VDE 0160
4.75 to 30 V
220 g (8 oz.)
5 to 24 V DC
(32 to 104 °F)

(32 to 140 °F)
100 m (330 ft.)

- 19 V (at 24 V)
TTL-compatible *
(6ES5 453-8MA11)
Module Spectrum
14-29
X.3
X.2
X.1
X.0
aaaaaa aaaaaa aaaaaa aaaaaa
aaaa
M
.3
.2
.1
.0
aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa
9
7
5
3
1
aaaa
14-30
19
17
15
13
11
aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaaaa
aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaa aaa aaa aaa aaa
F
aaaaa aaaaaaaaaa
A
aaaaaaaaaa
9
7
5
3
1
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaa aaaaaa aaaaaaaaaaaaaa
19
17
15
13
11
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaa aaaaaaaaaa
aaaaaa aaaaaa aaaa aaaaaaaaaaaa
5
3
13
11
aaaaaaaaaaaa
Module Spectrum
7
1 2 3
5
3
8×30 V DC
13
11
M
aaaaaa aaaaaaaaaaaa
9
7
5
3
1
19
17
15
13
11
aaa aaaaaaaaaaaa
.+24V
aaaaaaaa aaaaaa aaaaaa aaaaaaaa
.7
.6
.5
.4
aaaaaaaa aaaaaa aaaaaa aaaaaaaa aaaaaaaaaaaa
RELAY OUTPUT
aaaaaaaaaaaa
aaaaaa
L+
aaaaaa
Screw Plug Connector, 40-pin

9
8
7
6
5
4
3
2
1
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
20
19
18
17
16
15
14
13
12
11
10
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Crimp Snap-in Connector, 40-pin

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaa
B
aaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaa
9
7
5
3
1
19
17
15
13
11
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaaa
aaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaa aaaaaaa
Relay Output Module 8 x 30 V DC/230 V AC

aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
10
aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
X.7
X.6
X.5
X.4
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Weight
Outputs
- AC - 11
- from L+
- DC - 11
Relay type
Power loss
- ripple VPP
(+ 9 V to )
- tested with
- tested with
- tested with
- unshielded
- rated value
(+ 9 V to L 1)
- in groups of
(for the relay)
of the module
- resistive load
of the contacts
- inductive load
Fault LED (red)
Length of cable
Insulation rating
(ripple included)
- insulation group
- insulation group
- insulation group
- value to t <0.5 s
Galvanic isolation
Supply voltage L+
(for ET 100U only)
Switching capacity
- from + 9 V (CPU)
(between contacts)
- permissible range
Operating cycles of
VDE 0660, part 200
Switching frequency
Permissible ambient
Address designation
Current consumption
Continuous current Ith

the contacts according to

typ.
typ.
typ.
max.
max.
max.
max.
max.
approx.
3A
yes
35 V
2xB
1xB
2xB
3.6 V
8 DQ
1.6 W
10 Hz
70 mA
30 mA
1 x 106
12 V AC
24 V DC
0.5 x 106
500 V AC
250 V AC
250 V AC
S07-K275
0 to 40 °C
0 to 60 °C
VDE 0160
20 to 30 V
1500 V AC
1500 V AC
2 with signal
status display
(32 to 104 °F)

(32 to 140 °F)
300 g (11 oz.)

varistor SIOV-
100 m (330 ft.)

Dold OW 5699
8 relay outputs,
no input voltage
3 A at 250 V AC
1.5 A at 30 V DC
0.5 A at 30 V DC
contact switching
0.5 A at 250 V AC
(6ES5 490-8MB11)
(6ES5 490-8MB21)
(6ES5 451-8MR12)
(6ES5 490-8MA12)
EWA 4NEB 812 6120-02

S5-100U
Relay Output Module 4 x 30 V DC/230 V AC (6ES5 452-8MR11)
Address designation
Outputs 4 relay outputs,
contact switching
varistor SIOV-S07-
K275
aaaaaaaaaaaa
aaaaaaaaaaaa
aaa
L+
aaaaaaaaaaaaaaaa
1
2
M - in groups of 1
3 Continuous current Ith 5A
aaaaaaaaaa
aaaaaaaaaa
.0
.4 Relay type Siemens
aaaaaaaaaa
aaaaaaaaaa
V 23127-D 0006-
aaaaaaaaaa
4 A402
aaaaaaaaaa
aaaaaaaaaa
.1 5 Switching capacity
.5 of the contacts
- resistive load max. 5 A at 250 V AC
aaaaaaaa
aaaaaaaa
2.5 A at 30 V DC
aaaaaaaa
6 - inductive load max. 1.5 A at 250 V AC

aaaaaaaaaa
aaaaaaaaaa
.2 7 0.5 A at 30 V DC
.6
Operating cycle of
aaaaaaaa
aaaaaaaa
the contacts according to

aaaaaaaa
8 VDE 0660, part 200

aaaaaaaaaa
aaaaaaaaaa
.3 9 - AC-11 1.5 x 10 6
.7 - DC-11 0.5 x 10 6
aaaaaaaa
aaaaaaaa

aaaaaa
aaaaaa
10
Permissible ambient
aaaaaa
7 (32 to 140 °F)

(32 to 104 °F)
Length of cable
RELAY OUTPUT
4 x 30 V DC/230 V AC Insulation rating VDE 0160
6ES5 452-8MR11
1 2 3 4 5 6
(+ 9 V to L1) 250 V AC
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
+9 V (+ 9 V to ) 12 V AC
GND
Data - insulation group 1xB
(between contacts) 250 V AC
Supply voltage L+
(for the relay)
- ripple Vpp max. 3.6 V
- permissible range
(ripple included) 20 to 30 V
aaaaaaaa
aaaaaaaaaaaa aaaa
aaaaaaaaaaaaaaaaaa aaaaaaaa
aaaaaaaaaaaaa aaaa
aaaaaaaaaaaaa aaaaaaaa
1 3 5 7 9 Current consumption
aaaaaaaaaaaaaaaaaa
2 4 6 8 10 - from + 9 V (CPU) typ. 14 mA

aaaaaaaaaa
aaaaaaaaaa
L+ M Power loss of
the module typ. 2W
aaaaaaaa
X.0 X.1 X.2 X.3

EWA 4NEB 812 6120-02 14-31

14-32
n
M
.7
.6
.5
.4
.3
.2
.1
.0
M
.7
.6
.5
.4
.3
.2
.1
.0
Module Spectrum
L+
L+
n+1
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
mA
100
aaaaaaaaaaaaaaaaaa
n+1
n
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa
X.7
X.6
X.5
X.4
500X.3
X.2
X.1
X.0
X.7
X.6
mA X.5
X.4
X.3
X.2
X.1
X.0
OUT
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa
aaaaaaaa aaaaaaaa
F
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaa
aaaa aaaaaaaa
M L+
M L+
.7
.0
.7
.0
aaaaaaaa aaaaaaaa aaaaaaaaaa
0.5A
0.1 A
aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa aaaaaaaa
6
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaa aaaaaaaaaa
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
10
aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaa aaaaaaaa
1 2 3
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
DIGITAL
Crimp Snap-in Connector, 40-pin
32x24V DC
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa
F
aaaaaaaa
n
L+
M
n+1
NC
NC
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
n
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaa
n+1
IN
aaaaaaaaaaaaaaaaaa
aaaa
14.6.3 Digital Input/Output Modules
Digital Input/Output Module with LED Display

aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
10
aaaaaaaa
180 K
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
10
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
9
8
7
6
5
4
3
2
1
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
20
19
18
17
16
15
14
13
12
11
10
M
aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
L+
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
X.7
X.6
X.5
X.4
X.3
X.2
X.1
X.0
+9 V
NC
NC
Data
X.7
X.6
X.5
X.4
X.3
X.2
X.1
X.0
GND
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
(6ES5 490-8MB11)
(6ES5 490-8MA12)
(6ES5 482-8MA12)
S5-100U
EWA 4NEB 812 6120-02

Digital Input/Output Module with LED Display (continued) 6ES5 482-8MA12)

aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Address designation Rated insulation voltage
(for ET 100U only) 1 AX (+9 V to ) 12 V AC
Permissible ambient - insulation group 1xB
temperature of the unit Power loss of the module typ. 4.5 W
(32 to 140 °F) Weight approx. 190 g (7 oz.)
(32 to 104 °F)
Cable length
- unshielded 100 m (330 ft.)
Input side Output side | 100 mA 500 mA

|
Number of inputs 16 Number of outputs |
Galvanic isolation no - pins 2 through 9 8 |
- in groups of 16 - pins 12 through 19 | 8
Galvanic isolation no | no
Input voltage L+ - in groups of 8 | 8
- rated value 24 V DC |
- for ”0” signal 0 to 5 V Output current IN |
- for”1” signal 13 to 30 V with ”1” signal |
- rated value 100 mA | 500 mA
Input current - permissible range 5 to 100 mA | 5 to 500 mA
with ”1” signal typ. 4.5 mA |
Residual current |
Inherent delay with ”0” signal max. 0.6 mA | max.1 mA
- from ”0” to ”1” typ. 4 ms |
- from ”1” to ”0” typ. 3 ms Short-circuit protection yes | yes
|
Fault LED (red) indicates Short-circuit indication red LED | red LED
interruption of |
L+/M supply Current consumption |
- from +9 V (CPU) typ. 5 mA | typ. 5 mA
Connection of - from L+ (without load) typ. 35 mA | typ. 120 mA
two-wire BERO |
proximity switches possible Lamp load max. 2 W | max.10 W
Load voltage L+
Current consumption - rated value 24 V DC
- from +9 V (CPU) typ. 50 mA - permissible range 20 to 30 V
(ripple included)
Output voltage with
”1” signal L+(- 0.8 V)
Switching frequency with

- resistive load 100 Hz
- inductive load 2 Hz

interruption (internal)
limited to - 15 V
Permissible total current
of the outputs 4A
Driving of a digital input possible
Paralleling of outputs possible in pairs

- maximum current (0.8×IN)
EWA 4NEB 812 6120-02 14-33

14.7
14-34
Module Spectrum
aaaaaaaaaa
box
sating
aaaaaaaaaa
Analog Modules
Compen-
aaaaaaaaaa
Analog Input Module 4×±50 mV
+
aaaaaaaaaa aaaaaaaa
-
1
aaaaaaaaaaaaaaaaaa
aaaa aaaaaaaaaaaaaaaaaaaa
14.7.1 Analog Input Modules
2
2
+
aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
3
-
aaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa
Ch.0
4
1+
2-
aaaaaaaaaa aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
+
mode
aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaa aaa
4 x±50 mV
9+
7+
5+
3+
8-
6-
4-
10 -
5
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa
Comp.
5
aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaaaa
operating
-
6ES5 464-8MA11
aaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaaaa
6
broken wire
Ch.1
1
2
3
4
6
6
aaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa aaaaaa
ANALOG INPUT
+
Ch.3
Ch.2
Ch.1
Ch.0
aaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaa aaa
-
Ch.2
8
aaaaaaaaaaaaa aa aaaaaaaaaaaa
+
9
aaaaaaaaaaaaaaaaaa aaaaaa
Fe Ko
wire
Cu Cu
Ch.3
aaaaaaaaaa aaaa aaaa
broken
10
aaaaa aaaaaaaaaaa
aaaa
aaaaaaaa
aaaa aaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaa
aaaaaaaaaa
Terminal box
aaaaaaaaaa
(6ES5 464-8MA11)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 4×±50 mV (continued) (6ES5 464-8MA11)
Noise suppression
Address designation for f=nx
(for ET 100U only) 4 AI (50/60 Hz±1%);
n=1, 2, ...
Input ranges - common-mode
(rated values) ±50 V rejection min. 86 dB
(Vpp=1 V)
Number of inputs 1, 2 or 4 - series-mode rejection min. 40 dB
(selectable) (peak value of noise
<rated value of
Galvanic isolation yes (inputs to input range)
grounding point;
not between inputs) Basic error limits ±0.15 %
Input resistance 10 M Operational error limits ±0.4 %
(0 to 60 °C)
Connection method two-wire (32 to 140 °F)
of sensors connection
Single errors
Digital representation 12 bits+sign - linearity ±0.05 %
of input signal (2048 units - tolerance ±0.05 %
= rated value) - polarity reversal error ±0.05 %
Measured value two's complement Temperature error
representation (left-justified) - final value ±0.01 %/K
- zero point ±0.002 %/K
Measuring principle integrating
Length of cable
Conversion principle voltage-time - shielded max. 50 m (164 ft.)
conversion
(dual slope) Supply voltage L+ none
Integration time 20 ms at 50 Hz Connection of com-
(adjustable for optimum 16.6 ms at 60 Hz pensating box possible
noise suppression)
Encoding time
per input Rated insulation voltage
- for 2048 units max. 60 ms at 50 Hz (+9 V to ) 12 V AC
max. 50 ms at 60 Hz - insulation group 1×B
- for 4095 units max. 80 ms at 50 Hz - tested with 500 V AC
max. 66.6 ms at 60 Hz
Permissible voltage (inputs to+9 V) 60 V AC
difference - insulation group 1×B
- between inputs max. ±1V - tested with 500 V AC
- between inputs and
central ground point max. 75 V DC/60 V AC Current consumption
- from+9 V (CPU) typ. 70 mA
Permissible
input voltage Power loss of the
(destruction limit) max. 24 V DC module typ. 0.7 W
Fault indication for Weight approx. 230 g (8 oz.)
- range exceeded yes
(more than
4095 units)
- sensor wire break yes (selectable)
- general indication of wire

break red LED
EWA 4NEB 812 6120-02 14-35

14-36
Module Spectrum
+
aaaaaaaaaa
1
aaaaaa
-
aaaaaa aaaaaaaaaaaaaaaaaa
Comp.
2
aaaaaaaaaaaa
+
Analog Input Module 4 x ± 50 mV
1
aaaaaa aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
3
aaaaaaaa
-
2
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
Ch.0
aaaaaaaa
4
3
aaaa aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
+
aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa aaaaaa
5
aaaaaaaa aaaaaa
-
mode
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaa
4 x±50 mV
9+
7+
5+
3+
1+
8-
6-
4-
2-
10 -
Ch.1
5
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
6
aaaa aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaa aaaa aaaaaaaa aaaaaaaaaaaa
+
6ES5 464-8MA21
aaaaaa
Comp.
6
broken wire
aaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
7
6
operating 1
2
3
4
5
6
7
8
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
-
ANALOG INPUT
Ch.3
Ch.2
Ch.1
Ch.0
aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaaaaaaa aaa
Ch.2
8
aaaaaaaa aaaaaa aaaaaa
+
aaaaaa aaaaaa aaaaaaaaaaaaaa aaaaaaaa
9
aaaaaaaa aaaaaaaa aaaaaaaa
-
wire
Fe Ko
Cu Cu
aaaaaa aaaaaa aaaaaaaa
Ch.3
broken
aaaaaaaa aaa aaa aaaaaaaaaaaaaaa
10
aaaa aaaaaaaaaa aaaaaaaa
aaaa aaaaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaa
(6ES5 464-8MA21)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 4 x ± 50 mV (continued) (6ES5 464-8MA21)
Noise suppression
Address designation for f = nx
(for ET 100U only) 4 AI (50/60 Hz±1%)
n = 1, 2, ...
Input range - common mode rejection min. 86 dB
(rated values) ± 50 mV (Vpp = 1 V)
Number of inputs 1, 2 or 4 - series mode rejection min. 40 dB
(selectable) (peak value of noise
< rated value of
Galvanic isolation yes (inputs to input range)
grounding point;
not between Basic error limits ±0.15%
inputs)
Operating error limits ±0.4%
Input resistance 10 M (0 to 60 °C)
(32 to 140 °F)
Connection method two-wire
of sensors connection Single errors
- linearity ±0.05%
Digital representation 12 bits + sign - tolerance ±0.05%
of input signal (2048 units = - polarity reversal error ±0.05%
rated value)
Temperature error
Measured value two's complement - final value ±0.01 %/K
representation (left-justified) - zero point ±0.002 %/K
Measuring principle integrating Linearization exactness

for rated range
Conversion principle voltage-time (for types J,K,L) ±1 °C (1.8 °F)
conversion
(dual slope) Characteristic lineari-
zation for the following
Integration time 20 ms at 50 Hz thermoelements
(adjustable for optimum 16.6 ms at 60 Hz - Nickel-Chromium/
noise suppression) Nickel-Aluminium (Type K) IEC 584
- Iron/Copper-Nickel (Type J) IEC 584
Encoding time - Iron/Copper-Nickel (Type L) DIN 43710
per input
- for 2048 units max. 60 ms at 50 Hz Length of cable
max. 50 ms at 60 Hz - shielded max. 50 m (164 ft.)
- for 4095 units max. 80 ms at 50 Hz
max. 66.6 ms at 60 Hz Supply voltage L+ none
Permissible voltage Connection of

difference compensating box possible
- between inputs max. ±1 V
- between inputs and Insulation rating VDE 0160
central ground point max. 75 V DC/60 V AC
(+9 V to ) 12 V AC
Permissible - insulation group 1xB
input voltage - tested with 500 V DC
(destruction limit) max. 24 V DC
Fault indication for (inputs to + 9 V) 60 V AC
- range exceeded yes (more than - insulation group 1xB
4095 units) - tested with 500 V AC
- general indication Current consumption
of wire break red LED - from + 9 V (CPU) typ. 100 mA
Power loss of the

module typ. 0.7 W
EWA 4NEB 812 6120-02 14-37

14-38
Module Spectrum
1
aaaaaaaaaa
aaaaa
Analog Input Module 4 x ± 1 V

a a
2
+
aaaaaaaaaaaaaaaa
-
aaaaaa aaaaaaaaaaaaaaaaaaaa
Ch.0
aaaaaa aaaaaaaaaaaaaaaaa
4
+
aaaaaaaaaaaaaa
2
5
aaaaaa aaaaaaaaaaaaaaa
Ch.1
3
aaaaaa aaaaaaaaaaaaaaaaa aaaaaa
6
- +
4
aaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaa aaa aaaaaa
4 ×± 1V
9+
7+
5+
3+
8-
6-
4-
aaaaaaaa
mode
10 -
7
aaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaaaa aaaaaa
-
5
Ch.2
operating
aaaaaa aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
6ES5 464-8MB11
8
6
broken wire
+
1
2
3
4
Ch.3
Ch.2
Ch.1
Ch.0
aaaaaaaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa
ANALOG INPUT
aaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaa aaa aaa aaa aaaaaaaaaaaaaaaaa aaa
-
aaaaaaaaaaaaaaaaaaaa aaa
wire
Ch.3
aaaaaa aaaaaaaa
broken
aaa aaaaaaaaaaaaaaaaa
10
aaaaaaaa aaaaaaaa
aaaa aaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaa
aaaaaaaaaaaa
(6ES5 464-8MB11)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 4 x ± 1 V (continued) (6ES5 464-8MB11)
Noise suppression
Address designation for f=nx
(for ET 100U only) 4 AI (50/60 Hz±1%);
n=1, 2, ...
Input ranges - common-mode
(rated values) ±1V rejection (Vpp=1 V) min. 86 dB
- series-mode rejection min. 40 dB
Number of inputs 1, 2 or 4 (peak value of noise
(selectable) < rated value of
input range)
Galvanic isolation yes (inputs to
grounding Basic error limits ±0.1 %
point; not between
inputs) Operational error limits ±0.35 %
(0 to 60 °C)
Input resistance 10 M (32 to 140 °F)
Connection method two-wire Single errors
of sensors connection - linearity ±0.05 %
- tolerance ±0.05 %
Digital representation 12 bits+sign - polarity reversal error ±0.05 %
of input signal (2048 units
= rated value) Temperature error
- final value ±0.01 %/K
Measured value two's complement - zero point ±0.002 %/K
representation (left-justified)
Length of cable
Measuring principle integrating - shielded max. 200 m (660 ft.)
Conversion principle voltage-time Supply voltage L+ none
conversion
(dual slope) Connection of com-
pensating box not possible
Integration time 20 ms at 50 Hz
(adjustable for optimum 16.6 ms at 60 Hz Insulation rating VDE 0160
noise suppression)
Encoding time (+9 V to ) 12 V AC
per input - insulation group 1×B
max. 50 ms at 60 Hz
- for 4095 units max. 80 ms at 50 Hz Rated insulation voltage
max. 66.6 ms at 60 Hz (inputs to +9 V) 60 V AC
Permissible voltage - tested with 500 V AC
difference
- between inputs max. ± 1V Current consumption
- between inputs and - from+9 V (CPU) typ. 70 mA
Power loss of the
Permissible module typ. 0.7 W
input voltage
(destruction limit) max. 24 V DC Weight approx. 230 g (8 oz.)
Fault indication for
- range exceeded yes (more than
4095 units)
- general indication of
wire break red LED
EWA 4NEB 812 6120-02 14-39

14-40
Module Spectrum
1
aaaaaaaaaa
a a aaaaa
2
+
Analog Input Module 4 x ± 10 V
aaaaaaaaaaaaaaaa aaaaaaaaaa
1
-
47 k
Ch.0
2
aaa aaaaaaaaaaaaaaaaa aaaaaaaaaa
4
+
3
aaaaaa aaaaaaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaa
5
4
aaaaaaaaaaaaaaa
Ch.1
aaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaa
2,5 k
mode
4 x ± 10 V
9+
7+
5+
3+
8-
6-
4-
aaa aaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaa
6
5
10 -
- +
aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaa
operating
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
6ES5 464-8MC11
6
aaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaa
-
1
2
3
4
aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa
Ch.2
Ch.3
Ch.2
Ch.1
Ch.0
ANALOG INPUT
aaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaa
aaa aaaaaaaaaaaaaaaaa aaaaaaaaaa aaa aaaaaa aaaaaa aaaaaa aaaaaa
8
+
aaaaaaaaaaaaaa
9
aaaaaa
-
Ch.3
aaaaaa
aaa aaaaaaaaaaa
10
+9 V
Data
GND
aaaaaaaaaaaa
aaaaaaaaaaaa
(6ES5 464-8MC11)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 4 x ± 10 V (continued) (6ES5 464-8MC11)
Address designation Noise suppression
(for ET 100U only) 4 AI for f=nx
(50/60 Hz±1%);
Input ranges n=1,2, ...
(rated values) ±10 V - common-mode min. 86 dB
rejection (Vpp=1 V)
Number of inputs 1, 2 or 4
(selectable) - series-mode rejection min. 40 dB
(peak value of noise
Galvanic isolation yes (inputs to < rated value of
grounding point; input range)
not between inputs)
Basic error limits ±0.2 %
Input resistance 50 k
Operational error limits ±0.45 %
Connection method two-wire (0 to 60 °C)
of sensors connection (32 to 140 °F)
Digital representation 12 bits+sign Single errors

of input signal (2048 units =rated - linearity ±0.05 %
- tolerance ±0.05 %
value)
- polarity reversal error ±0.05 %
Measured value two's complement
representation (left-justified) Temperature error
- final value ±0.01 %/K
Measuring principle integrating - zero point ±0.002 %/K
Conversion principle voltage-time Length of cable

conversion - shielded max. 200 m (660 ft.)
(dual slope)
Supply voltage L+ none
Integration time 20 ms at 50 Hz
(adjustable for optimum 16.6 ms at 60 Hz Connection of
noise suppression) compensating box not possible
Encoding time Insulation rating VDE 0160

per input
max. 50 ms at 60 Hz (+9 V to ) 12 V AC
- for 4095 units max. 80 ms at 50 Hz - insulation group 1×B
max. 66.6 ms at 60 Hz - tested with 500 V AC
Permissible voltage Rated insulation voltage

(inputs to +9 V) 60 V AC
difference
- between inputs max. ±1 V - insulation group 1×B
- between inputs and - tested with 500 V AC
Current consumption
Permissible
input voltage
(destruction limit) max. 50 V DC Power loss of the
module typ. 0.7 W
- range exceeded yes (more than Weight approx. 230 g (8 oz.)
4095 units)
- sensor wire break no
- general indication of
wire break no
EWA 4NEB 812 6120-02 14-41

14-42
Module Spectrum
1
aaaaaaaa
1
a a a aaaa aaaaaaaaaaaaaaaaaaaaaa
2
2
+
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
aaaaaa aaaaaaaaaaaaaaaaaaaaaa
3
3
Analog Input Module 4 x ± 20 mA
aaaa aaaaaaaa
Ch.0
aaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
4
aaa
4
+
aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
mode
9+
7+
5+
3+
8-
6-
4-
aaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaaaa
5
4 x ± 20 mA
10 -
25
aaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
5
operating
aaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
6ES5 464-8MD11
Ch.1
6
aaaaaa aaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
1
2
3
4
aaa aaaaaa aaaaaa aaaaaa aaaaaa
6
6
+
Ch.3
Ch.2
Ch.1
Ch.0
ANALOG INPUT
aaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaaaaaaaaaa
aaaaaa aaaaaaaaaaa aaa aaaaaa aaaaaa aaaaaa aaaaaa
7
aaaa aaaaaaaa
Ch.2
aaaaaa aaaa
aaa
8
+
aaaaaaaaaaaaaaaaaaa
9
aaaaaa aaaa aaaaaaaa
Ch.3
aaaaaa
aaa aaaaaaaaaa
10
aaaaaaaaaa aaaaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
(6ES5 464-8MD11)
S5-100U
EWA 4NEB 812 6120-02

break
per input
S5-100U
difference
of sensors
Permissible
Input ranges
input voltage
(rated values)
of input signal
Encoding time
representation
- for 4095 units

- for 2048 units
Integration time
Input resistance
Measured value
- between inputs
(destruction limit)
Number of inputs
- range exceeded
Galvanic isolation

(for ET 100U only)
noise suppression)
- sensor wire break

Permissible voltage
Measuring principle
Connection method
Conversion principle
Address designation

central ground point
Digital representation
EWA 4NEB 812 6120-02

(adjustable for optimum

max.
max.
max.
max.
max.
max.
max.
no
no
4 AI
±1 V
25 k
80 mA
±20 mA
1, 2 or 4
two-wire
integrating
conversion
connection
4095 units)
(2048 units
(selectable)
(dual slope)
12 bits+sign
voltage-time
(left-justified)
=rated value)
yes (inputs to
yes (more than

80 ms at 50 Hz
50 ms at 60 Hz
60 ms at 50 Hz
20 ms at 50 Hz
between inputs)
66.6 ms at 60 Hz
16.6 ms at 60 Hz
75 V DC/60 V AC
two's complement
grounding point; not
Analog Input Module 4 x ± 20 mA (continued)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Weight
module
for f=nx
(+9 V to
n=1,2, ...
- linearity
- shielded
- tolerance
- zero point
- final value
(0 to 60 °C)
- tested with
- tested with
)
Single errors
input range)
(32 to 140 °F)
pensating box
(inputs to +9 V)
Length of cable
(50/60 Hz±1%);
Insulation rating
<rated value of
- common-mode
Basic error limits
Power loss of the

- insulation group
- insulation group
Supply voltage L+
- from +9 V (CPU)
Temperature error
Noise suppression
Connection of com-
rejection (Vpp=1 V)
Current consumption
- polarity reversal error

Operational error limits
- series-mode rejection

typ.
typ.
min.
min.
max.
approx.
1×B
1×B
none
0.7 W
40 dB
86 dB
70 mA
±0.2 %
±0.05 %
±0.05 %
±0.05 %
±0.45 %
60 V AC
12 V AC
500 V AC
500 V AC
VDE 0160
±0.01 %/K
±0.002 %/K
not possible
230 g (8 oz.)
200 m (660 ft.)

(6ES5 464-8MD11)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Module Spectrum
14-43
14-44
Module Spectrum
aaaaaa
L+
aaaaaa
1
aaaaaaaa
1
aaaa aaaaaaaaaaaaaaaaaaaaaa
M
aaaaaa a a a
2
2
+
aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
3
3
aaaa aaaaaaaa
Ch.0
Analog Input Module 4 x ± 4 to 20 mA
aaaaaa aaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaaaa
4
aaa
4
+
2
1
mode
31,2
9+
7+
5+
3+
8-
6-
4-
aaaaaaaaaaaaaaaaaaa aaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaa aaaaaa aaaaaaaaaaaaaaaa
5
10 -
aaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
5
4 x 4 ... 20 mA
operating
aaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaa aaaaaaaaaa
6ES5 464-8ME11
Ch.1
6
aaaaaa aaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aa aaaaa
M
L+
1
2
3
4
aaa aaaaaa aaaaaa aaaaaa aaaaaa
6
6
+
Ch.3
Ch.2
Ch.1
Ch.0
ANALOG INPUT
aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaa aaaaaa
aaaaaa aaaaaaaaaaa aaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaaa aaaaaaaaaaaaaaaaaaaaaaa
7
24V
aaaa aaaaaaaa aaaaaa
Ch.2
aaaaaa aaaa
aaa aaa aaaa
8
+
aaaaaaaaaaaaaaaaaaa aa
9
aaaaaa aaaa aaaaaaaa
Ch.3
aaaaaa
aaa aaaaaaaaaa
10
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
(6ES5 464-8ME11)
EWA 4NEB 812 6120-02

S5-100U
S5-100U
break
per input
difference
of sensors
Permissible
Input ranges
input voltage
(rated values)
of input signal
Encoding time
representation
- for 4095 units

- for 2048 units
Integration time
Input resistance
Measured value
- between inputs
(destruction limit)
Number of inputs
- range exceeded
Galvanic isolation

(for ET 100U only)
noise suppression)
- sensor wire break

Permissible voltage
Measuring principle
Connection method
EWA 4NEB 812 6120-02

Conversion principle
Address designation

central ground point
(adjustable for optimum


max.
max.
max.
max.
max.
max.
max.
no
no
4 AI
±1 V
80 mA
ducers
31.25 k
1, 2 or 4
integrating
conversion
4095 units)
(2048 units
(selectable)
(dual slope)
12 bits+sign
±4 to 20 mA
voltage-time
(left-justified)
=rated value)
yes (inputs to
yes (more than

80 ms at 50 Hz
50 ms at 60 Hz
60 ms at 50 Hz
20 ms at 50 Hz
between inputs)
66.6 ms at 60 Hz
16.6 ms at 60 Hz
75 V DC/60 V AC
for 2/4 wire trans-
two's complement
two-wire connection
grounding point; not
Analog Input Module 4 x ± 4 to 20 mA (continued)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Weight
module
for f=nx
- from L+
- linearity
n=1, 2, ...
- shielded
- tolerance
- ripple Vpp
- zero point
- final value
(0 to 60 °C)
(+9 V to )
- tested with
- tested with
- rated value
Single errors
input range)
(32 to 140 °F)
pensating box
(inputs to +9 V)
Length of cable
(50/60 Hz±1%);
Insulation rating
<rated value of
- common-mode
Basic error limits
Power loss of the

- insulation group
- insulation group
Supply voltage L+
- from +9 V (CPU)
Temperature error
Noise suppression
- permissible range
Connection of com-
rejection (Vpp=1 V)
Current consumption
for 2-wire transducers


- series-mode rejection

- for 4-wire transducers typ.

- for 2-wire transducers typ.
typ.
typ.
min.
min.
max.
approx.
1×B
1×B
3.6 V
0.7 W
1.0 W
40 dB
86 dB
80 mA
70 mA
±0.4 %
±0.05 %
±0.05 %
±0.15 %
60 V AC
12 V AC
24 V DC
500 V AC
500 V AC
VDE 0160
20 to 30 V
±0.01 %/K
±0.002 %/K
not possible
230 g (8 oz.)
200 m (660 ft.)

(6ES5 464-8ME11)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
Module Spectrum
14-45
14-46
Module Spectrum
aaaaaa
aaaaaa
1
aaaaaa
2×PT100
aaaaaa aaaaaaaa
2
+
aaaaaaaaaaaaaa
3
aaaaaaaa aaaa
-
aaaaaa
Ch.0
aaaaaaaa aaaa
4
+
aaaaaaaaaaaaaa
2
5
aaaaaaaa aaaa
Analog Input Module 2×PT 100/± 500 mV
-
3
Ch.1
aaaaaaaa aaaa aaaa aaaaaa
6
+
4
10
6
5
9
8
4
3
7
aaaaaaaaaaaaaa aaaaaaa aaaaaa
mode
2×Pt100
aaaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaa
7
5
aaaaaa aaaa aaaa aaaaaaaaa aaaaaa
IC0
aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
operating
M-
M-
IC-
IC-
M+
M+
IC+
IC+
6ES5 464-8MF11
aaaaaa aaaaaaaa aaaa aaaaaaaa aaaaaa
broken wire
8
Ch.1
Ch.0
aaaaaaaaaaaaaaaaaaaa aaaa aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa
1
2
3
4
+
6
aaaaaaaaaaaaaa aaa aaaaa aaaaaa
ANALOG INPUT
aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaa aaaaa aaaaaaaaaaaa
9
aaaaaa aaaaaaaa aaaaaaaa
-
wire
IC1
aaaaaaaa
broken
10
aaaaaaaaaa aaaaaaaa
aaaa aaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaa
(6ES5 464-8MF11)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 2×PT 100/± 500 mV (continued) (6ES5 464-8MF11)
Address designation Noise suppression
(for ET 100U only) 2 AI for f = nx
(50/60 Hz±1%)
Input range n = 1, 2, ...
(rated values) - common mode
- resistance rejection (Vpp=1 V) min. 86 dB
sensor (PT 100) 0 to 200 - series mode rejection min. 40 dB
(max. 400 ) (peak value of noise
- voltage sources ± 500 mV < rated value
of input range)
Number of inputs 1 or 2
(selectable) Basic error limits ± 0.15%
Galvanic isolation yes (inputs to Operating error limits ± 0.4%
grounding point; not (0 to 60 °C)
between inputs) (32 to 140 °F)
Input resistance 10 M Single errors
- linearity ± 0.05%
Connection method - tolerance ± 0.05%
of sensors two or four-wire - polarity reversal error ± 0.05%
connection
Temperature error
Digital representation - final value ± 0.01 %/K
of input signal 12 bits + sign - zero point ± 0.002 %/K
(2048 units
= rated value) Length of cable
- shielded max. 200 m (660 ft.)
representation (left-justified) Supply voltage L+ none
Auxiliary current
for PT 100 2.5 mA
Resistance sensor
Conversion principle voltage-time - tolerance ± 0.05%
conversion - temperature error ± 0.006%/K
(dual slope) - load dependency ± 0.02%/100
Integration time Insulation rating VDE 0160
(adjustable for opti- 20 ms at 50 Hz
mum noise suppression) 16.6 ms at 60 Hz Rated insulation voltage
(+9 V to ) 12 V AC
Encoding time per input - insulation group 1xB
max. 50 ms at 60 Hz
max. 66.6 ms at 50 Hz (inputs to + 9 V) 60 V AC
Permissible voltage - tested with 500 V AC
difference
- between inputs max. ±1V Current consumption
- between inputs and - from + 9 V (CPU) typ. 70 mA
Power loss of
Permissible the module typ. 0.9 W
input voltage
(destruction limit) max. 24 V DC Weight approx. 230 g (8 oz.)
4095 units)
- general indication
of wire break red LED
EWA 4NEB 812 6120-02 14-47

14-48
Module Spectrum
aaaaaa
aaaaaa
aaaaaa
2×PT100
aaaaaa aaaaaaaa
aaa a a a aaaa
2
+
aaaaaaaaaaaaaaaa
-
Ch.0
aaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
4
+
aaa
2
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
5
Analog Input Module 2 x PT 100/± 500 mV
-
3
aaaa aaaaaa
Ch.1
aaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
6
+
10
4
aaa aaaaaaaa aaaaaa
6
5
9
8
4
3
7
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaaaaaaaaaaaaaa
2×Pt100
aaaaaaaaaa aaaaaa
7
5
-
aaaaaa aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaa
operating
IC0
C
M-
M-
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaa
IC-
IC-
M+
M+
IC+
mode I +
6ES5 464-8MF21
broken wire
6
aaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaa aaaaaaaaaaaaaa
8
Ch.1
Ch.0
1
2
3
4
5
6
7
8
+
aaaaaa aaaaaaaaaa aaaaaaaaaa aaaaaa
ANALOG INPUT
aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaa aaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaa
9
aaaaaaaa aaaaaaaaaa aaa
-
wire
IC1
aaa aaaaaaaa
broken
aaaaaaaaaaaa
10
aaaaaaaaaa aaaaaaaa
aaaaaaaaaaaaaa
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
(6ES5 464-8MF21)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 2×PT 100/± 500 mV (continued) (6ES5 464-8MF21)
Address designation Noise suppression for f = nx
(for ET 100U only) 2 AI (50/60Hz ± 1%);
n = 1, 2, ...
Input range - common mode
(rated values) rejection
- resistance sensor (PT 100) 0 to 200 (V = 1 V) min. 86 dB
PP
(max. 400/ - series-mode rejection min. 40 dB
- voltage source ± 500 ) (peak value of noise
< rated value
Number of inputs 1 or 2 of input range)
(selectable)
Basic error limits ±0.15%
Galvanic isolation yes (inputs to
grounding point; not Operational error limits ±0.4 %
between inputs) (0 to 60 °C)
(32 to 140 °F)
Input resistance 10 M
Single errors
Connection method - linearity ±0.05%
of sensors two- or four-wire - tolerance ±0.05%
connection - polarity reversal error ±0.05%
of input signal 12 bits + sign Temperature error
(2048 units = rated - final value ±0.01%/K
value) - zero point ± 0.002%/K
Measured value two's complement Linearization exactness
representation (left-justified) in rated range ±0.5 °C
(0.9 °F)
Characteristic linearization
Conversion principle voltage-time con- of PT 100-charac-
version (dual slope) teristic curve DIN IEC 751
Integration time 20 ms at 50 Hz Length of cable
(adjustable for optimum 16.6 ms at 60 Hz - shielded max. 200 m (660 ft.)
noise suppression)
Supply voltage L + none
Encoding time Auxiliary current for PT 100 2.5 mA
per input
- for 2048 units max. 60 ms at 50 Hz Resistance-type sensor
max. 50 ms at 60 Hz - tolerance ± 0.05%
- for 4095 units max. 80 ms at 50 Hz - temperature error ±0.006%/K
max. 66.6 ms at 60 Hz - influence of load variation ±0.02%/100
Permissible voltage Insulation rating VDE 0160
difference
- between inputs max. ±1V Rated insulation voltage
- between inputs and (+9 V to ) 12 V AC
central ground point max. 75 V DC/60 V AC - insulation group 1xB
Permissible input
voltage Rated insulation voltage
(destruction limit) max. 24 V DC (inputs to + 9V) 60 V AC
Fault indication for - tested with 500 V AC
4095 units) Current consumption
- general indication Power loss of the
of wire break red LED module typ. 0.9 W
EWA 4NEB 812 6120-02 14-49

14-50
Module Spectrum
1
aaaaaaaa
1
a a a aaaa aaaaaaaaaaaaaaaaaaaa
2
+
aaaaaaaa
2
aaaaaa aaaaaaaaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa
3
90 k
-
3
aaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa
Ch.0
aaaaaa aaaaaaaa
aaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
4
4
+
aaaaaaaaaaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaaa aaaaaaaa aaa
10 -
9+
7+
5+
3+
8-
6-
4-
Analog Input Module 4×+0 to 10 V
5
aaaaaa aaaaaaaa aaaaaa aaaaaaaa aaaaaaaaaaaaaaaa aaaaaa
4 x 0 ...10 V
5
aaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaa
10 k
Ch.1
6ES5 466-8MC11
aaaaaa aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
6
aaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
6
6
- +
Ch.3
Ch.2
Ch.1
Ch.0
aaaaaaaa aaaaaa aaaaaa aaaaaa aaaaaa
ANALOG INPUT
aaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaa aaa aaa aaa aaa
-
aaaaaaaa aaaaaaaa
Ch.2
aaaaaa
aaa aaaaaaaaaaaaaaa
8
+
aaaaaaaaaaaaaa
9
aaaaaa
-
aaaaaaaa aaaaaaaa
Ch.3
aaaaaa
aaa aaaaaaaaaaaa
10
+9 V
Data
GND
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
(6ES5 466-8MC11)
EWA 4NEB 812 6120-02

S5-100U
Analog Input Module 4×+0 to 10 V (continued) (6ES5 466-8MC11)
Address designation Basic error limits ±0.4%
(for ET 100U only) 4 AI
Input ranges (0 to 60 °C)
(rated values) +0 to 10 V (32 to 140 °F) ±0.6%
Number of inputs 4 Single errors

- linearity ±0.1%
Galvanic isolation no - tolerance ±0.1%
Input resistance 100 k Temperature error
- final value ±0.01% K
Connection for the - zero point ±0.01% K
signal sensor 2-wire connection
Length of cable
Digital representation of - shielded max. 200 m (660 ft.)
the input signal 8 bits (256 units
= rated value) Supply voltage L+ none
Representation of the Current consumption
measured value binary * - from + 9 V (CPU) typ. 100 mA
Measuring principle successive Power loss
approximation of the module typ. 0.9 W
Conversion time 100 µs Weight approx. 200 g (7 oz.)

Encoding time
per input 5 ms
Permissible voltage
difference
- between inputs max. ±1 V
Permissible input voltage

(destruction limit) max. 60 V DC
- range exceeded no
- sensor wire break no
- general indication
of wire break no
Noise suppression
- common mode
interference (V =1 V) min. 86 dB
PP
* Bit
Input voltage 7 6 5 4 3 2 1 0
Units
in V 2 7 26 25 24 23 22 21 20
255 9.961 1 1 1 1 1 1 1 1
254 9.922 1 1 1 1 1 1 1 0
192 7.500 1 1 0 0 0 0 0 0
191 7.461 1 0 1 1 1 1 1 1
128 5.000 1 0 0 0 0 0 0 0
127 4.961 0 1 1 1 1 1 1 1
64 2.500 0 1 0 0 0 0 0 0
63 2.461 0 0 1 1 1 1 1 1
1 0.039 0 0 0 0 0 0 0 1
0 0.000 0 0 0 0 0 0 0 0
EWA 4NEB 812 6120-02 14-51

14.7.2 Analog Output Modules

Analog Output Module 2 x ± 10 V (6ES5 470-8MA12)
Address designation
(for ET 100U only) 2 AQ
Output range
(rated values) ±10 V
Number of outputs 2
Galvanic isolation yes (outputs to
grounding point and
between outputs)
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaa aaaaaa
aaaaaa aaaaaaaaaaaa aaaaaaaaaaa aaaaaaaaaaaa aaaaaaaaaa aaaaaaa aaa
L+ Input resistance 3.3 k

aaaa aaaaaaaaaaaa
aaaaaaaaaaaa
1
+
M Connection method two- or four-wire
2
QV 24 V connection
4
Digital representation 11 bits + sign
3 S+
of output signal (1024 units =
Ch.0 R rated value)
S-
5 Measured value two's complement
6 M
ANA
representation (left-justified)
QV Conversion time
8 (0 to 100%) max. 0.15 ms
7 S+
Permissible overload 25%
aaaaaa
Ch.1 R
S- Short-circuit protection yes
aaaaaa aaaaaa
9
10 M Short-circuit current ±30 mA
ANA
R 3k Permissible voltage
difference to ground
aaa
6 and between outputs max. 75 V DC/60 V AC

aaaaaaaaaa
ANALOG OUTPUT (0 to 60 °C)

2 x± 10 V (32 to 140 °F) ±0.6%
6ES5 470-8MA12
1 2 3 4 5 6 Single errors
- linearity ±0.2%
- polarity reversal error ±0.1%
- temperature error ±0.01%/K
Length of cable
aaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaaaa
+9 V - shielded max. 200 m (660 ft.)

GND
Data
Supply voltage L+
(peripheral)
- ripple V 3.6 V
PP
aaaaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
0V - permissible range 20 to 30 V
- 15V (ripple included)
+15V
(+9 V to ) 12 V AC
aaaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaa
1 3 5 7 9 (Output to L +, between
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaa
aaaa
2 4 6 8 10 outputs, output to + 9V) 60 V AC

S+ QV S- MA S+ QV S- MA
Current consumption
- from L + typ. 100 mA
aaaaaa
aaaaaa
aaaaaa
aaa
L+ M Power loss
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaa
Ch.0 Ch.1 of the module typ. 3.1 W

Legend:
QV: Analog output ”voltage”
14-52 EWA 4NEB 812 6120-02a

Analog Output Module 2×± 20 mA (6ES5 470-8MB12)
Address designation
Output range
(rated values) ±20 mA
Number of outputs 2

grounding point and
between outputs)
aaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaa aaaaaa aaaaaa
L+
Input resistance max. 300
aaaaaaaaa
aaaaaa aaaaaaaa aaa

aaaa aaaaaa
1 +
M Connection method two-wire connection
2
aaaaaa aaaa
QI 24 V
4 Digital representation
of output signal 11 bits + sign
Ch.0 R (1024 units =rated
value)
aaaaaa aaaaaa
aaaaaaaaaaaaaa
6
aaaaaaaaaaaa
aaaaaa
MANA representation (left-justified)

QI Conversion time
8
(0 to 100%) max. 0.15 ms
aaaaaa
aaaaaa
aaaaa
aaaa
Ch.1 R Permissible overload 25%

Short-circuit protection yes
aaaaaa aaaaaa
aaaaaaaaaaaaa
aaaaaaaaaaaa
10 M
ANA Short-circuit current ± 30 mA
R 300 Permissible voltage
difference to central
aaa
6 ground point and

between outputs max. 75 V DC/60 V AC
aaaaaaaaaa
ANALOG OUTPUT Operating error limits

2 x± 20 mA
6ES5 470-8MB12
(0 to 60 °C)
(32 to 140 °F) ±0.6%
1 2 3 4 5 6
Single errors
- linearity ±0.2%
- polarity reversal error ±0.1%
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
+9 V
GND Length of cable
Data - shielded max. 200 m (660 ft.)
Supply voltage L+
- ripple V 3.6 V
aaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaa
PP
- permissible range
aaaaaaaaaaaaaa
0V
- 15V (ripple included) 20 to 30 V
+15V
(+9 V to ) 12 V AC
aaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaa
aaaaaaaa aaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaa
aaaaaaaaaaaaaaa
aaaaaaaa aaaaaaaa
1 3 5 7 9 (output to L+, between

aaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaaaa
aaaaaaaaaaaa
aaaaaaaaaa
2 4 6 8 10 outputs, output to + 9 V) 60 V AC
+QI MANA +QI MANA
Current consumption
- from L + typ. 130 mA
aaaaaa
aaaaaa
Power loss of the

aaaaaa
aaa
L+ M
module typ. 3.8 W
aaaaaa
aaaaaa
aaaaaa
aaaaaa
aaa
Ch.0 Ch.1
Legend:
QI: Analog output ”current”
EWA 4NEB 812 6120-02a 14-53

Analog Output Module 2 x 4 to 20 mA (6ES5 470-8MC12)
Address designation
Output range
(rated value) 4 to 20 mA
Number of outputs 2
grounding point and
between outputs)
aaaaaaaaaaaaaaaaaa
aaaaaaaa aaaaaa
L+
aaaaaaaaaa aaaa
aaaaaa aaaaaa
aaa aaaaaa
1 + Load resistance max. 300

M
2
aaaaaa
QI 24 V Connection method two-wire connection

4
aaaaaa
aaaaaa
aaaaaa
aaaaaa
Ch.0 R of output signal 11 bits + sign

(1024 units = rated
value)
aaaaaa aaaaaa
aaaaaa aaaaaaaa aaaaaaa
6
aaaaaa aa aaaa
aaaa
MANA Measured value two's complement

QI representation (left-justified)
8
Conversion time
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Ch.1 R (0 to 100%) max. 0.15 ms

Permissible overload 25%
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10 M
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ANA Short-circuit protection yes

R 300 Short-circuit current ±30 mA
aaa
6 Permissible voltage
ground point and
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ANALOG OUTPUT
2 x 4 ... 20 mA Basic error limits ±0.2%
6ES5 470-8MC12
Operating error limits
1 2 3 4 5 6 (0 to 60 °C)
(32 to 140 °F) ±0.06%
Single errors
- linearity ±0.2%
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+9 V - temperature error ±0.01%/K

GND
Data
Length of cable
- shielded max. 200 m (660 ft.)
Supply voltage L+
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0V
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- 15V
- ripple VPP 3.6 V
+15V - permissible range 20 to 30 V
(ripple included)
(+9 V to ) 12 V AC
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1 3 5 7 9
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2 4 6 8 10 Rated insulation voltage

a a
(outputs to L+,
a
+QI MANA +QI MANA

between outputs,
output to + 9 V ) 60 V AC
Current consumption
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L+ M - from + 9 V (CPU) typ. 170 mA

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Ch.0 Ch.1 - from L+ typ. 130 mA

Power loss of
the module typ. 3.8 W
Legend:
QI: Analog output ”current” Weight approx. 290 g (10 oz.)
14-54 EWA 4NEB 812 6120-02a

Analog Output Module 2 x 1 to 5 V (6ES5 470-8MD12)
Address designation
Output range
(rated values) 1 to 5 V
Number of outputs 2
grounding point and
between outputs)
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L+ Input resistance min. 3.3 k

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1
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+ Connection method two- or four-wire

M connection
2
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QV 24 V
4 Digital representation
3 S+ of output signal 11 bits + sign
Ch.0 R (1024 units=rated
S-
value)
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5
6
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MANA representation (left-justified)

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QV Conversion time
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8
(0 to 100%) max. 0.15 ms
7 S+
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Ch.1 R Permissible overload 25%

S- Short-circuit protection yes
9
10 Short-circuit current ±30 mA
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MANA
Permissible voltage
R 3k
ground point and
6
Operating error limits
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ANALOG OUTPUT (0 to 60 °C)

2 x 1 ... 5 V
6ES5 470-8MD12 (32 to 140 °F) ±0.06%
1 2 3 4 5 6 Single errors
- linearity ±0.2%
Length of cable
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+9 V - shielded max. 200 m (660 ft.)

GND
Data Supply voltage L+
- ripple VPP 3.6 V
- permissible range 20 to 30 V
(ripple included)
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0V
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- 15V Insulation rating VDE 0160

+15V Rated insulation voltage
(+9 V to ) 12 V AC
(outputs to L+,
between outputs,
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1 3 5 7 9 output to +9 V) 60 V AC
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2 4 6 8 10 - insulation group 1xB

a a

a
S+ QV S- MA S+ QV S- MA
Current consumption
Power loss of
the module typ. 3.1 W
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aaa
L+ M
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aaa
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Ch.0 Ch.1 Weight approx. 290 g (10 oz.)
EWA 4NEB 812 6120-02a 14-55

15 Function Modules
15.1 Comparator Module 2×1 to 20 mA/0.5 to 10 V ............... 15 - 1
15.2 Timer Module 2×0.3 to 300 s ........................... 15 - 4
15.3 Simulator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 7
15.4 Diagnostic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 9
15.5 Counter Module 2×0 to 500 Hz ......................... 15 - 12
15.6 Counter Module 25/500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 17

15.6.1 Installation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 20
15.6.2 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 25
15.6.3 Functional Description of the Counter Mode . . . . . . . . . . . . . . . . . 15 - 27
15.6.4 Functional Description of the Position Decoder . . . . . . . . . . . . . . . 15 - 29
15.6.5 Entering New Setpoints for the Counter and
Position Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 38
15.6.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 39
15.7 Closed-Loop Control Module IP 262 ...................... 15 - 41
15.8 Positioning Module IP 266 ............................. 15 - 45
15.9 Stepper Motor Control Module IP 267 ..................... 15 - 49
15.10 Communications Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 52

15.10.1 Printer Communications Module CP 521 . . . . . . . . . . . . . . . . . . . 15 - 52
15.10.2 Communications Module CP 521 BASIC . . . . . . . . . . . . . . . . . . . 15 - 55
EWA 4NEB 812 6120-02

Figures
15-1 Scanning the Comparator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 2

15-2 Scanning the Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 5
15-3 Scanning the Simulator Module as a Digital Input . . . . . . . . . . . . . . . . . . . 15 - 8
15-4 Setting the Input Voltage Range on the Counter Module (500 Hz) . . . . . . . 15 - 14
15-5 Scanning the Counter Module (500 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 15
15-6 Timing Diagram: Setting and Resetting an Output of the
Counter Module (500 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 15
15-7 Switch Positions on the Operating Mode Switch . . . . . . . . . . . . . . . . . . . . 15 - 19
15-8 Pin Assignment of the 15-Pin Sub-D Female Connector . . . . . . . . . . . . . . 15 - 20
15-9 Connecting a Counting Pulse Sensor for 5-V Differential Signal to RS 422 . 15 - 21
15-10 Connecting a Counting Pulse Sensor for 24 V DC . . . . . . . . . . . . . . . . . . 15 - 21
15-11 Connecting a 5-V Position Sensor to RS 422 . . . . . . . . . . . . . . . . . . . . . . 15 - 22
15-12 Connecting a 24-V DC Position Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 22
15-13 Signal Sequence for Up-Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 23
15-14 Assignment Diagram for the Terminal Block . . . . . . . . . . . . . . . . . . . . . . . 15 - 24
15-15 Diagnostic Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 26
15-16 Switching the Outputs Dependent on the Status of the Counter and
the Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 28
15-17 Position of the Reference Point (SYNC Bit = 1) within the
Reference Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 32
15-18 Position of the Reference Point (SYNC Bit = 1) after the Reference
Signal ................................................ 15 - 32
15-19 Position of the Reference Point (SYNC BIT = 1) during a Reversal of
Direction before Reaching the Reference Pulse in a Positive Direction . . . . 15 - 33
15-20 Schematic of a Reference Point Approach Operation . . . . . . . . . . . . . . . . 15 - 33
15-21 Enabling the Outputs - Reaching the Setpoints - Resetting the Outputs ... 15 - 34
15-22 Approaching a Setpoint in Up-Count Direction . . . . . . . . . . . . . . . . . . . . . 15 - 35
15-23 Approaching a Setpoint in Down-Count Direction . . . . . . . . . . . . . . . . . . . 15 - 36
15-24 Approaching a Setpoint in Up-Count Direction and Consecutive
Reversal of Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 36
15-25 Requirement for New Setpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 38
15-26 Units of Measurement that IP 266 Can Process for Circular Axis
and Linear Axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 46
15-27 Course of a Following Error during a Positioning Operation . . . . . . . . . . . . 15 - 47
15-28 Velocity Profile of the IP 267 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 50
Tables
15-1 Sending Data from the Programmable Controller to the Counter Module . . . 15 - 25
15-2 Sending Data from the Counter Module to the Programmable Controller .. 15 - 25
15-3 Pulse Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 30
15-4 Example for a Traversing Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 31
15-5 Reaction of the Counter Module during Transfer of the Setpoints . . . . . . . . 15 - 38
15-6 Slot Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 39
15-7 Meaning of the Address Bytes of a Slot Address (Example: Slot 1) . . . . . . 15 - 39
15-8 Designation of the Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - 48
EWA 4NEB 812 6120-02

S5-100U Function Modules
15 Function Modules
15.1 Comparator Module 2×1 to 20 mA/0.5 to 10 V (6ES5 461-8MA11)
Address designation
Channels 2
Current or voltage switch-selectable

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measurement
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3
0
Switch position “0” no measuring
4
Display green LED for actual
value setpoint
Setpoint adjustment with potentiometer
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U
O Setting error ±10%
I
Reproducibility ±2%
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9
1
Hysteresis 10%
10
“V” measuring range 0.5 to 10 V DC
Input resistance 47 k
Inherent delay typ. 5 ms
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U
O
I Input voltage max. 100 V DC
( 0.5 s)
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6 “I” measuring range 0.5 to 20 mA

Input resistance 500
Overload capability 100%

COMPARATOR
0.5 to 10V/1 to 20mA Insulation rating VDE 0160
6ES5 461-8MA11
1 2 3 4 5 6
Rated insulation
voltage
(+9 V to measuring
circuit and between
measuring circuits) 30 V AC
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+9 V - insulation 2×B
GND
Data - tested with 500 V AC
(+9 V to ) 12 V AC
Length of cable
- shielded 200 m (660 ft.)
- unshielded 100 m (330 ft.)
Current consumption
Power losses
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1 3 5 7 9
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2 4 6 8 10
V I
EWA 4NEB 812 6120-02 15-1

Function Modules S5-100U
Function
The module has two isolated comparators for voltage or current measurement (selector switch with
positions U/0/I). When the preset value is reached, the LED of the respective channel lights up and
sends a “1” signal to the programmable controller.
The module must be removed or the measuring circuit disconnected before you select the function.
In switch position “0”, the comparator is switched off; if scanned, a “0” signal results.
The response threshold of the comparator is set by a selector on the front panel. The selector has
scale divisions to simplify adjustment.
Installation
The comparator module is mounted on a bus unit like any other input or output module
(see chapter 3).
Wiring
See schematic diagram. Unused inputs can be left open.
Addressing
The comparator module is addressed like a 2-channel digital input module (channel “0” or “1”).
Scan A I x.0 Channel “0”

(examples) O I x.1 Channel “1”
Channel number
Slot address
Figure 15-1. Scanning the Comparator Module
15-2 EWA 4NEB 812 6120-02

S5-100U
=
A
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EWA 4NEB 812 6120-02

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Typical Application
Q
STL
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5.1
4.1
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1
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4
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5
6
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7
8
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Terminal Connections
+
9
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10
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-
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Explanation
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becomes "1"; this sets output 5.1 to "1".

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Schmitt trigger 1 detects that the current has exceeded the preset value, output 5.1 is to be set.
A comparator module is mounted at slot 4. The current source is connected to channel 1. If the
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As soon as the limit is reached or exceeded, input 4.1

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Function Modules
15-3
15.2 Timer Module 2×0.3 to 300 s (6ES5 380-8MA11)
Address designation
(for ET 100U only) 4 DX
Number of timers 2
Time setting 0.3 to 3 s
Range extension factor ×10, ×100
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0 Function indication green LED

Setting error ±10%
Reproducibility ±3%
Temperature influence +1%/10 °C (50 °F)
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x 0.3s of set time

x 3s
x 30s
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1 Rated insulation voltage

(+ 9 V to ) 12 V AC
Current consumption
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x 0.3s
x 3s Weight approx. 200 g (7 oz.)
x 30s
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6
TIMER
2 x 0.3-300s
6ES5 380-8MA11
1 2 3 4 5 6
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+9 V
GND
Data
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0.3 s 300 s 0.3 s 300 s

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X.0 X.1
15-4 EWA 4NEB 812 6120-02

Function
The module contains two pulse timers. While a timer runs, the LED of the respective channel is lit
and a “1” is reported to the CPU.
The pulse duration is preselected with the time range selector “x 0.3 s / x 3 s / x 30 s” in a definite
range and then set to the exact value by means of a potentiometer on the front panel. This selector
has scale divisions to simplify setting.
(time value=time range x scale value)
Example: Time range: x3s

Scale value: 7
Set time: 7 x 3 s=21 s
Installation
The counter is inserted into a bus unit like any other input or output module (see chapter 3).
Wiring
No wiring is required.
Addressing
A timer module is addressed like a two-channel digital module (channel “0” or “1”).
The timer module is addressed like a digital output module for starting, resetting, or interrupting the
pulse. The signal status is scanned like a digital input module.
Starting the pulse S Q x.0 Channel “0”

S Q x.1 Channel “1”
Interrupt/ R Q x.0
Reset R Q x.1
Scan A I x.0
“1” = timer running A I x.1
Channel number
Slot address
Figure 15-2. Scanning the Timer Module
EWA 4NEB 812 6120-02 15-5

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15-6
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=
A
R
A
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I
AN I
A I
A F
AN I
I
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Q
Q
= F
S Q
STL
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5.0
0.0
4.0
0.0
5.0
4.0
5.0
0.0
65.0
65.0
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Function Modules
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to “1”.
module.
Typical Application as “On-Delay Timer”

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The timer is started if I 0.0 is “1”.

A lamp lights up (output 4.0) when the timer has run down.
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If I 0.0 is “0”, the lamp is switched off.

making any program modifications.

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Terminal Connections
modified using a timer module without

Explanation
timer had started until one program scan later.

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No process peripherals are connected to this
Unlike the internal timers, times can be set or

of the time-range selector and the potentiometer. The timer is started when input 0.0 is “1”.
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If flag 65.0 is “1” and the timer has run down (AN I 5.0), output 4.0 is set
If the “Timer started” message has been sent to the CPU, the flag is set.
enabled since the CPU would not receive the acknowledgement that the
The timer must not be scanned in the program scan cycle in which it was
A timer module is mounted at slot 5. A time of 270 s is set on channel “0” of this module by means
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EWA 4NEB 812 6120-02

S5-100U
aaaaaaaa
15.3. Simulator Module (6ES5 788-8MA11)
Address designation
(for ET 100U only)
- input simulator 8DI
- output simulator 8DQ
Function selection
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IN
- simulation of 8 input selected by switch
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OUT signals on rear of module

- display of 8 output
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.0 signals
.1 Function indication yellow LED
“0”/“1” input signals switch-selectable

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.2
.3
Rated insulation
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.4 voltage
(+9 V to ) 12 V AC
.5 - insulation group 1×B
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.6 Signal status display for

input/output green LEDs
.7
Current consumption
- from +9 V (CPU) 30 mA
Power loss of the
module typ. 0.3 W
Weight 190 g (6.7 oz.)

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SIMULATOR
INPUT/OUTPUT
6ES5 788-8MA11
1 2 3 4 5 6
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+9 V
GND
Data
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OUT IN
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EWA 4NEB 812 6120-02 15-7

Function
Simulator modules are 8-channel modules that can simulate digital input signals and display output
signals.
The type of module to be simulated (input or output) is selected by means of a switch on the rear of
the module and indicated by two LEDs on the front panel.
The module cannot simulate interrupt inputs.
Installation
The simulator module is inserted into a bus unit like any other input or output module (see
section 3.2.1). The module does not have a coding key and can therefore replace any digital
module. The coding element on the bus unit does not have to be readjusted.
Wiring
There is no electrical connection between the module and the terminal block. It can therefore be
inserted into slots that have already been wired and connected to the power supply.
Addressing
A simulator module is addressed like an 8-channel digital module (channels 0 to 7).
Scan A I 0.0 Channel “0”

(examples) O Q 1.1 Channel “1”
Channel number
Slot address
Figure 15-3. Scanning the Simulator Module as a Digital Input
Typical Application
The CPU is in the RUN mode, the green LED is lit but the programmable controller is mal-
functioning. You have also discovered that the fault must be in a particular I/O module. If the
module has no fault indicator, check to see if:
• The power supply is connected.
• The bus connections and interface modules are plugged in correctly.
Then, try to access the module via the process image (STATUS or STATUS VAR). If this
procedure is not successful, replace the module with the simulator module. Perform a second
check with the STATUS or STATUS VAR function. If the simulator performs, the input/output
module you replaced is defective.
15-8 EWA 4NEB 812 6120-02

15.4
1
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VRef
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3
1
- +
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4
Function Modules
3
EWA 4NEB 812 6120-02

5
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4
6
DISPLAY
5
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6ES5 330-8MA11
+1024
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7
BUS SIGNAL
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DATA
U1 8V
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8
IDENT
U1>8V
LATCH
CLEAR
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CLOCK
DATA-N
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9
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Diagnostic Module
10
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+9 V
GND
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Data/Bus signals
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Weight
the module
- voltage ok
(+9 V to )
- tested with
Power loss of
control signals
- undervoltage
Voltage monitor
Insulation rating
- insulation group
- from+9 V (CPU)
Current consumption
Signal status display for
typ.
1×B
0.3 W
25 mA
red LED
12 V AC
500 V AC
VDE 0160
green LED
yellow LEDs
approx. 175 g (6.1 oz.)

(6ES5 330-8MA11)
S5-100U
15-9
Function
The diagnostic module is used for monitoring the S5-100U I/O bus. LEDs on the front panel display
the signal states of the control lines and the supply voltage for the I/O bus.
• IDENT
The programmable controller executes an IDENT run after each change from STOP to RUN. It
executes an IDENT run after any changes in the configuration in order to determine the current
configuration. The IDENT LED lights up briefly. If the LED lights up in the RUN mode, this
indicates that a faulty I/O module has been plugged in.
• CLEAR
The CLEAR signal line is “1” only in the STOP mode in normal operation.
The outputs of the output modules are disabled.
If CLEAR is “1” in the RUN mode, the control line itself may be defective (no contact).
• LATCH/CLOCK
These two control lines control data interchange between the CPU, the I/O bus, and the I/O
modules.
During normal operation, both LEDs must flash (programmable controller in RUN mode).
The flashing frequency provides information on the speed of the serial bus.
If both LEDs show a steady light in the RUN mode, the bus unit that the diagnostic module is
plugged into is defective.
• DATA/DATA-N
The alternate lighting up of the DATA and DATA-N LEDs indicates data flow on the I/O bus.
If these two LEDs show a steady light (as in the case of the LATCH and CLOCK LEDs), this
indicates that the bus unit that the diagnostic module is plugged into is defective.
• U1 8V
If the supply voltage of a slot remains at a value U1 8V, proper functioning of the I/O modules
is no longer guaranteed. The low supply voltage can be explained by an excessively high bus
load (> 1 A).
If this LED flickers, noise pulses are superimposed on the supply voltage U1 (e.g., by the
coupling of noise pulses).
The LED lights up briefly if the programmable controller is switched on or off.
• U1 > 8V
The supply voltage of the I/O bus is functioning correctly.
15-10 EWA 4NEB 812 6120-02

Installation
The diagnostic module is plugged into a bus unit like any other input or output module (see
section 3.2.1). The module has no mechanical coding. The coding element on the bus unit does
not have to be reset.
Note
The module can be plugged in and removed regardless of the operating status of the
programmable controller.
Wiring
No wiring is required. Existing wiring does not have to be removed.
Addressing
There is no addressing since the module cannot be addressed by the programmable controller.
EWA 4NEB 812 6120-02 15-11

15.5
15-12
S5-100U
1
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Ch.1
Ch.0
5V
2
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24 V
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1 2
3
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-0
-0
4
4
500 Hz
Counter Module 2×0 to 500 Hz
5
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5
COUNTER
6
6ES5 385-8MA11
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6
5V/24 V
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7
6
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Q1
Q0
8
Ch.1
Ch.0
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9
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10
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+9 V
Data
GND
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(6ES5 385-8MA11)
Function Modules
EWA 4NEB 812 6120-02

Address designation Total permissible current
(for ET 100U only) 4DX of outputs 1A
Number of Inputs 2 Driving a digital input possible
Galvanic isolation yes Paralleling of outputs possible
- max. current 0.5 A
Input voltage
- rated value 5 V/24 V DC Permissible ambient
- for “0” signal 0 to 0.8/-33 to 5 V temperature for the unit
- for “1” signal 3 to 5 V/13 to 33 V - horizontal arrangement 0 to 60 °C (32 to 140 °F)
- vertical arrangement 0 to 40 °C (32 to 104 °F)
Input current for
“1” signal typ. 1.5/8.5 mA Length of cable
Inherent delay typ. 180 µs
Input frequency max. 500 Hz
Connection of 2-wire BERO (inputs and outputs to
proximity switches each other and to ;
(24 V DC) possible input to +9 V) 60 V AC
- quiescent current 1.5 mA - insulation group 1×B
Length of cable
- unshielded max. 50 m (165 ft.) Current consumption
- from+9 V (CPU) typ. 20 mA
Outputs 2
Power loss of the
Galvanic isolation yes module typ. 2.5 W
Supply voltage L+ Weight approx. 200 g (7 oz.)
(for load)
- permissible range 20 to 30 V
(including ripple)
Output current
for “1” signal
- rated value 0.5 A
- permissible range 0.5 to 500 mA
Residual current
at “0” signal max. 1 mA
Output voltage
- for “0” signal max. 3 V
- for “1” signal max. L+-2.5 V
Short-circuit protection electronic
Fault indication (red LED) short-circuit

interruption (internal)
limited to L+-47 V
Switching frequency
EWA 4NEB 812 6120-02 15-13

Function
The module consists of two independent down counters with isolated inputs and outputs. It counts
input signals up to a frequency of 500 Hz from a set value down to the value 0. When 0 is reached,
the 24-V DC output of the module is energized.
At the same time, a green LED on the module lights up and the input signal (I x.0 or I x.1) is set
to “1”.
The setpoint (0 to 999) can be entered via the three-digit thumbwheel switches on the front panel of
the module.
The input voltage ranges can be set for 5 V DC or 24 V DC using rocker switches on the front
panel.
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Channel 0 Channel 0
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Channel 1 Channel 1
5 V DC (TTL) 24 V DC
Figure 15-4. Setting the Input Voltage Range on the Counter Module (500 Hz)
Installation
The counter module is plugged into a bus unit like any other module (see section 3.2.1).
Wiring
See schematic diagram for the counter module.
15-14 EWA 4NEB 812 6120-02

Addressing
A counter module can be addressed like a two-channel digital module (channel “0” or “1”). For
enabling and resetting the counter, you address the module like a digital output module. The
counter reading is scanned in the same way as a digital input module.
Counter enable S Q x.0 Channel “0”

(Set to start value) S Q x.1 Channel “1”
Counter reset R Q x.0

R Q x.1
Scan A I x.0
“1” = Counter at zero A I x.1
Channel number
Slot address
Figure 15-5. Scanning the Counter Module (500 Hz)
Timing Diagram
S Q x.0 R Q x.0
1 Enable
0
1 Counting
0
pulses
6
1 Output Q
0
Time
Figure 15-6. Timing Diagram: Setting and Resetting an Output of the

Counter Module (500 Hz)
EWA 4NEB 812 6120-02 15-15

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15-16
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S5-100U
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released.
=
A
S
Q
I
Q
Typical Application
STL
4.0
2.0
2.0
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1
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2
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3
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4
5
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6
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7
Connection Diagram
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5 and 6 is possible.
8
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9
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10
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Explanation
the counter status is “0”, input I 2.0 is set to “1”.

During the counting operation, input I 2.0 is “0”. When

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Output Q 4.0 is then also set. Direct output at terminals

A counter module is plugged into slot 2. A value of 100 is set on channel “0” of this module using
the three-digit thumbwheel switches. The incoming pulses are counted once the counter has been
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enabled by the control program. As soon as 100 pulses have been counted, a signal (output 4.0) is
Function Modules
EWA 4NEB 812 6120-02

15.6
Function Modules
EWA 4NEB 812 6120-02

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1
+5 V
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24 V
2
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1 2
8
5
4
3
1
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3
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4
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Counter Module 25/500 kHz
4
F
SV
PD
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5
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5
6ES5 385-8MB11
6
HIGH SPEED
6
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COUNTER 25/500 kHz

6
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7
4×
2×
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24 V
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8
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9
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10
+9 V
Data
GND
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(6ES5 385-8MB11)
15-17
S5-100U
Power supply for sensor 24 V from L+
Address designation (PTC thermistor)
(for ET 100 only) 2AX
Output current max. 300 mA, short-
Operating mode circuit proof
(switch-selectable)
- position decoder PD Digital Inputs reference and
- counter C enabling
Sensor inputs 1 sensor 5 V Rated input voltage 24 V DC

(differential input) or
1 sensor 24 V DC Input voltage
- “0” signal - 33 to +5 V DC
Digital inputs 2; reference and - “1” signal +13 to 33 V DC
enabling
Rated input current for
Digital outputs 2; setpoints reached 1 “1” signal and at 24 V typ. 8.5 mA
and 2
Input frequency max. 100 Hz
Inherent delay typ. 3 ms (1.4 to 5 ms)
Counting range
Operating mode Cable length (unshielded) max. 100 m (330 ft.)
- position decoder two's complement
(KF) - 32768 to Digital Outputs setpoints 1 and 2
+32767
- counter unipolar representation Output current 5 mA to 0.5 A
(KH) 0 to 65535 (resistive, inductive load)
Counting mode Residual current for
- position decoder up/down “0” signal max. 0.5 mA
- counter up
Switching current
Setpoint input via program for lamps 0.22 A (5 W)
5-V Sensor Input 15-pin Cannon sub- Limitation of inductive to -15 V
miniature D connector interrupting voltage
Input signals differential signals Output voltage
to RS 422 - “1” signal min. L+ - 2.2 V
- position decoder A A-N, B B-N, R R-N - “0” signal max. 3V
- counter A A-N
Cable length (unshielded) max. 100 m (330 ft.)
Counting frequency max. 500 kHz
Cable length (shielded) max. 50 m (165 ft.) (cable impedance up to 15 ) electronic
Power supply for decoder 5 V from L+via voltage Short-circuit indication red LED
transformer (short-circuit to M)
Output current max. 300 mA, short-circuit- Supply voltage L+

proof - rated value 24 V DC
- ripple Vpp max. 3.6 V
24-V Sensor Input 15-pin Cannon sub- - permissible range 20 to 30 V DC
miniature D connector (including ripple)
Rated input voltage 24 V DC Fuse (internal) T 5 A (slow blow)

Input signals Current consumption
- position decoder A, B, R - from L+ 30 mA
- counter A without sensor supply
without load
Input voltage - internal (+9 V) 70 mA
- “0” signal - 33 to 5 V DC
- “1” signal +13 to 33 V DC Power consumption
of the module typ. 1.9 W+total output
Rated input current current (IA)×1.1 V
for “1” signal typ. 8.5 mA
Counting frequency max. 25 kHz
Cable length (shielded) max. 100 m (330 ft.)
15-18 EWA 4NEB 812 6120-02

•
•
•
•
•
•
•
Function
requirements:
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SV
Function Modules
PD
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EWA 4NEB 812 6120-02

The function mode
The updated count
The diagnostic byte
The position resolution

24-V signals (up to 25 kHz)
4×
2×
24 V
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The input voltage range of the sensor

5-V error voltages according to RS 422 (up to 500 kHz)
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You can preselect the following items on the operating mode switch:
You can also read the following values by using the STEP 5 program:
(Q 0 or Q 1). The status of the outputs is displayed in the diagnostic byte.

As additional inputs, the module has an enable input and a reference input.
not allowed
Counter (C)
Pos. resolution
Pos. resolution
Pos. resolution
Figure 15-7. Switch Positions on the Operating Mode Switch

Sensor connection
Sensor connection
Position decoding (PD)

single
5V
double
24 V
quadruple
By using the STEP 5 program, you can assign two setpoints via the I/O bus. Once the counter
status reaches one of these values, the respective output completes the circuit at terminal block
The counting pulses are supplied by a sensor that you can connect to the 15-pin subminiature D
female connector of the module. You can choose from two types of sensors that fulfill the following
The counter module can be used as an up-counter or as an up/down counter for a position decoder.
15-19
S5-100U
15.6.1 Installation Guidelines
Installing and Removing the Module

Plug the counter module into a bus unit like other I/Os.
The counter module can only be plugged into slots 0 through 7.
Set the coding key to number 6 on the bus unit.
Installing or Removing the Sensor

Disconnect the 24-V DC power supply (terminals 1 and 2 of the terminal block) before connecting or
disconnecting the sensor cables.
! Warning
Connecting or disconnecting the 5-V sensor cable while the module is energized can
cause damage to the sensor.
Connection of Pulse and Position Sensors

Connect pulse and position sensors on the front plate by means of a 15-pin sub-D female
connector. The correct cable connectors are listed in Appendix D. The module can supply the
sensors (5 V DC or 24 V DC).
Basically, all sensors can be connected if they fulfill the requirements of the system signals and
supply voltage. Sensors with OPEN-COLLECTOR outputs cannot be connected to the module.
The shield connection of the sensors must be connected to the metallic front connector cover.
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Pin Assignment
1 5 V Supply voltage
2 5 V Sensor line
3
4 Ground
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1
9
2 5
10
3 6 Rectangular-wave signal A-N (5 V)
11
4 7 Rectangular-wave signal A (5 V)
12
5 8 Supply voltage (24 V)
13
6 9 Rectangular-wave signal B (5 V)
14
7 10 Rectangular-wave signal B-N (5 V)
15
8 11 Reference pulse R (5 V)
12 Reference pulse R-N (5 V)
13 Rectangular-wave signal A (24 V)
14 Rectangular-wave signal B (24 V)
15 Reference pulse R (24 V)
Figure 15-8. Pin Assignment of the 15-Pin Sub-D Female Connector
15-20 EWA 4NEB 812 6120-02

• Connecting Counting Pulse Sensors for 5-V Differential Signal to RS 422
Module
Electronic light 1 5V
Sensor line 2 5V L+
3
4 0V 24 V M
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5V 5V 0V 5
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6 A-N
5-V Va 7 A
Pulse 8
sensor 9
10
11
12
13
16
15
Shield
Shell of subminiature D connector
Figure 15-9. Connecting a Counting Pulse Sensor for 5-V Differential Signal to RS 422
• Connecting a Counting Pulse Sensor for 24 V DC
Module
1
2
3
4 M
5
0V
6
7
0V DC 8 L+
9 DC 24V
10
24-V
11
Pulse
12
sensor
13 A
16
15
Shield
Figure 15-10. Connecting a Counting Pulse Sensor for 24 V DC
EWA 4NEB 812 6120-02 15-21

• Connecting a 5-V Position Sensor to RS 422
Module
Electronic light 1 5V
Sensor line 2 5V L+
3
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4 0V 24 V M
5V 5V 0V
5
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6 A-N
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5-V Va1 7 A
Position 8
sensor 9 B
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Va2 10 B-N
11 R
Va0 12 R-N
13
16
15
Shield
Figure 15-11. Connecting a 5-V Position Sensor to RS 422
• Connecting a 24-V DC Position Sensor
Module
1
2
3
4 M
Electronic light source 5
0V
6
7
0V 8 L+
24 V 9 24 V
10
24-V 11
Position 12
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sensor Va1 13 A
Va2 16 B
Va0 15 R
Shield Shell of subminiature D connector
Figure 15-12. Connecting a 24 V DC Position Sensor
15-22 EWA 4NEB 812 6120-02

Sensor Requirements
The following requirements must be satisfied by the sensor signals to the module inputs:
• Signal sequence for up-counting
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Sensor t1
signals: Va1
(A, A-N/A)
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t t
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t t
Va2
(B, B-N/B)
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t2
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Va0
(R, R-N/R)
Figure 15-13. Signal Sequence for Up-Counting
• Pulse time of the sensors
5-V Sensors 24-V Sensors Pulses
t 500 ns 10 µs Va1 = Position decoder count pulses (A)

t1 2 µs 40 µs Va2 = Position decoder count pulses (B)
t2 500 ns 10 µs Va0 = Position decoder ref. pulse (R)
• Minimum edge steepness

5 V - differential signals according to RS 422A (A, A-N, B, B-N, R, R-N): 5 V/µs
24 V - count pulses and reference pulse (A, B, R): 0.3 V/µs
24 V - enable and reference signal: 0.3 mV/µs
EWA 4NEB 812 6120-02 15-23

Terminal Block
Proximity switches can be connected (contacts, two-wire BERO proximity limit switches) to the
inputs on the terminal block.
Terminal Terminal Assignment

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1 24-V DC supply for the module

2 Ground
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1 3 5 7 9 1 3 5 7 9
3 24-V DC supply for enable signal
4 DI enable signal
2 4 6 8 10 2 4 6 8 10
5 DQ 24 V/0.5 A setpoint (Q0)
6 Ground
7 24-V DC supply for reference signal
8 DI reference signal
9 DQ 24-V/0.5 A setpoint 2 (Q1)
10 Ground
Figure 15-14. Assignment Diagram for the Terminal Block
• Assignment of Inputs on the Terminal Block

Two-wire BERO proximity limit switches can be connected to the reference input. The enable
input can also be driven by a 24-V DC digital output module.
• Outputs on the Terminal Block

There are two short-circuit protected 24-V DC digital outputs on the terminal block.
• Short-Circuit Indication
A shorted output is indicated by the red LED on the front panel.
15-24 EWA 4NEB 812 6120-02

15.6.2 Data Transfer
The data is transmitted via the I/O bus. Four bytes are used.
Examples of data transfer are shown in section 15.6.6.
Transfer from the Programmable Controller to the Counter Module (PIQ)

The control program transfers two setpoints to the counter module by means of transfer operations.
Table 15-1. Sending Data from the Programmable Controller to the Counter Module
Byte 0 Byte 1 Byte 2 Byte 3
Setpoint 1 Setpoint 2
Transfer from the Counter Module (PII) to the Programmable Controller

The counter module transfers the diagnostic byte and the current counter status. In the control
program, this data can be read in by means of load operations and then evaluated.
Table 15-2. Sending Data from the Counter Module to the Programmable Controller
Byte 0 Byte 1 Byte 2 Byte 3
Diagnostic Actual value

Irrelevant
byte High byte Low byte
EWA 4NEB 812 6120-02 15-25

• Diagnostic Byte (Byte 1)

The diagnostic byte is byte 1 of the first input word. Byte 0 has no significance.
The diagnostic byte provides information on the following items:
- Preset position resolution
- Preset mode
- Status of setpoints
- Signal status of the sync bit for position decoding
Bit No.: 7 6 5 4 3 2 1 0
X R R P/C OV S2 S1 Sy
Position resolution
single 0 1
double 1 0
quadruple 1 1
not possible 0 0
Mode
Position decoding 1
Counter 0
Counter overflow 1
No counter overflow 0
Setpoint 2 reached 1
Setpoint 2 not reached 0
Setpoint 1 reached 1
Setpoint 1 not reached 0
Sync bit set 1

Sync bit not set * 0
X = irrelevant
* If the sync bit is not set, a reference point approach must be implemented before operation
can continue in the Position Decoding mode.
Figure 15-15. Diagnostic Byte
15-26 EWA 4NEB 812 6120-02

15.6.3 Functional Description of the Counter Mode

In the operation mode “Counter”, the module works as a “port-controlled” up-counter and counts
the positive edges of the counting pulses while the enable input is active. If the counter reaches a
preselected setpoint, the respective output is enabled.
Initial Settings
Use the operating mode switch to make the following selections:
• “Counter” (C)
• Signal level of counting pulses (5 V or 24 V)
The position of the switches for the position resolution is irrelevant.
For this operation, you need a counting pulse sensor (e.g., BERO). The pulses can be applied as
5-V differential signals according to RS 422A (up to 500 kHz) or as 24-V signals (up to 25 kHz).
The sensor is connected to the sub-D connector of the module.
Loading Setpoints
The control program can transfer two setpoints to the module. These setpoints must be between 0
and 65,535. The transfer of the setpoints via the module depends on whether the “setpoint 1
(setpoint 2) reached” bit is set in the diagnostic byte (S1 and S2).
If the bit is not set, which means the existing setpoint has not been reached or has not been ex-
ceeded, the new setpoint is transferred immediately and is immediately valid.
If the bit is set, which means the existing setpoint has been reached or exceeded, the new setpoint
is valid only after a positive edge occurs at the enable input.
If you do not specify a setpoint, a setpoint of “0” applies.
Enabling the Counter

The signal state of the enable input (terminal 3 on the terminal block) determines the function of the
counter.
A positive edge at the enable input

• Sets the counter to 0
• Resets the diagnostic bits for “setpoint reached”
• Resets the outputs
• Enables the counter
Note
The enable input should be set to “1” only after the setpoint has been transferred.
Otherwise, the outputs are enabled automatically when the first positive edge occurs.
EWA 4NEB 812 6120-02 15-27

Disabling the Counter

A negative edge at the enable input disables the counter. The outputs, diagnostic bits, and the
counter are not reset. You can continue reading the current count. A positive edge at the enable
input resets the outputs and the diagnostic bytes.
Reaching the Setpoints - Setting the Outputs - Resetting the Outputs

If setpoints have been preselected and the counter is enabled, the module counts the positive edges
at the counter input. The count is incremented by “1” with every leading edge.
After setpoint 1 has been reached, output Q 0 is enabled. At the same time, status bit S1 is set.
After setpoint 2 has been reached, output Q 1 is enabled. At the same time, status bit S2 is set.
As long as the enable input is active, the counter counts the pulses. After the enable command has
been cancelled, the counter is disabled. The actual value remains constant.
You can read the current count in the STEP 5 program. The actual value is displayed as an
unsigned whole number and must be between 0 and 65,535.
Note
If no setpoint is preselected, the respective value “0” is assigned. The corresponding
output is enabled with the positive edge of the enable input.
Example: Setpoints S1=2 and S2=4 are entered into the counter
Counter status 0 1 2 3 4 5 5 0 1 2
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Counting pulses
Enable
input
Output Q 0
(setpoint 1
reached)
Pulse is not counted because
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counter is disabled by enable

Output Q 1 input=0.
(setpoint 2 The count is "frozen" to the
reached)
current value.
Figure 15-16. Switching the Outputs Dependent on the Status of the Counter and
the Enable Input
When the programmable controller goes from RUN to STOP, outputs Q 0 and Q 1 are reset.
15-28 EWA 4NEB 812 6120-02

Performance during Overflow

If the enabled counter exceeds the counter range limit 65,535 the following occurs:
• Bit 3 (overflow) in the diagnostic byte is set to “1”.
• The outputs and diagnostic bits for “setpoint reached” are disabled, but they remain unchanged.
The counting function continues. Thus the actual value is constantly updated.
You can continue to read all data from the module in the STEP 5 program:
• The updated count
• The status of the outputs at the time of the overflow (This status remains unchanged until the
overflow bit is reset.)
• The set overflow bit
After an overflow, the counter can be reset by one of the following actions:
• A positive edge at the enable input
• An overall reset of the programmable controller (STOP to RUN mode)
Note
After a cold restart of the programmable controller, the outputs are disabled. These
outputs can be enabled via a positive edge to the enable input.
15.6.4 Functional Description of the Position Decoder
In the operation mode “position decoder” the module works as an up/down-counter and counts the
pulses of the connected position encoder. Because of the phase offset of the two decoder signals
A and B, the counter determines the counting direction. If the counter reaches a preselected set-
point, the respective output is then turned on.
Settings
Set the following items on the operating mode switch:
• “Position decoding” (PD) function
• The desired position resolution (single, double, or quadruple)
• The signal level of the counting pulses (5 V or 24 V)
EWA 4NEB 812 6120-02 15-29

Connect the sub-D interface female connector to an incremental position encoder that has to deliver
the following signals:
• Two counting pulses offset by 90 degrees
• A reference pulse
The pulses can be supplied as 5-V differential signals according to RS 422 (up to 500 kHz) or as
24-V DC signals.
Connect a switch to the enable input. This switch must deliver a 24-V signal. In the same way, the
reference pulse has to deliver a 24-V signal to the reference input.
Position Resolution
• Counter capacity
The 16-bit up/down-counter permits a resolution of 65,536 units between -32,768 and +32,767.
The traversing range depends on the resolution of the position encoders.
• Pulse evaluation
The counting pulses, which are offset by 90 degrees, can be subjected to single, double, or
quadruple evaluation. The necessary setting is made on the operating mode switch (see
section 15.6).
The accuracy of the traversing path increases accordingly if double or quadruple pulse evaluation is
used. However, the traversing range then available is reduced by the factor 2 or 4.
Table 15-3. Pulse Evaluation

Single Double Quadruple
Evaluation Evaluation Evaluation
Counting pulse A
Counting pulse B
Count 0 1 0 1 2 01234
15-30 EWA 4NEB 812 6120-02

Example:
A rotary incremental position encoder produces 1000 pulses per revolution.
The spindle has a pitch of 50 mm/revolution. The position encoder therefore produces 1000 pulses
for a traversing path of 50 mm (1 revolution).
The resolution of the encoder is therefore 50 mm/1000 pulses.
The counter can handle up to 65,536 pulses. With the above resolution, the following traversing
ranges are obtained:
Table 15-4. Example for a Traversing Range

Pulse evaluation Single Double Quadruple
Traversing range 3.25 m (10.7 ft.) 1.625 m (5.3 ft.) 0.81 m (2.7 ft.)
Distance travelled/
50 µm 25 µm 12.5 µm
pulse
Loading Setpoints
In the STEP 5 program, two setpoints can be transferred to the module. These setpoints must lie
between -32768 and +32767.
The acceptance of the setpoints by the module depends on whether the “setpoint 1 (setpoint 2)
reached” bit has been set in the diagnostic byte.
If the bit is not set, which means the existing setpoint is not reached or not exceeded, the new
setpoint is immediately accepted and is immediately valid.
If the bit is set, which means the existing setpoint is reached or exceeded, the new setpoint is not
valid until a positive edge occurs at the enable input.
If you do not specify a setpoint, a setpoint of “0” applies.
Synchronization of the Actual Value Detection (Reference Point Approach)

The synchronization of the actual value detection is necessary after Power ON and after a counter
overflow.
Synchronization performs one of the following functions:

• The count (actual value) is set to “0” and the SYNC bit (bit 0 in the diagnostic bit) is set after
Power ON.
• The overflow bit (bit 3 in the diagnostic byte) is reset after an overflow.
EWA 4NEB 812 6120-02 15-31

Prerequisites for a Synchronization

• The reference signal
- The sensor for the reference signal is connected to terminals 7 and 8 of the terminal block.
- Synchronization is enabled with the leading edge (0 to 1) at terminal 8. If the signal was
already on “1” when the module was switched on, then the reference signal must be turned
off to restart the synchronization.
- If the reference signal lies in the normal traversing range, the actual value will be constantly
resynchronized by the reference signal. To prevent the unwanted resynchronizing, you have
to mask out the reference signal after the first reference point approach.
• The traversing direction after a positive edge of the reference signal
- After the reference signal has been reached, the module has to recognize a positive
traversing path (up-counting) while the reference signal is still active (1). This means, you
have to input the reference signal with increasing actual value to synchronize the module.
• The reference pulse
- The reference pulse is generated by the position encoder at least once per revolution.
The first reference pulse that the module recognizes after a leading edge of the reference
signal synchronizes the module. This is also valid if, after the first positive traversing path,
the direction is changed and a reference pulse is encountered (see Figure 15-19). If, during
post synchronization, the reference point is again passed, then you have to mask out the
reference signal after the synchronization reference point approach to avoid resynchronizing
the module.
The following three figures illustrate different possibilities for a reference traversing path:
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Reference Positive direction of traverse

signal
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Reference pulse
of the sensor
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Sync bit
Figure 15-17. Position of the Reference Point (SYNC Bit=1) within the
Reference Signal Range
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Positive direction of traverse

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Reference
signal
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Reference pulse
of the sensor
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Sync bit
Figure 15-18. Position of the Reference Point (SYNC Bit=1) after the Reference Signal
15-32 EWA 4NEB 812 6120-02

Function Modules S5100U
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Reference Positive direction of traverse

signal
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Reference pulse
of the sensor
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Change of direction
Reference
signal
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Reference pulse
of the sensor
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Sync
bit
Figure 15-19. Position of the Reference Point (SYNC Bit=1) during a Reversal of Direction
before Reaching the Reference Pulse in a Positive Direction
Example: Transporting objects from point A to point B on a conveyor belt.

A rotary position encoder is used, together with a BERO proximity switch as reference
transmitter. The conveyor belt is marked at a definite point. As soon as this mark
comes within the range of the BERO, the BERO produces a reference signal.
Following the reference point approach, the enable input is set via a digital output module.
Rotary position Operation range Conveyor belt

of reference
encoder transmitter
PS CPU DQ
Counting-up
direction
Mark
BERO as refer-
ence transmitter
Traversing path
Enable input
Reference input Traversing range
Figure 15-20. Schematic of a Reference Point Approach Operation
EWA 4NEB 812 6120-02 15-33

Starting the Counter

The counter is reset and started by setting the SYNC bit in the diagnostic byte during the reference
point approach operation. The active pulses are counted according to the rotation direction of the
position encoder. The count value is incremented during a positive count direction, and decremen-
ted during a negative count direction.
Enabling the Outputs - Reaching the Setpoints - Resetting the Outputs

The two outputs are enabled for switching by a positive pulse edge at the enable input.
An output and the associated diagnostic bit “setpoint reached” are set if all of the following
statements are true:
• The position decoder was synchronized (SYNC bit=1 and overflow bit=0).
• The enable signal (terminal 3 on the terminal block) is set to “1” signal.
• The actual value corresponds to the selected setpoint.
- The setpoint can be reached in the up-count or down-count direction.
Up-count direction Down-count direction

SYNC bit is set to begin SYNC bit is constantly set
Counter status 0 1 2 3 4 5 6 7 8
7 9 10 -10 -9 -8
7 -7 -6 -5 -4 -3 -2 -1 0 1
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Counting
pulses
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SYNC bit
(in diagnostic
byte)
Enable
input
Output Q0
(setpoint 1
reached)
Output Q1
(setpoint 2
reached)
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Measured counting pulse Counter is still disabled
Figure 15-21. Enabling the Outputs - Reaching the Setpoints - Resetting the Outputs
After reaching setpoint 1, the output Q 0 is energized and the status bit S1 is set. After reaching
setpoint 2, the output Q 1 is energized and status bit S2 is set.
As long as the enable input is active, the outputs are switchable through the module. If the enable
command is cancelled, the outputs are switched off and the diagnostic bits are reset. The current
actual value is still being measured and incremented or decremented depending on the direction of
rotation.
15-34 EWA 4NEB 812 6120-02

You can read the current count in the STEP 5 program. The actual value is displayed as a signed
whole number in two's complement and lies in the range - 32768 to +32767.
Note
Before you enable the outputs to be switched on by setting the enable input to “1”,
make sure the following conditions exist:
• Both setpoints were transferred.
• The overflow bit=0.
• The SYNC bit=1.
If you ignore these prerequisites, the outputs are switched on directly when the actual
value=0.
The diagnostic bit and the output are reset with the “0” signal at the enable input. Outputs Q 0 and
Q 1 are also reset when the programmable controller goes from RUN to STOP.
The following examples show the switching on of the output at the selected setpoint. There are
three possibilities:
• Reaching the setpoint in the direction of a rising actual value
• Reaching the setpoint in the direction of a falling actual value
• Reaching the setpoint in the direction of a rising actual value, then a reversal of direction and a
reapproaching of the setpoint in the opposite direction
Example 1: Approaching a Setpoint in Up-Count Direction
Enable input
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Direction of traverse
Output,
diagnostic bit
setpoint reached
Setpoint
Example of 1000 2000 3000 4000 5000 6000 7000
actual value
Figure 15-22. Approaching a Setpoint in Up-Count Direction
• Actual value=1000: The enable input is set to “1”.

• Actual value=3000: The setpoint is reached, output and diagnostic bit “setpoint reached” are
set.
• Actual value=6000: The enable input is set to “0”, output and diagnostic bit are reset.
EWA 4NEB 812 6120-02 15-35

Example 2: Approaching a Setpoint in Down-Count Direction
Enable input
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Output,
diagnostic bit
setpoint reached
Setpoint
Example of 1000 2000 3000 4000 5000 6000 7000
actual value
Figure 15-23. Approaching a Setpoint in Down-Count Direction
• Actual value= 7000: The enable input is set to “1”.

• Actual value= 3000: The setpoint is reached, the output and the diagnostic bit “setpoint
reached” are set.
• Actual value= 1000: The enable input is set to “0”, the output and the diagnostic bit are reset.
Example 3: Reversal of Direction after Approaching a Setpoint
Enable input
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Output, Setpoint Change of direction

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diagnostic bit Direction of traverse

setpoint reached
Example of 1000 2000 3000 4000 5000 6000 7000

actual value
Figure 15-24. Approaching a Setpoint in Up-Count Direction and

Consecutive Reversal of Direction
• Actual value=1000: The enable input is set to “1”.

• Actual value=3000: The setpoint is reached, the output and the diagnostic bit “setpoint
reached” are set.
• Actual value=4500: The traversing path is reversed.
• Actual value=1000: The enable input is set to “0”, the output and the diagnostic bit are reset.
Note
Set outputs can be reset only via a “0” signal to the enable input.
15-36 EWA 4NEB 812 6120-02

Performance during Overflow

If the counter leaves the counting range of -32768 to + 32767, then the following occurs:
• Bit 3 (overflow) in the diagnostic byte is set to “1”.
• The outputs of the counter module are disabled.
The enable input (terminal 4 of the terminal block) must be set to “0”, in order to switch off active
outputs.
After an overflow, a new reference point approach operation has to be executed for synchronization
of the actual value detection. After reaching the synchronization, bit 3 in the diagnostic byte is again
set to “0”, and the outputs along with the active enable input can be turned on.
Note
During an overflow, active outputs are not switched off, and the SYNC bit (bit 0 in the
diagnostic byte) is not reset.
EWA 4NEB 812 6120-02 15-37

15.6.5 Entering New Setpoints for the Counter and Position Decoder
Entering new setpoints is always possible via the PIQ. However, a setpoint is only valid if the
respective output is not switched on. The status of the outputs is displayed with diagnostic bits S1
and S2.
Diagnostic bit S1 (bit 1 in the diagnostic byte)=1: setpoint 1 is reached and output 1 is switched
on.
Diagnostic bit S2 (bit 2 in the diagnostic byte)=1: setpoint 2 is reached and output 2 is switched
on.
Table 15-5. Reaction of the Counter Module during Transfer of the Setpoints
Diag. Bit Response
S1 = 0 New setpoint 1 is transferred and is valid immediately.
S2 = 0 New setpoint 2 is transferred and is valid immediately.
S1 = 1 New setpoint 1 only becomes active if a positive edge has appeared at the
enable input.
S2 = 1 New setpoint 2 only becomes active if a positive edge has appeared at the
enable input.
Example:
You want to control a drive by using the outputs of the counter module. After a run of positioning,
both setpoints are reached and both outputs are turned on. You can enter the new setpoints by
using the following sequence:
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Enable input
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Output Q 0/
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Diag. bit S 1
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Output Q 1/
Diag. bit S 2
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S 1old S 2old S 1new S 2new
Figure 15-25. Requirement for New Setpoints
Transfer the new setpoints to the module. Since both diagnostic bits S1 and S2 are set to “1”,
the actual values are not yet accepted.
Switch the signal now at the enable input to “0”. With the falling edge, the outputs are switched
off and the diagnostic bits are reset.
Switch the signal at the enable input again to “1”. The new setpoints are accepted and are
now active.
After reaching the new setpoints, the respective output is switched on again.
15-38 EWA 4NEB 812 6120-02

15.6.6 Addressing
The counter module is addressed like an analog module (see section 6.3).
• The module may only be plugged into slots 0 to 7.
• The address range extends from byte 64 to byte 127.
• In both process image tables, eight bytes are reserved per slot and of these eight bytes only the
first four are used.
Slot Addressing
Table 15-6. Slot Addressing
Slot 0 1 2 3 4 5 6 7
Address 64 72 80 88 96 104 112 120

PII/PIQ to to to to to to to to
71 79 87 95 103 111 119 127
Meaning of the Bytes of a Slot Address (Example: Slot 1)
Table 15-7. Meaning of the Address Bytes of a Slot Address (Example: Slot 1)
Byte Byte Meaning in PII Meaning in PIQ

Number Address
0 72 Irrelevant High
byte
Setpoint 1
Low
1 73 Diagnostic byte
byte
High High
2 74
byte byte
Actual value Setpoint 2
Low Low
3 75
byte byte
4 to 7 76 to 79 Irrelevant
EWA 4NEB 812 6120-02 15-39

Examples for Data Exchange between the Programmable Controller and the Counter Module
Example 1:
The counter module is plugged into slot 4. If you now wish to check whether your system for
position decoding has been synchronized by a reference point approach, you must scan the sync bit
in the diagnostic byte (bit 0). If this bit is set, a branch is to be made to FB20. The position
decoding operation is started in FB20.
STL Description
...
A I 97.0 Read in bit 0 of the diagnostic byte (sync bit).
JC FB 20 If this bit is set, a branch is made to FB20.
If the bit is not set, program scanning is continued
... with the statement following the block call.
Example 2:
Transferring the setpoints stored in flag words 0 and 2 to the counter module inserted into slot 7.
The module has only to accept the setpoints when the old setpoints have been reached or
exceeded.
STL Description
...
AN I 121.1 If setpoint 1 has not yet been reached (bit 1=0), a
JC= L001 branch is made to label 1.
L FW 0 Read in setpoint 1
T QW 120 and transfer it to the counter module.
L001 AN I 121.2 If setpoint 2 has not yet been reached (bit 2=0), a
JC= L002 branch is made to label 2.
L FW 2 Read in setpoint 2
T QW 122 and transfer it to the counter module.
L002 BE Block end
...
15-40 EWA 4NEB 812 6120-02

15.7
4
3
2
1
on
Function Modules
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1 2
EWA 4NEB 812 6120-02

aaaaaaaa
S1
off
3
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4
5
6ES5 262-8MA12
CONTROLLER
6
6
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STATUS
CLOSED LOOP
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Closed-Loop Control Module IP 262

(6ES5 262-8MB12)
(6ES5 262-8MA12)
S5-100U
15-41
Address designation Analog outputs of the constant controller

(only for ET 200) 223 (6ES5 262-8MA11)
Controller Number of outputs 3

Total cycle time Output signal range 0 to 20 mA or
(equals scan time) 100 to 200 ms 4 to 20 mA
Resolution of the Maximum permissible load 600
open-loop controller 5 ms at 50 Hz No load voltage (L+) - 2 V
4.2 ms at 60 Hz
Binary outputs for the open-loop controller
Analog Inputs (6ES5 262-8MB11)
Number of inputs 4 (suited for Number of outputs 8
current, thermo- Galvanic isolation no
couple, or resist- Signal state “0” <1.5 V
ance thermometer) Signal state “1” (L+) - 3.8 V
Voltage with Maximum load current 100 mA short-circuit
external switching proof
Additional input for
reference temperature 1 (resistance Wiring method
thermometer)
Programmer (PG) front side via
Operator panel (OP) 15-pin subminiature
SINEC L1 network connection D connector
Permissible voltage difference
Connectable are PG 605, PG 615,
- between inputs - 1 V to +1 V
PG 635, PG 675,
PG 685, PG 695,
central ground point - 1 V to +1 V
PG 730, PG 750,
Digital representation OP 393, OP 396,
of the input signal 11 bits+sign OP 395
Current input Analog and binary inputs front side via

- input signal range 0 to 20 mA or 25-pin subminiature D
4 to 20 mA connector
- input resistance 24.3 ±0.1%
Analog and binary outputs via terminal block of the
mV Input (for thermocouple) bus unit
- input signal range 0 to 50 mV or
- 8.9 to 41.1 mV General data
(type J, K, L, S) Input voltage
Cable impedance 30 per wire - permissible range 18 to 34 V DC
- permissible range with
Resistance thermometer the PG 605/OP 393 18 to 27 V DC
- start 18.49
- end 219.12 Current consumption
- permissible cable impedance 30 per wire - internal (from
the CPU; 9 V) approx. 20 mA
Binary Inputs - external (for 24 V;
Number of inputs 4 without load) approx. 180 mA
- external (for 24 V;
Signals state “0” - 30 to+4.5 V without load;
or open with PG 605/OP 393) approx. 340 mA
Signal state “1” +13 to +30 V
(signal state Ambient temperature 0 ° to 55 °C
invertible) (32 to 131°F)
Input resistance approx. 4 k
15-42 EWA 4NEB 812 6120-02

Function
The S5-100U programmable controller offers different solutions for individual closed-loop control
tasks. First there is a software solution for CPU 103, version 8MA02 and higher, via function blocks.
Second, there is a control module solution (for example, a module that can solve PID control tasks
simply and in a time saving manner). The basis, in both cases, is a PID control algorithm.
The closed-loop control module IP 262 can be used with the S5-90U, S5-95U, and S5-100U
programmable controllers. It can be used without COM software.
The module relieves the programmable controller from closed-loop control tasks. The IP 262 also
works with its own power supply in a stand-alone operation. The module can function independently
without a programmable controller and can handle up to four closed-loop control circuits.
Two interfaces are located on the front panel of the module.
• An interface for the connection of a programmer (PG) or an operator panel (OP) or the
SINEC L1 Network (under development)
• An interface for the connection of analog and binary inputs
In addition, the following items are available:

• A selector switch for each channel for current and voltage (thermocouples or PT 100)
• A status LED for RUN (a continuously lit green light), transducer malfunction (blinking light), and
module malfunction (off)
The module is well suited to take over control-loop tasks in the area of industrial processing
technology, for example, temperature control, pressure and flow control, continuous injection
functions, and non-time-critical closed-loop rpm controls.
Modules
There are two IP 262 modules.
• ... - 8MA12 with 3 analog outputs for continuous controllers with analog output signals
• ... - 8MB12 with 8 binary outputs for continuous controllers with pulse time-interval signals or for
step-action controllers
Additionally, the module provides the following inputs:

• 4 analog inputs for direct feed of setpoint and actual values
• 4 binary inputs for control variables
Installation
• The closed-loop control module is plugged into a bus unit like any other input or output module
(see chapter 3).
• The module can only be plugged into slots 0 to 7.
• The connections for power supply and the analog and binary output signals are located on the
terminal block of the bus unit.
• The analog and binary inputs are connected to the module with a 25-pin sub-D female
connector.
EWA 4NEB 812 6120-02 15-43

Addressing
The module is addressed like a four-channel analog module.
Operating Modes
Since transducers and sensors are directly wired to the module, the module can work independently
from a programmable controller in stand-alone operation, provided that the setpoints and the 24-V
power supply voltage are fed directly to the IP 262. This means that the module executes the
control and the output of the manipulated variable and can work alone or be controlled via the
SINEC L1 by a master unit.
Besides this, the IP 262 has its own back-up, which means that the module can continue to work
alone in the event the master CPU (e.g., S5-135U with R64) fails. It uses the last setpoint received
from the CPU or the predefined back-up setpoint.
Two operating modes are possible:
• DDC Operation (Direct Digital Control)
- The control is executed entirely from the CPU. The IP only outputs the manipulated
variable. If the CPU fails, the module can continue to control independently with a
predefined back-up setpoint.
• SPC Operation (SetPoint Control)
- The module receives only the setpoint from the CPU; the control task is carried out
independently of the CPU. If the CPU fails, the IP continues to control using the last
setpoint received from the CPU. It is also possible to use a predefined back-up setpoint
here.
15-44 EWA 4NEB 812 6120-02

15.8 Positioning Module IP 266 (6ES5 266-8MA11)
Address designation
(only for ET 200) 095
Analog Output
Output signal range ±10 V
Digital signal representation 13 bits plus sign
Short-circuit proof yes
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Reference potential of the

FAULT analog output signal analog ground of the
power section
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ANALOG Cable length shielded max. 32 m (105 ft.)

OUT
Pulse Input
Position decoder incremental
Traverse range ±32767.999 mm/
0.1 inch/degree
Input voltages for the tracks
E - differential inputs 5 V/RS 422

N - asymmetrical inputs 24 V/typ. 7.3 mA
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C
O P Supply voltage for
D
the sensor
G (short-circuit proof) 5 V/350 mA
E
R
24 V/350 mA
Input Frequency and
Cable Length
Symmetrical sensors (5 V) max. 500 kHz,
max. 30 m (98 ft.) shielded
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6 cable length
Asymmetrical sensors
(24 V) max. 100 kHz for
25 m (82 ft.) cable
length shielded
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POSITIONING CONT.
MODULE IP 266 max. 25 kHz for 100 m
6ES5 266-8MA11 (330 ft.) cable length
1 2 3 4 5 6 shielded
Input Signals 2 pulse series 90
degrees out of phase
1 zero pulse
Digital Inputs
Input voltage range ±30 V
“0” signal - 30 V to +5 V
“1” signal 13 V to 30 V
Permissible zero signal
current at “0” signal 1.5 mA
Typ. input current at 24 V 7.3 mA
Digital Outputs
Output voltage range 20 V to 30 V
Max. output current at
“1” signal 100 mA
Short-circuit protector short-circuit proof output
Cable length shielded max. 100 m (330 ft.)
Supply Voltage
Logic voltage from 24-V
ext. supply produced
with switched-mode
power supply 4.7 V to 5.5 V
Current consumption from
24-V supply without out-
puts and 24-V sensor typ. 180 mA
EWA 4NEB 812 6120-02 15-45

Because of its performance capability and the complexity of its description, the IP 266 has its own
manual that you can order separately. The order number is: 6ES5 998-5SC21. The positioning
control module IP 266 expands the field of application for “positioning operations” of the S5-100U.
As an “intelligent I/O module”, it allows you to use open-loop as well as closed-loop control
positioning.
The positioning operations are processed independently of the execution times of the user programs
in the programmable controller. Thus the CPU is not burdened with positioning jobs constantly
being processed. You can plug the IP 266 into slots 0 to 7 on the S5-100U. The IP 266 is assigned
addresses in the analog address area of the programmable controller.
Operation Principle of the IP 266

The IP 266 enables you to control the positioning operation of your drive exactly. The module
delivers a voltage setpoint in the range of±10 V via an analog output for the control of a power
section for servo motors.
The IP 266 needs exact data about your drive system in order to calculate speed, acceleration, or
traverse residual distances. This data can be stored in an EEPROM that is permanently installed in
the programmable controller. By using its own start-up routine, this data can be accessed
immediately after you switch on the programmable controller and can be processed directly.
The IP 266 allows you to select between a linear axis and a circular axis. You can also select the
unit of measurement for processing the data: either [mm], [in.] or [deg].
Linear Axis Circular Axis

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Beginning/end of traversing range
Table
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Rotary table
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Continuous
belt
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Possible parameter units: [mm], [in.] Possible parameter units: [deg], [mm], [in.]
Figure 15-26. Units of Measurement that IP 266 Can Process for Circular Axis and Linear
Axis
15-46 EWA 4NEB 812 6120-02

Besides purely traversing movements, other operating modes allow offset generation of axis
coordinates or drift compensation in the system. In addition, the IP 266 offers operating modes to
read data such as positioning actual value or residual traversing distances.
In order to use the IP 266 in an automatic manufacturing process, it is possible to combine individual
traversing applications, positioning corrections, offsets or dwell times in a “traversing program”.
These traversing programs can be called up via two special operating modes and processed auto-
matically or semi-automatically.
Such a traversing program can be created by using the “learning capable” “Teach-in mode” for
positioning applications. The information from single positioning applications can be stored at the
end of an operation in a traversing program.
Positioning
For the positioning operation, the IP 266 calculates the setpoint from the selected end data and
velocity data in conjunction with the programmed machine data. The actual value follows the
selection. The deviation (following error) that occurs reaches a constant value after the short
start-up phase and must reach zero at the end of the positioning operation.
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S(t)
a = Setpoint function
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s b = Actual value function

a
S = Following error
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b
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t
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S
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s = const
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Figure 15-27. Course of a Following Error during a Positioning Operation
EWA 4NEB 812 6120-02 15-47

Overview of the Operation Modes
Table 15-8. Designation of the Operating Modes

List of the Operating Modes
JOG 1 AUTOMATIC SINGLE BLOCK ACKNOWLEDGE ERROR
JOG 2 TEACH-IN ON DRIFT COMPENSATION ON
CONTROLLED JOG TEACH-IN OFF DRIFT COMPENSATION OFF
FOLLOW-UP MODE ZERO OFFSET ABSOLUTE RAM EEPROM
REFERENCE POINT ZERO OFFSET RELATIVE READ ACTUAL POSITION
INCREMENTAL ABSOLUTE CLEAR ZERO OFFSET READ FOLLOWING ERROR
INCREMENTAL RELATIVE TOOL OFFSET ON READ DISTANCE TO GO
AUTOMATIC TOOL OFFSET OFF SYNCHRONIZE IP
The COM 266 software package offers user friendly operation and programming. The IP 266
exchanges all data with the programmable controller via a serial interface. All tasks written in 8-byte
messages are sent to the IP 266 during the program cycle via the process output image table (PIQ).
The IP 266 transmits feedback messages cyclically via the process image input table (PII). These
messages can be about the actual value position, remaining traversing distance, or following error as
well as a status byte, error byte, the current operation mode, and special data from the traversing
program.
Installation
1. Plug the IP 266 into a bus unit like any other I/O module (see chapter 3).
2. Insert the IP 266 only into slots 0 to 7.
3. Connect the external switches to the digital inputs of the IP 266 via the terminal block. These
switches are used to limit the traversing range. They also allow you to intervene at any time into
the processing of the module.
- The IP 266 can bypass the STEP 5 OB1 cycle, via three digital outputs, and send signals
directly to external I/Os. The controller must, however, be enabled (function signal enable
controller, FUM) and must be connected to the power section of the drive.
4. Connect the servo motor's power section to the 9-pin subminiature D female connector.
5. Connect the incremental encoder to the left 15-pin subminiature D female connector ENCODER.
You can connect a programmer with screen to the 15-pin subminiature D female connector on the
right side to operate the IP 266 via the COM software.
15-48 EWA 4NEB 812 6120-02

15.9 Stepper Motor Control Module IP 267 (6ES5 267-8MA11)
Address designation
Supply voltage (BUS) 9V

Current consumption approx. 150 mA
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ABT Special voltage VS 5 V to 30 V

US Digital Inputs
5V
Rated input voltage 24 V
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RDY
Input voltage:
“0” signal - 33 V to 5 V
“1” signal 13 V to 33 V
Input current typ. 8.5 mA
Supply voltage for
two-wire BEROs 22 V to 30 V
9-pin Subminiature D Connector
Output voltage
with 5-V supply
“0” signal max. 0.4 V
“1” signal min. 4.5 V
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With special supply
voltage VS
(5 V to 30 V)
“0” signal max. 0.4 V
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STEPPER MOTOR “1” signal min. VS - 0.4 V

MODUL IP 267
6ES5 267-8MA11 Output current 20 mA
1 2 3 4 5 6 (short-circuit proof)
Output frequency max. 204 kHz

Increment number
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+9 V
GND of steps max. 220 - 1 pulses/
Data job
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US 5 V - L
Permissible cable length max. 50 m (165 ft.) at
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9V 50 kHz
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5V
(twisted pair cable)
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24 V
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f
RDY
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5V
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ACT
t
G ABT
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ASIC
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1 3 5 7 9
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2 4 6 8 10
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+24 V +US
EWA 4NEB 812 6120-02 15-49

Because of its performance capability and the complexity of its description, the IP 267 has its own
manual that you can order separately. The order number is: 6ES5 998-5SD21. The IP 267 Stepper
Motor Control Module expands the field of application as an intelligent I/O module (IP) of the
S5-100U and S5-95U programmable controllers for “closed-loop control positioning". The IP 267
controls positioning processes independently of the run time of user programs in the programmable
controller. The CPU is not loaded with processing positioning job operations.
You can plug the IP 267 into slots 0 to 7 in the programmable controller. It then occupies addresses
in the analog address area of the programmable controller.
Principle of Operation
The IP 267 generates pulses for the stepper motor power section. The number of output pulses
determines the length of the traversing path. The pulse frequency is a measure of the velocity.
Each pulse causes the stepper motor shaft to turn through a certain angle. In the case of
high-speed pulse trains, this step movement becomes a constant rotational movement. Stepper
motors can reproduce all movement sequences only as long as no steps are lost. Step losses can
be caused when load variations occur or when the programmed pulse trains exceed motor-specific
values.
To enable the IP 267 to generate these pulse trains, the user must enter the following data:
• Configuration data: This data describes the individual stepper motors and the technical charac-
teristics of the drive system.
• Positioning data: This data describes the individual traverse jobs and indicates the velocities,
directions, and lengths of the configured paths.
The IP exchanges data with the programmable controller via the serial interface. During the program
scans, all necessary information is sent from the process image output table (PIQ) to the IP 267 in
4-byte messages. The IP 267 cyclically transmits feedback signals on the remaining distance to go
and various status bits to the process image input table (PII).
Using the configuration and positioning data settings, the IP 267 generates a symmetrical traverse
profile consisting of an acceleration ramp, a constant velocity range, and a deceleration ramp.
f
fA
fss
1. Accelera- 2. Constant stepping 3. Decelera-

tion ramp rate/velocity range tion ramp
t
fss = Start/stop rate; fA = Stepping rate
Figure 15-28. Velocity Profile of the IP 267
15-50 EWA 4NEB 812 6120-02

Using a limit switch on the digital inputs, IP 267 can monitor the limits of a traversing range and stop
the traversing movement when the permissible range limit is exceeded. The activated input
“external stop” causes a calculated decelerating of the traversing movement. An emergency limit
switch can be installed at input “IS” (pulse inhibit). When this switch responds, the pulse output is
interrupted immediately.
For a reference point approach operation, an additional switch can be connected at input REF that
lies within the traversing zone. The reference point approach operation is also possible without this
switch.
Status LEDs provide you with the following information:

• The IP 267 is configured RDY
• Pulse outputs during a positioning operation ACT
• Interruption of the positioning operation ABT
There are four operating modes:

• STOP
• START FORWARDS
• START BACKWARDS
• NEUTRAL
Installation
1. Plug the IP 267 into a bus unit like any other I/O module (see chapter 3).
2. Insert the IP 267 module only into slots 0 to 7.
3. Connect the external switches to the DIs of the IP 267 via the terminal block.
4. Connect the stepper motor's power section to the 9-pin subminiature D female connector.
Addressing
The IP 267 is addressed like an analog module.
EWA 4NEB 812 6120-02 15-51

15.10 Communications Modules
15.10.1 Printer Communications Module CP 521 (6ES5 521-8MA11)
Galvanic isolation TTY signals are

isolated
Memory submodule EPROM/EEPROM

Serial interface V.24
(RS-232-C)/TTY,
passive
Real-time clock
- accuracy ±2 s/day
- variation due to
temperature change tV
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aaaaaaaa
Battery
(ambient temperature TA in °C) - 3.5× (TA -15)2
3.4V
ms/day
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BATTERY - e.g. tolerance at 40 °C ±2 s - 3.5×

850mAh (104 °F) (40-15)2 ms/day
OFF/LOW
approx. 0 to - 4 s/day
Transmission mode asynchronous
10-bit character
frame
11-bit character
frame
Baud rate 110 to 9600 Bd
Permiss. length of cable

- TTY (PT 88) 30 m (98.4 ft.)
- V.24 (RS-232-C) 15 m (49.2 ft.)
Battery low LED

(yellow) yes
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6
Back-up battery
lithium AA 3.4 V/850 mAh
Life expectancy 1 year minimum
CP-521 Degree of protection IP20

PRINTER-INTERFACE
6ES5 521-8MA11 Permiss. ambient
1 2 3 4 5 6 temperature
(32 to 140 °F)
(32 to 104 °F)
Relative humidity 15% to 95%
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+9 V
Data from+9 V (CPU) typ. 140 mA
Power loss of the
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module typ. 1.2 W
Weight approx. 500 g (1 lb. 1.5 oz.)

Note:
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aaa
V.24
It is only possible to run the CP 521 with the interrupt
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aaa
module
processing if the interrupts are disabled at the end of
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aaa
TTY
the OB1 cycle and enabled again at the beginning of
the OB1 cycle.
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1 3 5 7 9
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2 4 6 8 10
15-52 EWA 4NEB 812 6120-02

The CP 521 is a powerful peripheral module that can be used with the SIMATIC systems S5-90U,
S5-95U, and the S5-100U. It has its own central processor (cannot be used with the CPU 100,
version 8MA01).
A separate manual for this module is available. The order number is 6ES5 100-0UD21.
A brief overview of the functions of this module follows.
Function
You can operate the CP 521 module in both the “printer mode” and the “ASCII mode”.
Printer Mode
In the printer mode, you can transfer message texts to a printer. You can print process data and
process malfunctions. The printing of messages to a printer does not increase the response time of
the programmable controller. You can print the following types of information:
• Messages configured by the user in a memory submodule in data blocks DB2 to DB63
• Time of day and date from the module's real-time clock
• Values for variables, transferred to the communications module via the S5-100 bus
The messages can be stored in an EPROM or in an EEPROM submodule (up to 8 Kbytes).
ASCII Mode
In the ASCII mode, the module can exchange data with other peripheral devices such as a computer
terminal, CP 523 or other CP 521s.
You can network programmable controllers to each other (point-to-point connection). The ASCII
mode makes it possible to transfer data messages between the CPU and a peripheral device
connected to the CP 521.
In the ASCII mode, the module’s real-time clock can be used for tasks in the user program requiring
the date and time of day.
The following statements are valid for both modes:
• The peripheral device and the module are connected via a serial interface. You can choose (by
setting parameters) between a passive TTY current-loop interface or an RS-232 V.24 interface.
• The DB editor of the programmers makes parameter setting to the printer interface and con-
figuration of message texts easier. You can either store the parameters for the printer interface
in DB1 on the memory submodule or transfer them directly into the user program.
The CP 521 can be programmed and operated without COM software.
EWA 4NEB 812 6120-02 15-53

Installation
1. Install the communications module on the bus module like any other I/O module
(see chapter 3)
2. Plug the module only into slots 0 to 7.
- The module has no connection to the terminal block.
3. Connect the printer to the module via a 25-pin sub-D female connector.
Addressing
The module is addressed like a 4-channel analog module.
15-54 EWA 4NEB 812 6120-02

15.10.2 Communications Module CP 521 BASIC (6ES5 521-8MB11)
Address designation
Galvanic isolation TTY signals are

isolated
Memory submodule EPROM/EEPROM/

RAM
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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
RUN Serial interface V.24

(RS-232-C)/TTY,
passive
PROG
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RXD Battery Real-time clock

TXD
3,4V - accuracy ±1 s/day at 25 °C
850mAh (77 °F)
RTS - variation due to
BATT temperature change tV
(ambient temperature TA in °C) -10 to +70 °C
1 s to -11 s
according to data
sheet
Quartz frequency 14.7456 MHz
Transmission mode asynchronous
10-bit character
frame/11-bit character
frame
Baud rate 110 to 9600 Bd

LEDs
- TXD send data
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6 - RXD receive data

- RTS ready to send
- BATT (yellow) battery low
Permiss. length of cable
CP-521 BASIC- - TTY dependent on:

SERIAL INTERFACE
6ES5 521-8MB11 voltage drop on the +line
1 2 3 4 5 6
- typical for receiver 1.5 V+
- typical for sender 0.9 V
- V.24 15 m (50 feet)
Back-up battery
lithium AA 3.4 V/850 mAh
Life expectancy 1 year minimum
Degree of protection IP20

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+9 V
GND Permiss. ambient
Data
temperature
(32 to 140 °F)
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BASIC - vertical arrangement 0 to 40 °C

+
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Interpreter (32 to 104 °F)
Relative humidity 15% to 95%

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V.24
Current consumption
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module
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TTY from+9 V (CPU) typ. 180 mA
Power loss of the

module typ. 1.6 W
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1 3 5 7 9 Weight approx. 500 g (1 lb. 1.5 oz.)

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2 4 6 8 10
Note:
It is only possible to run the CP 521 with the interrupt
processing if the interrupts are disabled at the end of
the OB1 cycle and enabled again at the beginning of
the OB1 cycle.
EWA 4NEB 812 6120-02 15-55

The CP 521 BASIC is a powerful peripheral module that can be used with the SIMATIC systems
S5-90U, S5-95U, and the S5-100U. It has its own central processor (cannot be used with the CPU
100, version 8MA01).
A separate manual for this module is available. The order number is 6ES5 521-8MB21.
A brief overview of the functions of this module follows.
Function
This module comes with a special COM software package that is required for generating and storing
BASIC programs (on a floppy disk or an EPROM submodule).
Since the CP 521 includes a basic interpreter, you can create and run BASIC programs that ex-
change data with a CPU and a connected peripheral device. Use a programmer or a PC terminal
and the COM software to program the BASIC interpreter.
You can store the BASIC programs in the module’s own battery backed-up RAM or on a plug-in
memory submodule.
Connect programmers or PC terminals to the CP 521 via a serial interface. You can choose (by
setting parameters) between a passive TTY current-loop interface or a RS-232 C V.24 interface to
connect a programmer or terminal. Connect a printer to the unidirectional V.24 interface of the
module to print listings or messages.
Change parameter settings for the peripheral interface by using a BASIC command or by using the
BASIC program.
The CP 521 has an integral real-time clock that can be backed up by a battery. You can use the
clock data in unidirectional data traffic to log process statuses or process malfunctions.
Installation
1. Install the communications module on the bus module like any other I/O module (see chapter 3).
2. Plug the module only into slots 0 to 7.
- The module has no connection to the terminal block.
3. Connect the printer to the module via a 25-pin sub-D female connector.
Addressing
The module is addressed like a 4-channel analog module.
15-56 EWA 4NEB 812 6120-02

A Operations List, Machine Code and List of Abbreviations
A.1 Operations List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1

A.1.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 1
A.1.2 Supplementary Operations ............................. A - 8
A.1.3 System Operations, for CPU 102 and Higher . . . . . . . . . . . . . . . . . A - 13
A.1.4 Evaluation of CC 1 and CC 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 14
A.2 Machine Code Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 15
A.3 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A - 18
EWA 4NEB 812 6120-02

S5-100U Operations List, Machine Code and List of Abbreviations
A Operations List, Machine Code and Abbreviations
A.1 Operations List
A.1.1 Basic Operations

For organization blocks (OB) For function blocks (FB)
For program blocks (PB) For sequence blocks (SB)
Oper- Permissible RLO* Execution Time in µs Function
ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Boolean Logic Operations
A I, Q N Y N typ. 4 1.6 0.8 Scan operand for “1” and

70 combine with RLO through
F N Y N logic AND.
T N Y N 7
C N Y N
AN I, Q N Y N typ. 4 1.6 0.8 Scan operand for “0” and

F N Y N logic AND.
T N Y N 9
Z N Y N
O I, Q N Y N typ. 4 1.6 0.8 Scan operand for “1” and
F N Y N
logic OR.
T N Y N 7
C N Y N
ON I, Q N Y N typ. 4 1.6 0.8 Scan operand for “0” and
F N Y N
logic OR.
T N Y N 9
C N Y N
O N Y Y 41 7 1.6 0.8 Combine AND operations

through logic OR.
A( N Y Y 61 6 1.6 0.8 Combine expressions enclosed

in parentheses through logic
AND (6 nesting levels).
O( N Y Y 64 6 1.6 0.8 Combine expressions enclosed

in parentheses through logic
OR (6 nesting levels).
) N Y N 51 13 1.6 0.8 Close parentheses (conclusion

of a parenthetical expression).
S I, Q Y N Y typ. 7 1.6 0.8 Set operand to “1”.

70
F Y N Y
* 1 RLO dependent ? 2 RLO affected ? 3 RLO reloaded ?
EWA 4NEB 812 6120-02 A-1

Operations List, Machine Code and List of Abbreviations S5-100U

ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Set/Reset Operations (cont.)
R I, O Y N Y typ. 7 1.6 0.8 Reset operand to “0”.

70
F Y N Y
= I, O N N Y typ. 6 1.6 0.8 Assign value of RLO to

70 operand.
F N N Y
Load Operations
L IB N N N 59 14 1.6 0.8 Load an input byte from the PII

into ACCU 1.
L QB N N N 63 14 1.6 0.8 Load an output byte from the

PIQ into ACCU 1.
L IW N N N 59 17 1.6 0.8 Load an input word from the

PII into ACCU 1:
byte n ACCU 1 (bits 8-15);
byte n+1 ACCU 1 (bits 0-7)
L QW N N N 63 17 1.6 0.8 Load an output word from the

PIQ into ACCU 1:
byte n+1 ACCU 1 (bits 0-7)
L PB/PY -- -- N -- -- 91 68 Permissible in OB2 and OB13.

(PG dep.) Load an input byte of the
digital/analog inputs from the
interrupt PII into ACCU 1.
L PW -- -- N -- -- 92 69 Permissible in OB2 and OB13.

Load an input byte of the
digital/analog inputs from the
interrupt PII into ACCU 1.
L FY N N N 64 14 1.6 0.8 Load a flag byte into ACCU 1.
L FW N N N 71 17 1.6 0.8 Load a flag word into ACCU 1:

byte n+1 ACCU 1 (bits 0-7).
L DL N N N 65 39 82 1.7 Load a data word (left-hand

byte) of the current data block
into ACCU 1.
L DR N N N 65 41 83 1.7 Load a data word (right-hand
byte) of the current data block
into ACCU 1.
L DW N N N 66 43 85 2.0 Load a data word of the cur-
rent data block into ACCU 1:
byte n+1 ACCU 1 (bits 0-7).
A-2 EWA 4NEB 812 6120-02


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Load Operations (cont.)

L KB N N N 54 7 59 1.45 Load a constant (1-byte
number) into ACCU 1.
L KS N N N 57 7 1.6 0.8 Load a constant (2 characters

in ASCII format) into ACCU 1.
L KF N N N 57 7 1.6 0.8 Load a constant (fixed-point

L KH N N N 57 7 1.6 0.8 Load a constant (hexadecimal

code) into ACCU 1.
L KM N N N 57 7 1.6 0.8 Load a constant (bit pattern)

into ACCU 1.
L KY N N N 57 7 1.6 0.8 Load a constant (2-byte

L KT N N N 57 7 1.6 0.8 Load a constant (time in BCD)

into ACCU 1.
L KC N N N 57 7 1.6 0.8 Load a constant (count in

BCD) into ACCU 1.
L T, C N N N typ. 19 1.6 0.8 Load a time or count (in binary

70 code) into ACCU 1.
LC T N N N 125 69 154 1.8 Load times or counts (in BCD)

into ACCU 1.
C N N N
Transfer Operations
T IB N N N 51 5 1.6 0.8 Transfer the contents of

ACCU 1 to an input byte (into
the PII).
T QB N N N 54 5 1.6 0.8 Transfer the contents of

ACCU 1 to an output byte (into
the PIQ).
T IW N N N 53 11 1.6 0.8 Transfer the contents of

ACCU 1 to an input word (into
the PII):
ACCU 1 (bits 8-15) byte n;
ACCU 1 (bits 0-7) byte n+1.
T QW N N N 56 11 1.6 0.8 Transfer the contents of
ACCU 1 to an output word (into
the PIQ):
T PB/PY -- -- N -- -- 60 37 Permissible in OB2 and OB13.

(PG-dep.) Transfer the contents of
ACCU 1 to the interrupt PIQ
with updating of the PIQ.
EWA 4NEB 812 6120-02 A-3


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Transfer Operations (cont.)

T PW -- -- N 67 51 Permissible in OB2 and OB13.
Transfer the contents of
ACCU 1 to the interrupt PIQ
with updating of the PIQ.
T FY N N N 55 5 1.6 0.8 Transfer the contents of

ACCU 1 to a flag byte.
T FW N N N 64 11 1.6 0.8 Transfer the contents of

ACCU 1 to a flag word (into the
PIQ):
T DL N N N 53 31 75 1.15 Transfer the contents of

ACCU 1 to a data word
(left-hand byte).
T DR N N N 57 33 78 1.15 Transfer the contents of

ACCU 1 to a data word (right-
hand byte).
T DW N N N 59 36 81 1.4 Transfer the contents of

ACCU 1 to a data word.
Timer Operations
SP T Y N Y 125 74 147 1.9 Start a timer (stored in
ACCU 1) as a signal-
contracting pulse.
SE T Y N Y 125 74 147 1.9 Start a timer (stored in

ACCU 1) as extended pulse
(signal contracting and
stretching).
SD T Y N Y 127 76 150 1.9 Start an on-delay timer (stored

in ACCU 1).
SS T Y N Y 127 76 150 1.9 Start a stored on-delay timer

(stored in ACCU 1).
SF T Y N Y 125 74 144 1.9 Start an off-delay timer (stored

in ACCU 1).
R T Y N Y 126 75 96 1.9 Reset a timer.

Counter Operations
CU C Y N Y 79 42 105 1.9 Counter counts up 1.

CD C Y N Y 92 31 117 1.9 Counter counts down 1.
A-4 EWA 4NEB 812 6120-02


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Counter Operations (cont.)

S C Y N Y 118 67 141 1.9 Set counter.
R C Y N Y 69 12 96 1.9 Reset counter.

Arithmetic Operations
+F N N N 55 26 1.6 0.8 Add two fixed-point numbers:

ACCU 1+ACCU 2.
CC 1/CC 0/OV are affected.
-F N N N 58 23 1.6 0.8 Subtract one fixed-point

number from another:
ACCU 2 - ACCU 1.
CC 1/CC 0/OV are affected.
Comparison Operations
!=F N Y N 79 24 1.6 0.8 Compare two fixed-point

numbers for “equal to”: If
ACCU 2=ACCU 1, the RLO
is “1”.
CC 1/CC 0 are affected.
><F N Y N 82 27 1.6 0.8 Compare two fixed-point
numbers for “not equal to”: If
ACCU 2 ACCU 1, the RLO
is “1”.
>F N Y N 79 24 1.6 0.8 Compare two fixed-point

numbers for “greater than”:
If ACCU 2 > ACCU 1, the
RLO is “1”. CC 1/CC 0 are
affected.
>=F N Y N 79 24 1.6 0.8 Compare two fixed-point
numbers for “greater than or
equal to”: If ACCU 2
ACCU 1, the RLO is “1”.
<F N Y N 82 27 1.6 0.8 Compare two fixed-point

numbers for “less than”:
If ACCU 2 < ACCU 1, the
affected.
<=F N Y N 82 27 1.6 0.8 Compare two fixed-point
numbers for “less than or equal
to”: If ACCU 2 ACCU 1, the
affected.
EWA 4NEB 812 6120-02 A-5


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Block Call Operations
JU PB N N Y 125 49 185 3.35 Jump unconditionally to a

program block.
JU FB N N Y 147 49 187 3.35 Jump unconditionally to a

function block.
JU SB N N Y -- -- 185 3.35 Jump unconditionally to a

sequence block.
JC PB Y Y1) Y 130 53 190 3.35 Jump conditionally to a

program block.
JC FB Y Y1) Y 152 53 196 3.35 Jump conditionally to a

function block.
JC SB Y Y1) Y -- -- 194 3.35 Jump conditionally to a

sequence block.
C DB N N N 70 28 79 1.75 Call a data block.
G DB N N Y -- -- 233 182 Generate or delete a data

block.
Return Operations
BE N N Y 88 36 119 2.5 Block end (termination of a

block)
BEC Y Y1) Y 90 38 121 2.5 Block end, conditional

BEU N N Y 88 36 119 2.5 Block end, unconditional (BEU
cannot be used in organization
blocks.)
“No” Operations
NOP 0 N N N 35 0 1.6 0.8 No operation (all bits reset)
NOP 1 N N N 35 0 1.6 0.8 No operation (all bits set)
Stop Operations
STP N N N 35 1 53 25 Stop: scanning is still comple-
ted before a stop. Error ID
“STS” is set in the ISTACK.
Display Generation Operations
BLD N N N 35 0 1.6 0.8 Display generation operation

130 for the programmer: carriage
return generates blank line.

131 for the programmer: switch to
statement list (STL).

1) RLO is set to “1”.
A-6 EWA 4NEB 812 6120-02

S5-100U Operations List, Machine Code and Abbreviations
Oper- Permissible Execution Time in µs Function

ation Operands RLO*
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Display Generation Operations (cont.)

control system flowchart (CSF).

ladder diagram (LAD).

255 for the programmer:
terminate a segment.
EWA 4NEB 812 6120-02 A-7

Operations List, Machine Code and Abbreviations S5-100U
A.1.2 Supplementary Operations

For organization blocks (OB) For function blocks (FB)
For program blocks (PB) For sequence blocks (SB)
ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Boolean Logic Operations

A= Formal- N Y N -- -- 202 151 AND operation: scan formal
operand operand for “1”.
I, Q, F, T, C (Data type: BI)
AN= Formal N Y N -- -- 202 151 AND operation: scan formal

O= Formal N Y N -- -- 202 151 OR operation: scan formal

ON= Formal N Y N -- -- 202 151 OR operation: scan formal
AW N N N 53 19 1.6 0.8 Combine contents of ACCU 2
and ACCU 1 through logic
AND (word operation).
Result is stored in ACCU 1.
OW N N N 53 19 1.6 0.8 Combine contents of ACCU 2
and ACCU 1 through logic OR
(word operation).
XOW N N N 51 19 1.6 0.8 Combine contents of ACCU 2
and ACCU 1 through logic
EXCLUSIVE OR (word oper-
ation).
Bit Operations
TB T, C N Y N -- -- 187 123 Test a bit of a timer or counter

word for “1”.
TB D N Y N -- -- 187 144 Test a bit of a data word

for “1”.
TB RS N Y N -- -- 185 121 Test a bit of a data word in the

system data area for “1”.
TBN T, C N Y N -- -- 188 124 Test a bit of a timer or counter

word for “0”.
A-8 EWA 4NEB 812 6120-02


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Bit Operations (cont.)

TBN D N Y N -- -- 188 145 Test a bit of a data word
for “0”.
TBN RS N Y N -- -- 186 122 Test a bit of a data word in the

system data area for “0”.
SU T, C N N Y -- -- 180 125 Set a bit of a timer or counter

word unconditionally.
SU D N N Y -- -- 183 146 Set a bit of a data word un-

conditionally.
RU T, C N N Y -- -- 189 124 Reset a bit of a timer or

counter word unconditionally.
RU D N N Y -- -- 189 146 Reset a bit of a data word

unconditionally.
S= Formal Y N Y -- -- 202 151 Set a formal operand
operand (when RLO=1).
I, Q, F (Data type: BI)
RB= Formal Y N Y -- -- 203 152 Reset a formal operand
operand (when RLO=1).
I, Q, F (Data type: BI)
RD= Formal Y N Y -- -- 197 147 Reset a formal operand
operand (digital) (when RLO=1).
T, C
== Formal Y N Y -- -- 202 151 Assign the value of the RLO to
operand the status of the formal
I, Q, F operand.
(Data type: BI)
FR T, C Y N Y -- -- 98 1.9 Enable a timer/counter for cold

restart. If RLO=“1”,
- “FR T” restarts the timer
- “FR C” sets, decrements, or
increments the counter.
FR= Formal op. T, Y N Y -- -- 194** 145** Enable formal operand (timer/

C counter) for cold restart (for
detailed description, see “FR”
operation).
SP= Formal op. T Y N Y -- -- 194** 145** Start a timer (formal operand)

as pulse with the value stored
in ACCU 1.
** +Execution of the substituted command
EWA 4NEB 812 6120-02 A-9


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Timer and Counter Operations (cont.)

SD= Formal op. Y N Y -- -- 194** 145** Start an on-delay timer (formal
T operand) with the value stored
in ACCU 1.
SEC Formal op. Y N Y -- -- 194** 145** Start a timer (formal operand)
= T, C as an extended pulse with the
value stored in ACCU 1, or
set a counter (formal operand)
with the next count value
indicated.
SSU Formal op. Y N Y -- -- 194** 145** Start a stored on-delay timer

= T, C (formal operand) with the
value stored in ACCU 1, or
increment a counter (formal
operand).
SFD= Formal op. Y N Y -- -- 194** 145** Start an off-delay timer (formal

T, C operand) with the value stored
in ACCU 1, or decrement a
counter (formal operand).
L= Formal N N N -- -- 142** 148** Load the value of the formal

operand operand into ACCU 1.
I, Q, F, T, C Data type: BY, W
Additional actual operands:
DL, DR, DW
L RS N N N -- -- 77 61 Load a word from the system

data area into ACCU 1.
LD= Formal N N N -- -- 194** 145** Load the value of the formal

operand operand in BCD code into
T, C ACCU 1.
LW= Formal N N N -- -- 152 76 Load a formal operand bit

operand pattern into ACCU 1.
Data type: D
Parameter type:
KC, KF, KH, KM, KS, KT, KY
T= Formal N N N -- -- 195** 149** Transfer the contents of
operand ACCU 1 to the formal operand.
I, Q, F Data type: BY, W
Additional actual operands:
DR, DL, DW
** +Processing time for the substituted command
A-10 EWA 4NEB 812 6120-02


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Conversion Operations
CFW N N N 42 4 1.6 0.8 Form the one's complement of
ACCU 1.
CSW N N N 60 23 1.6 0.8 Form the two's complement of

ACCU 1. CC 1/CC 0 and OV
are affected.
Shift Operations
SLW Parameter N N N 47+ 12+ 1.6 0.8 Shift the contents of ACCU 1
n=0 to 15 n·10 n·10 to the left by the value
specified in the parameter.
Unassigned positions are
padded with zeros.
SRW Parameter N N N 47+ 12+ 1.6 0.8 Shift the contents of ACCU 1
n=0 to 15 n·10 n·10 to the right by the value
specified in the parameter.
Unassigned positions are
padded with zeros.
Jump Operations
JU= Symbolic N N N 62 2 1.6 0.8 Jump unconditionally to the

address max. symbolic address.
4 characters
JC= Symbolic Y Y1) Y 65 5 1.6 0.8 Jump conditionally to the

address max. symbolic address. (If the RLO
4 characters is “0”, it is set to “1”.)
JZ= Symbolic N N N 69 6 1.6 0.8 Jump if the result is zero. The

address max. jump is made only if CC 1=0
4 characters and CC 0=0. The RLO is not
changed.
JN= Symbolic N N N 69 10 1.6 0.8 Jump if the result is not zero.

address max. The jump is made only if
4 characters CC 1 CC 0. The RLO is not
changed.
JP= Symbolic N N N 71 6 1.6 0.8 Jump if the sign of the result is

address max. “+”. The jump is made only if
4 characters CC 1=1 and CC 0=0. The
RLO is not changed.
JM= Symbolic N N N 71 6 1.6 0.8 Jump if the sign of the result is

address max. “-”. The jump is made only if
4 characters CC 1=0 and CC 0=1. The
RLO is not changed.
JO= Symbolic N N N 65 4 1.6 0.8 Jump on overflow. The jump is

address max. made only if the OVERFLOW
4 characters bit is set. The RLO is not
changed.

1) RLO is set to “1”.
EWA 4NEB 812 6120-02 A-11


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Other Operations
IA N N N -- -- 58 24 Disable interrupt. Input/
output interrupt or timer OB
processing is disabled.
RA N N N -- -- 58 26 Enable interrupt.
This operation cancels the
effect of IA.
D N N N -- -- 49 0,9 Decrement the low byte (bits 0
to 7) of ACCU 1 by the
value n (n=0 to 255).
I N N N -- -- 49 0,9 Increment the low byte (bits 0
to 7) of ACCU 1 by the
value n (n=0 to 255).
DO= Formal N N Y -- -- 252** 188** Process a block.
operand (Only C DB, JU OB, J U PB,
JU FB, JU SB can be
substituted.)
Actual operands: C DB,
JU OB, JU PB, JU FB, JU SB
DO DW*** N N N -- -- 229 171 Process data word. The next

operation is combined with the
parameter specified in the data
word (OR operation) and then
carried out.
DO FW*** N N N -- -- 179 138 Process flag word. The next

operation is combined with the
parameter specified in the flag
word (OR operation) and then
carried out.

** +Processing time for the substituted command
*** Permissible operations:
A, AN, O, ON L, LC, T;
S, R=; JU, JC, JZ, JN, JP, JM, JO, SLW, SRW;
FR T, RT, SF T, SD T, SP T, SS T, SE T; D, I;
FR C, RC, SC, CU, CD C; C DB, T RS, TNB
A-12 EWA 4NEB 812 6120-02

A.1.3 System Operations, for CPU 102 and Higher

ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Set Operations
SU RS N N Y -- -- 167 123 Set bit in system data area
unconditionally.
RU RS N N Y -- -- 167 123 Reset bit in system data area

unconditionally.

LIR N N N -- -- 105 76 Load the contents of a memory
word (addressed by ACCU 1)
indirectly into the register
(0: ACCU 1; 2: ACCU 2).
TIR N N N -- -- 85 61 Transfer the register contents

(0: ACCU 1; 2: ACCU 2)
indirectly into the memory
word (addressed by ACCU 1).
TNB Parameter N N N -- 13+n·19 97+ 75+ Transfer a field byte by byte

n=0 to 255 (48+n·19) n·21 n·16 (number of bytes 0 to 255).
T RS N N N -- -- 71 59 Transfer a word to the system

data area.
EWA 4NEB 812 6120-02 A-13


ation Operands
CPU 100 CPU 102 CPU 103
(STL) 1 2 3 MA02 MA03
Block Call Operations and Return Operations
JU OB N N Y -- -- 187 3.35 Call an organization block

unconditionally.
JC OB Y Y1) Y -- -- 194 3.35 Call an organization block

conditionally.
Jump Operation
JUR N N N -- -- 131 82 Jump at random within a

function block (jump distance
-32768 to + 32767)
Arithmetic Operations
ADD BF N N N -- -- 58 35 Add byte constant (fixed point)
to ACCU 1.
ADD KF N N N -- -- 104 68 Add fixed-point constant

(word) to ACCU 1.
Other Operations
STS N N N -- -- Stop operation. Program pro-
cessing is interrupted imme-
diately after this operation.
TAK N N N -- -- 74 57 Swap the contents of ACCU 1
and ACCU 2.
1) RLO is set to “1”
A.1.4 Evaluation of CC 1 and CC 0
Digital
CC 1 CC 0 Arithmetic Logic Comparison Shift Conversion
Operations Operations Operations Operations Operations
0 0 Result Result ACCU 2 shifted

=0 =0 = ACCU 1 bit = 0
0 1 Result ACCU 2 Result

<0 < ACCU 1 <0
1 0 Result Result ACCU 2 shifted Result

>0 0 > ACCU 1 bit = 1 >0
A-14 EWA 4NEB 812 6120-02

A.2 Machine Code Listing
Machine Code Machine Code

Oper- Oper- Oper- Oper-
B0 B1 B2 B3 ation and B0 B1 B2 B3 ation and
L R L R L R L R L R L R L R L R
0 0 0 0 NOP 0 1 E 0c 0c SEC=
0 1 0 0 CFW 1 F 0c 0c ==
0 2 0d 0d L T 2 0 0f 0f C DB
0 3 0l 0l TNB 2 1 2 0 >F
0 4 0d 0d FR T 2 1 4 0 <F
0 5 0 0 BEC 2 1 6 0 ><F
0 6 0c 0c FR= 2 1 8 0 !=F
0 7 0c 0c A= 2 1 A 0 >=F
0 8 0 0 IA 2 1 C 0 <=F
0 8 8 0 RA 2 2 0g 0g L DL
0 9 0 0 CSW 2 3 0g 0g T DL
0 A 0a 0a L FY 2 4 0d 0d SD T
0 B 0a 0a T FY 2 5 0i 0i JM=
0 C 0d 0d LC T 2 6 0c 0c SD=
0 D 0i 0i JO= 2 7 0c 0c AN=
0 E 0c 0c LC= 2 8 0e 0e L KB
0 F 0c 0c 0 2 A 0g 0g L DR
1 0 8 2 BLD 130 2 B 0g 0g T DR
1 0 8 3 BLD 131 2 C 0d 0d SS T
1 0 8 4 BLD 132 2 D 0i 0i JU=
1 0 8 5 BLD 133 2 E 0c 0c SSU=
1 0 F F BLD 255 2 F 0c 0c ON=
1 1 0n 0n I 3 0 0 1 0e 0e 0e 0e L KC
1 2 0a 0a L FW 3 0 0 2 0e 0e 0e 0e L KT
1 3 0a 0a T FW 3 0 0 4 0e 0e 0e 0e L KF
1 4 0d 0d SF T 3 0 1 0 0e 0e 0e 0e L KS
1 5 0i 0i JP= 3 0 2 0 0e 0e 0e 0e L KY
1 6 0c 0c SFD= 3 0 4 0 0e 0e 0e 0e L KH
1 7 0c 0c S= 3 0 8 0 0e 0e 0e 0e L KM
1 9 0n 0n D 3 2 0g 0g L DW
1 C 0d 0d SE T 3 3 0g 0g T DW
1 D 0f 0f JC FB 3 4 0d 0d SP T
EWA 4NEB 812 6120-02 A-15


3 5 0i 0i JN= 5 C 0o 0o S C
3 6 0c 0c SI= 5 D 0f 0f JC SB
3 7 0c 0c RB= 6 1 0h 0h SLW
3 C 0d 0d R T 6 2 0g 0g L RS
3 D 0f 0f JU FY 6 3 0g 0g T RS
3 E 0c 0c RD= 6 5 0 0 BE
3 F 0c 0c LW= 6 5 0 1 BEU
4 0 0 0k LIR 6 6 0c 0c T=
4 1 0 0 AW 6 9 0h 0h SRW
4 2 0o 0o L C 6 C 0o 0o CU C
4 4 0o 0o FR C 6 D 0f 0f JU OB
4 5 0i 0i JZ= 6 E 0g 0g DO DW
4 6 0c 0c L= 7 0 0 0 STS
4 8 0 0k TIR 7 0 0 2 TAK
4 9 0 0 OW 7 0 0 3 C 0 0o 0o STP
4 A 0a 0a L IB 7 0 1 5 8 0 0o 0o TB C
4 A 8a 0a L QB 7 0 1 5 4 0 0o 0o TBN C
4 B 0a 0a T IB 7 0 1 5 0 0 0o 0o SU C
4 B 8a 0a T QB 7 0 1 5 C 0 0d 0d RU C
4 C 0o 0o LC C 7 0 2 5 8 0 0d 0d TB T
4 D 0f 0f JC OB 7 0 2 5 4 0 0d 0d TBN T
4 E 0g 0g DO FW 7 0 2 5 0 0 0d 0d SU T
5 0 0e 0e ADD BF 7 0 2 5 C 0b 0g 0g RU T
5 1 0 0 XOW 7 0 4 6 8 0b 0g 0g TB D
5 2 0a 0a L IW 7 0 4 6 4 0b 0g 0g TBN D
5 2 8a 0a L QW 7 0 4 6 0 0b 0g 0g SU D
5 3 0a 0a T IW 7 0 4 6 C 0b 0g 0g RU D
5 3 8a 0a T QW 7 0 5 7 8 0b 0g 0g TB RS
5 4 0o 0o CD C 7 0 5 7 4 0b 0g 0g TBN RS
5 5 0f 0f 0e 0e 0e 0e JC PB 7 0 5 7 0 0b 0g 0g SU RS
5 8 0 0 ADD KF 7 0 5 7 RU RS
5 9 0 0 -F
A-16 EWA 4NEB 812 6120-02


7 2 0a 0a L PB/PY* B F 0 0 )
7 3 0a 0a T PB/PY* C 0b 0a 0a A I
7 5 0f 0f JU PB C 0b 8a 0a A Q
7 6 0c 0c DO= C 8b 0a 0a O I
7 8 0 5 0 0 0f 0f G DB C 8b 8a 0a O Q
7 9 0 0 +F D 0b 0a 0a S I
7 A 0a 0a L PW D 0b 8a 0a S Q
7 B 0a 0a T PW D 8b 0a 0a = I
7 C 0o 0o R C D 8b 8a 0a = Q
7 D 0f 0f JU SB E 0b 0a 0a AN I
7 E 0 0 DI E 0b 8a 0a AN Q
8 0b 0a 0a A F E 8b 0a 0a ON I
8 8b 0a 0a O F E 8b 8a 0a ON Q
9 0b 0a 0a S F F 0b 0a 0a R I
9 8b 0a 0a = F F 0b 8a 0a R Q
A 0b 0a 0a AN F F 8 0d 0d A T
A 8b 0a 0a ON F F 9 0d 0d O T
B 0b 0a 0a R F F A 0i 0i JC=
B 8 0o 0o A C F B 0 0 O
B 9 0o 0o O C F C 0d 0d AN T
B A 0 0 A( F D 0d 0d ON T
B B 0 0 O( F F F F NOP 1
B C 0o 0o AN C
B D 0o 0o ON C
* Depending on the type of programmer used
Explanation of the Indices
a + byte address h + number of shifts

b + bit address i + relative jump address
c + parameter address k + register address
d + timer number l + block length in bytes
e + constant m + jump displacement (16 bits)
f + block number n + value
g + word address o + counter number
EWA 4NEB 812 6120-02 A-17

Operations List, Machine Code and List of Abbreviabrations S5-100U
A.3 List of Abbreviations
Permissible Operand Value Range for

Abbreviation Explanation
CPU 100 CPU 102 CPU 103
ACCU 1 Accumulator 1 (When accumulator 1 is loaded,

any existing contents are shifted
into accumulator 2.)
ACCU 2 Accumulator 2
BF Byte constant (fixed-point number) (- 127 to +127) (- 127 to +127) (- 127 to +127)
C Counter (0 to 7) (0 to 7) (0 to 7)
- retentive (8 to 15) (8 to 127) (8 to 127)
- non-retentive (0 to 15) (0 to 127) (0 to 127)
- for the “Bit Test” and “Set” supplementary (0.0 to 127.15)
operations
CC 0/CC 1 Condition code 0/Condition code 1
CF DB1 parameter: input correction factor (integral

real-time clock)
CLK DB1 parameter: clock data location
CPU Central processing unit of programmable

controller
CSF STEP 5 control system flowchart method of

representation
D Data (1 bit) (0.0 to 255.15)
DB Data block (2 to 63) (2 to 63) (2 to 255)
DL Data word (left-hand byte) (0 to 255) (0 to 255) (0 to 255)
DR Data word (right-hand byte) (0 to 255) (0 to 255) (0 to 255)
DW Data word (0 to 255) (0 to 255) (0 to 255)
EF DB1 parameter: SINEC L1, position of receive

mailbox
F Flag - retentive (0.0 to 63.7) (0.0 to 63.7) (0.0 to 63.7)

- non-retentive (64.0 to 127.7) (64.0 to 127.7) (64.0 to 255.7)
FB Function block (0 to 63) (0 to 63*) (0 to 255)
FB/FY Flag byte - retentive (0 to 63) (0 to 63) (0 to 63)

Formal Expression with a maximum of 4 characters. The

operand first character must be a letter of the alphabet.
FW Flag word - retentive (0 to 62) (0 to 62) (0 to 62)

I Input (0.0 to 127.7) (0.0 to 127.7) (0.0 to 127.7)
IB Input byte (0 to 127) (0 to 127) (0 to 127)
IW Input word (0 to 126) (0 to 126) (0 to 126)
KB Constant (1 byte) (0 to 255) (0 to 255) (0 to 255)
KBE DB1 parameter: SINEC L1, position of the

“Receive” coordination byte
* +integrated FBs such as CPU 103
A-18 EWA 4NEB 812 6120-02

S5-100U Operations List, Machine Code and List of Abbreviabrations
CPU 100 CPU 102 CPU 103
KBS DB1 parameter: SINEC L1, position of the

“Send” coordination byte
KC Constant (count) (any two (any two

alphanumeric alphanumeric
characters) characters)
KF Constant (fixed-point number) (- 32768 to (- 32768 to (- 32768 to

+32767) +32767) +32767)
KH Constant (hexadecimal code) (0 to FFFF) (0 to FFFF) (0 to FFFF)
KM Constant (2-byte bit pattern) arbitrary bit arbitrary bit arbitrary bit
pattern: (16 bit) pattern: (16 bit) pattern: (16 bit)
KS Constant (2 characters) (0 to 999) (0 to 999) (0 to 999)
KT Constant (time) (0.0 to 999.3) (0.0 to 999.3) (0.0 to 999.3)
KY Constant (2 bytes) (0 to 255 each (0 to 255 each (0 to 255 each

byte) byte) byte)
LAD STEP 5-Ladder Diagram
NT DB1 parameter: number of timers being

processed
OB Organization block (0 to 63) (0 to 63) (0 to 255)

for special applications:
1, 3, 13, 21, 22, 31, 34, 251
OB13 DB1 parameter: interval (ms) within which OB13

is called and processed
OHE DB1 parameter: enable operating hours counter
OHS DB1 parameter: set operating hours counter
OP Operator panel
OV Overflow. This condition code bit is set if, e.g., a

numerical range is exceeded during arithmetic
operations.
PII Process image input table
PIQ Process image output table
PB Program block (0 to 63) (0 to 63) (0 to 255)

(with block call and return operations)
PB or PY Peripheral byte (0 to 127)

(depending
on type of
program-
mer used)
PG Programmer
PW Peripheral word (0 to 126)
Q Output (0.0 to 127.7) (0.0 to 127.7) (0.0 to 127.7)
QB Output Byte (0 to 127) (0 to 127) (0 to 127)
QW Output word (0 to 126) (0 to 126) (0 to 126)

EWA 4NEB 812 6120-02 A-19

Operations List, Machine Code and List of Abbreviabrations S5-100U
CPU 100 CPU 102 CPU 103
RLO Result of logic operation
RLO affected? The RLO is affected/not affected

Y/N by the operation.
RLO
dependent? The statement is executed only if the RLO is “1”.
Y The statement is executed only on
Y /Y positive/negative edge change of the RLO.
N The statement is always executed.
RLO reloaded? When the next binary operation takes place, the
Y/N RLO is reloaded/not reloaded (e.g. A I 0.0).
RS System data area (0 to 255)

- for load operations (supplementary operations)
and transfer operations (system operations) (0.0 to 255.15)
- for bit test and set operations (system
operations)
SAC STEP address counter
SAV DB1 parameter: Clock time after last switch from

STOP RUN or save from last Power OFF
SB Sequence block (0 to 255)
SDP DB1 block ID for system data parameters
SET DB1 parameter: Set clock/date
SF DB1 parameter: SINEC L1, position of send

mailbox
SL1 DB1 block ID for SINEC L1
SLN DB1 parameter: SINEC L1, slave number
STL STEP 5 statement list method of representation
STP DB1 parameter: update the clock while in the

STOP state.
STW DB1 parameter: status word location (integral

real-time clock)
T Timer (0 to 15) (0 to 31) (0 to 127)

- for the “Bit Test” and “Set” supplementary (0.0 to 127.15)
operations
TFB DB1 block ID for timer function block
TIS DB1 parameter: set prompt time
WD DB1 parameter: set scan time monitoring
A-20 EWA 4NEB 812 6120-02

B Dimension Drawings
EWA 4NEB 812 6120-02

Figures
B-1 Cross Sections of Standard Mounting Rails . . . . . . . . . . . . . . . . . . . . . . . . B - 1

B-2 Dimension Drawing of the 483-mm (19-in.) Standard Mounting Rail . . . . . . . B - 1
B-3 Dimension Drawing of the 530-mm (20.9-in.) Standard Mounting Rail . . . . . . B - 2
B-4 Dimension Drawing of the 830-mm (32.7-in.) Standard Mounting Rail . . . . . . B - 2
B-5 Dimension Drawing of the 2-m (6.6-ft.) Standard Mounting Rail . . . . . . . . . . B - 2
B-6 Dimension Drawing of the S5-100U (CPU) . . . . . . . . . . . . . . . . . . . . . . . . B - 3
B-7 Dimension Drawing of the Bus Unit (Crimp Snap-in Connections)

with I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B - 4
B-8 Dimension Drawing of the Bus Unit (SIGUT Screw-type Terminals)
with I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B - 5
B-9 Dimension Drawing of the IM 315 Interface Module . . . . . . . . . . . . . . . . . . B - 6
B-10 Dimension Drawing of the IM 316 Interface Module (6ES5 316-8MA12) . . . . B - 7
B-11 Dimension Drawing of the PS 930 and PS 931 Power Supply Modules .... B - 8
EWA 4NEB 812 6120-02

B
aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
De-
hole
hole
aaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
aaaaaaaa
S5-100U
burred
oblong
7 (0.3)
aaaaaaaa
aaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa
for oblong
Centerline
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8.7 (0.3)
aaaaaaaaaa
24 (1.0)
aaaaa
EWA 4NEB 812 6120-02

aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
2.5 (0.1)
aaaaaaaaaa
aaaaa
aaaaaaaaaa
15 (0.6)
aaaaaaaaaa
163.8 (6.5)
aaaaaaaaaa
R 1.2 (0.05)
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R 1.2 (0.05)
1
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15°
aaaaaaaaaa
aaaaa
rounded off to the nearest tenth or hundredth of an inch)
19 (0.8)
aaaaaaaaaa
Dimension Drawings
465.1 (18.3)
35 (1.4)
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aaaaaaaaaa
482.6 (19.0)
aaaaaaaaaa
Deburred
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155 (6.1)
24 (1.0)
aaaaaaaaaa
aaaaaaaaaa
aaaaaaaaaa
2.5 (0.1)
aaaaaaaaaa
aaaaa
aaaaaaaaaa
15 (0.6)
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Figure B-1. Cross Sections of Standard Mounting Rails

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R 1.2 (0.05)
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R 1.2 (0.05)
1
aaaaa aaaaaaaaaa
15°
aaaaa
11
aaaaaaaaaaaaaa
(0.4)
19 (0.8)
aaaaaaaaaaaaaa
Figure B-2. Dimension Drawing of the 483-mm (19-in.) Standard Mounting Rail
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35 (1.4)
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Dimensions are indicated in millimeters. The approximate equivalent in inches is indicated in parentheses. (1 mm=0.039 in.
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Deburred
Dimension Drawings
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B-1
Dimension Drawings S5-100U
15 (0.6) 20 x 25=500 (0.8 x 1.0=19.7)

25 (1.0)
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aaaaa
5.2 (0.2)
18 (0.7)
530 (20.9)
Figure B-3. Dimension Drawing of the 530-mm (20.9-in.) Standard Mounting Rail
15 (0.6) 32 x 25=800 (1.26 x 1.0=31.5)

25 (1.0)
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aaaaaaaaaa
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5.2 (0.2)
18 (0.7)
830 (32.7)
Figure B-4. Dimension Drawing of the 830-mm (32.7-in.) Standard Mounting Rail
2000 mm (6.6 ft.)
Figure B-5. Dimension Drawing of the 2-m (6.6-ft.) Standard Mounting Rail
B-2 EWA 4NEB 812 6120-02

S5-100U Dimension Drawings
81 (3.2)
91.5 (3.6)
63.5 (2.5) 35 (1.4)
135 (5.3)
120 127
(4.1) (5)
40 (1.6)
10.8 (0.4)
Figure B-6. Dimension Drawing of the S5 100U (CPU)
EWA 4NEB 812 6120-02 B-3

135 (5.3)
85 (3.4)
127 (5)
81 (3.2)
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aaaaaaaa
aaaaaaaa
aaaaaaaa
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135 (5.3) with crimp snap-in connection (6ES5 700-8MA21)

Standard
mounting rail
EN 50022-35 x 15
91.5
(3.6)
45.75
(1.8)
Figure B-7. Dimension Drawing of the Bus Unit (Crimp Snap-in Connections)
with I/O Module
B-4 EWA 4NEB 812 6120-02

135 (5.3)
85 (3.4)
127 (5)
81 (3.2)
162 (6.4) with screw type terminals (6ES5 700-8MA11)

EN 50022-35 x 15
91.5
(3.6)
45.75
(1.7)
Figure B-8. Dimension Drawing of the Bus Unit (SIGUT Screw-type Terminals)
with I/O Module
EWA 4NEB 812 6120-02 B-5

135
(5.3)
min. 210 (8.3)

max. 570 (22.4)
81 (3.2)
135
(5.3)
13.5 (0.5)
45.4 (1.8) 26 (1)

35 (1.4)
Figure B-9. Dimension Drawing of the IM 315 Interface Module
B-6 EWA 4NEB 812 6120-02

45.4
(1.8)
min. 210 (8.3)

max. 10000 (39.4)
81 (3.2)
135 (5.3)
13.5 (0.5)
26 (1)
35 (1.4)
Figure B-10. Dimension Drawing of the IM 316 Interface Module (6ES5 316-8MA12)
EWA 4NEB 812 6120-02 B-7

135 (5.3)
120 (4.7)
127 (5)
81 (3.2)
EN 50022-35×15
45.4 (1.8)
Figure B-11. Dimension Drawing of the PS 930 and PS 931 Power Supply Modules
B-8 EWA 4NEB 812 6120-02

C Active and Passive Faults in Automation Equipment
EWA 4NEB 812 6120-02

S5-100U Active and Passive Faults in Automation Equipment
C Active and Passive Faults in Automation

Equipment
Depending on the particular task for which the electronic automation equipment is used, both active
as well as passive faults can result in a dangerous situation. For example, in drive control, an
active fault is generally dangerous because it can result in an unauthorized startup of the drive. On
the other hand, a passive fault in a signalling function can result in a dangerous operating state not
being reported to the operator.
The differentiation of the possible faults and their classification into dangerous and non-dangerous
faults, depending on the particular task, is important for all safety considerations in respect to the
product supplied.
Warning
In all cases where a fault in automation equipment can result in severe personal injury or
substantial property damage, i.e., where a dangerous fault can occur, additional external
measures must be taken or equipment provided to ensure or force safe operating
conditions even in the event of a fault (e.g., by means of independent limit monitors,
mechanical interlocks, etc.).
Procedures for Maintenance and Repair

If you are carrying out measurement or testing work on an active unit, you must adhere to the rules
and regulations contained in the “VGB 4.0 Accident Prevention Regulations” of the German
employers liability assurance association (“Berufsgenossenschaften”). Pay particular attention to
paragraph 8, “Permissible exceptions when working on live parts.”
Do not open the S5-100U. Do not attempt to repair an item of automation equipment. Such repairs
may be carried out only by Siemens service personnel or repair shops Siemens has authorized
to carry out such repairs.
EWA 4NEB 812 6120-02 C-1

D Information for Ordering Accessories
EWA 4NEB 812 6120-02

S5-100U Information for Ordering Accessories
D Information for Ordering Accessories

Order Numbers
Standard 35 mm Mounting Rail

for 19-in. cabinets, length 483 mm 6ES5 710-8MA11
for 600 mm cabinets, length 530 mm 6ES5 710-8MA21
for 900 mm cabinets, length 830 mm 6ES5 710-8MA31
Length 2000 mm, without holes 6ES5 710-8MA41
Power Supply Modules

Power supply module PS 930
115/230 V AC; 1 A 6ES5 930-8MD11
Replacement fuse (3A extra-fast) 6ES5 980-3BC61
Power supply module PS 931
115/230 V AC; 24 V DC; 2 A 6ES5 931-8MD11
(with electronic circuit protection)
Load power supply 6EW1 6EW1 380-0AA

115/230 V AC; 24 V DC, 2 A 6EW1 380-0AA
115/230 V AC; 24 V DC; 4 A 6EW1 380-1AA
115/230 V AC; 24 V DC; 8 A 6EW1 380-4AA
Bus Units
Bus unit with SIGUT screw-type terminals 6ES5 700-8MA11
Bus unit with crimp snap-in terminals 6ES5 700-8MA21
Interrupt bus unit, with SIGUT screw-type terminals 6ES5 700-8MB11
Interrupt bus unit with crimp snap-in terminals 6ES5 700-8MB21
Accessories
Extracting tool
for crimp snap-in connections 6ES5 497-8MA11
Crimp snap-in contacts, 250 pieces 6XX3070
Crimping tool
for attaching the crimp contacts 6XX3071
Interface Modules
IM 315 interface module 6ES5 315-8MA11
IM 316 interface module 6ES5 316-8MA12
- Cable connectors (0.5 m/1.6 ft.) 6ES5 712-8AF00
- Cable connectors (2.5 m/8.2 ft.) 6ES5 712-8BC50
- Cable connectors (5.0 m/16.5 ft.) 6ES5 712-8BF00
- Cable connectors (10 m/33 ft.) 6ES5 712-8CB00
Central Processing Units (CPUs)

CPU 100 (without manual) 6ES5 100-8MA02
CPU 100 (with manual) German 6ES5 100-8MA12
” ” English 6ES5 100-8MA22
” ” French 6ES5 100-8MA32
” ” Spanish 6ES5 100-8MA42
” ” Italian 6ES5 100-8MA52
EWA 4NEB 812 6120-02 D-1

Information for Ordering Accessories S5-100U
Order Numbers


Accessories for the CPUs

Back-up battery lithium AA; 3.4 V/850 mAh 6ES5 980-0MB11
Memory submodule (EPROM) 4096 statements 6ES5 375-0LA15
Memory submodule (EEPROM) 1024 statements 6ES5 375-0LC11
Memory submodule (EEPROM) 2048 statements 6ES5 375-0LC21*
UV eraser
for 230 V AC/50 Hz 6ES5 985-1AA11
for 115 V AC/60 Hz 6ES5 985-1BA21
Programming pad (STL 50 sheets) E80850-C254-XA1
Manual for S5-100U, separately

German 6ES5 998-0UB13
English 6ES5 998-0UB23
French 6ES5 998-0UB33
Spanish 6ES5 998-0UB43
Italian 6ES5 998-0UB53
Manual for CP 521 Printer Output Module

German 6ES5 998-0UD11
English 6ES5 998-0UD21
French 6ES5 998-0UD31
Spanish 6ES5 998-0UD41
Italian 6ES5 998-0UD51
Manual for CP 521 BASIC Communications Module

German 6ES5 998-0UW11
English 6ES5 998-0UW21
French 6ES6 998-0UW31
* Only for CPUs with Order Number: -8MA02.

For CPU 100 (6ES5 100-8MA02), only 2 kbytes are useable.
D-2 EWA 4NEB 812 6120-02

Order Numbers
Manual for IP 262 Closed-Loop Control Module

German 6ES5 998-5SG11
English 6ES5 998-5SG21
Italian 6ES5 998-5SG51
Manual for IP 266 Positioning Module

German 6ES5 998-5SC11
English 6ES5 998-5SC21
Manual for IP 267 Stepper Motor Module

German 6ES5 998-5SD11
English 6ES5 998-5SD21
French 6ES5 998-5SD31
Spanish 6ES5 998-5SD41
Digital Input Modules

8 x 5 to 24 V DC isolated 6ES5 433-8MA11
4 x 24 V DC 6ES5 420-8MA11
8 x 24 V DC 6ES5 421-8MA12
8 x 24 V DC isolated 6ES5 431-8MA11
4 x 24 to 60 V DC isolated 6ES5 430-8MB11
4 x 115 V AC isolated 6ES5 430-8MC11
8 x 115 V AC isolated 6ES5 431-8MC11
4 x 230 V AC isolated 6ES5 430-8MD11
8 x 230 V AC isolated 6ES5 431-8MD11
Digital Output Modules

8 x 5 to 24 V DC/0.1 A isolated 6ES5 453-8MA11
4 x 24 V DC/0.5 A 6ES5 440-8MA11
4 x 24 V DC/2 A 6ES5 440-8MA21
8 x 24 V DC/0.5 A 6ES5 441-8MA11
8 x 24 V DC/0.5 A isolated 6ES5 451-8MA11
4 x 24 to 60 V DC/0.5 A isolated 6ES5 450-8MB11
4 x 115 to 230 V AC/1 A isolated* 6ES5 450-8MD11
8 x 115 to 230 V AC/0.5 A isolated* 6ES5 451-8MD11
4 relays x 30 V DC/230 V AC 6ES5 452-8MR11
8 relays x 30 V DC/230 V AC 6ES5 451-8MR12
* Replacement fuse (10 A extra-fast) 6ES5 980-3BC11
Digital Input/Output Module

24 V DC 16 inputs/16 outputs 6ES5 482-8MA12
Accessories
Crimp connector, 40 pin 6ES5 490-8MA12
EWA 4NEB 812 6120-02 D-3

Order Numbers
Analog Input Modules

4 x ± 50 mV isolated 6ES5 464-8MA11
4 x ± 50 mV isolated 6ES5 464-8MA21
4x±1V isolated 6ES5 464-8MB11
4 x ± 10 V isolated 6ES5 464-8MC11
4 x ± 20 mA isolated 6ES5 464-8MD11
4 x + 4 to 20 mA isolated 6ES5 464-8ME11
2 x PT 100/± 500 mV isolated 6ES5 464-8MF11
2 x PT 100/± 500 mV isolated 6ES5 466-8MF21
4 x + 0 to 10 V isolated 6ES5 466-8MC11
Analog Output Modules

2 x ± 10 V isolated 6ES5 470-8MA12
2 x ± 20 mA isolated 6ES5 470-8MB12
2 x + 4 to 20 mA isolated 6ES5 470-8MC12
2 x + 1 to 5 V isolated 6ES5 470-8MD12
Function Modules
IP 262 Closed-loop control module
- with 3 analog outputs 6ES5 262-8MA11
- with 8 binary outputs 6ES5 262-8MB11
IP 266 Positioning module 6ES5 266-8MA11
IP 267 Stepper motor control module 6ES5 267-8MA11
Diagnostic module 330 6ES5 330-8MA11
Timer module 380 2 x 0.3 to 300 s 6ES5 380-8MA11
Counter module 2 x 0 to 500 Hz 6ES5 385-8MA11
Counter module 385B 1 x 25/500 KHz 6ES5 385-8MB11
Comparator module 461 2 x 1 to 20 mA/0.5 to 10 V 6ES5 461-8MA11
CP 521 Printer output module 6ES5 521-8MA11
CP 521 BASIC communications module 6ES5 521-8MB11
Simulator 788 (digital input/output signals) 6ES5 788-8MA11
Operator Panels and Programmers

PG 605U Programmer 6ES5 605-0UA11
PG 605U Operator guide 6ES5 998-0UP11
PG 615 Programmer with connecting cable 6ES5 615-0UA11

PG 615 Operator guide 6ES5 998-0UR11
PG 615 Operating system submodules STEP 5
German 6ES5 815-0UA12
English 6ES5 815-0UB12
French 6ES5 815-0UC12
PG 615 Adapter with power supply unit

220/240 V AC 6ES5 984-2UA11
110/120 V AC 6ES5 984-2UB11
PG 615 Carrying case 6ES5 986-0MA11
Programmer PG 730 6EA1 730-0AA00-0AA0

Manual for PG 730 German 6ES5 834-0FC11
English 6ES5 834-0FC21
French 6ES5 834-0FC31
D-4 EWA 4NEB 812 6120-02

Order Numbers
PG 750 Programmer 6EA 1750-0AA00-0AA0

with 5 ” floppy disk drive
PG 750 Programmer 6EA1 750-0AF00-0AA0
with 3 ” floppy disk drive
PG 635 Programmer 6ES5 635-0UA13

Manual for PG 635 German 6ES5 835-0SC11
French 6ES5 835-0SC31
PG 685 Programmer 6ES5 685-0UA12

Manual for PG 685 German 6ES5 885-0SC11
French 6ES5 885-0SC31
PG 770-386 Programmer
with 100 mbyte fixed disk drive 6EA1 820-0AG02-0AA0
PG 770-486
with 210 mbyte fixed disk drive 6EA1 820-0CH03-0AA0
OP 393-II Operator panel

with connecting cable 6ES5 393-0UA13
OP 393-II Operator guide 6ES5 998-0UQ12
OP 395 Operator panel 6ES5 395-0UA11

OP 395 Operator guide 6ES5 998-0UN11
OP 396 Operator panel

with connecting cable 3 m (9.8 ft.) 6ES5 396-0UA11
OP 396 Operator guide 6ES5 998-0UK11
OP 396 Operating system submodule 6ES5 816-0AA11
OP 396 Adapter with power supply unit
for 230 V AC 6ES5 984-2UA11
for 115 V AC 6ES5 984-2UB11
728 Cable connector for connecting the OP 396 or PG 615 to the CPU
1 m (3.3 ft.) 6ES5 728-0BB00
2 m (6.6 ft.) 6ES5 728-0BC00
4 m (13.1 ft.) 6ES5 728-0BE00
5 m (16.4 ft.) 6ES5 728-0BF00
10 m (32.8 ft.) 6ES5 728-0CB00
20 m (65.6 ft.) 6ES5 728-0CC00
40 m (130 ft.) 6ES5 728-0CE00
80 m (260 ft.) 6ES5 728-0CJ00
100 m (330 ft.) 6ES5 728-0DB00
200 m (660 ft.) 6ES5 728-0DC00
400 m (1320 ft.) 6ES5 728-0DE00
800 m (2640 ft.) 6ES5 728-0DJ00
1000 m (3300 ft.) 6ES5 728-0EB00
EWA 4NEB 812 6120-02 D-5

Order Numbers
Program Packages
Basic Functions Program Package
with description in German, English, and French
for the S5-DOS operating system 6ES5 848-8AA01
for the MS-DOS, S5-DOS/MT operating system 6ES5 848-7AA01
Floating Point Arithmetic Program Package

for the S5-DOS operating system 6ES5 845-8GP01
for the MS-DOS, S5-DOS/MT operating system 6ES5 845-7GP01
GRAPH 5 Program Package

for the S5-DOS operating system 6ES5 845-8DA01
for the MS-DOS, S5-DOS/MT operating system 6ES5 845-7DA01
S5-100U Program Package

with description in
German 6ES5 840-4BC11
English 6ES5 840-4BC21
Italian 6ES5 840-4BC51
D-6 EWA 4NEB 812 6120-02

E Reference Materials
EWA 4NEB 812 6120-02

S5-100U Reference Materials
E Reference Materials
• Programming Primer for the SIMATIC® S5-100U

Practical Exercises with the PG 615 Programmer
Siemens AG, Berlin and Munich, 1989 (Order No.: ISBN 3-8009-1528-6)
• Automating with the SIMATIC S5-115U

Programmable Controllers
Hans Berger
Siemens AG, Berlin and Munich, 1989 (2nd Edition)
(Order No.: ISBN 3-8009-1530-8)
• Programmable Controllers
Basic Concepts
Siemens AG, 1989 (Order No.: ISBN 3-8009-8032-0)
EWA 4NEB 812 6120-02 E-1

F Siemens Addresses Worldwide
EWA 4NEB 812 6120-02

S5-100U Siemens Addresses Worldwide
F Siemens Addresses Worldwide

European Companies and Representatives
Austria Federal Republic Ireland
Siemens AG Österreich of Germany (continued) Siemens Ltd.
Vienna Hanover Dublin
Bregenz Leipzig
Graz Mannheim Italy
Innsbruck Munich Siemens S. p. A.
Klagenfurt Nuremberg Milan
Linz Saarbrücken Bari
Salzburg Stuttgart Bologna
Brescia
Belgium Finland Casoria
Siemens S.A. Siemens Osakeyhtiö Florence
Brussels Helsinki Genoa
Liège Macomer
Siemens N.V. France Padua
Brussels Siemens S.A. Rome
Antwerp Paris, Saint-Denis Turin
Gent Lyon, Caluire-et-Cuire
Marseilles Luxemburg
Bulgaria Metz Siemens S.A.
RUEN office of the Seclin (Lille) Luxembourg
INTERPRED corporation, Strasbourg
agency of the Malta
Siemens AG Sofia Great Britain J.R. Darmanin & Co., Ltd.
Sofia Siemens Ltd. Valletta
London, Sunbury-on-
Czechoslovakia Thames Netherlands
EFEKTIM Birmingham Siemens Nederland N.V.
Engineering Consultants, Bristol, Clevedon The Hague
Siemens AG Congleton
Prague Edinburgh Norway
Glasgow Siemens A/S
Denmark Leeds Oslo
Siemens A/S Liverpool Bergen
Copenhagen, Ballerup Newcastle Stavanger
Hojbjerg Trondheim
Greece
Federal Republic Siemens A.E. Poland
of Germany Athens PHZ Transactor S.A.
Branch offices of the Thessaloniki Warsaw
Siemens AG Gda sk-Letnica
Berlin Hungary Katowice
Bremen SICONTACT GmbH
Cologne Budapest Portugal
Dortmund Siemens S.R.A.L.
Düsseldorf Iceland Lisbon
Essen Smith & Norland H/F Faro
Frankfurt/Main Reykjavik Leiria
Hamburg Porto
EWA 4NEB 812 6120-02 F-1

Siemens Addresses Worldwide S5-100U
Romania Switzerland USSR

Siemens birou de Siemens-Albis AG Siemens AG Agency
consulta ii tehnice Zürich Moscow
Bukarest Bern
Siemens-Albis S.A. Yugoslavia
Spain Lausanne, Renens General Export
Siemens S.A. OOUR Zastupstvo
Madrid Turkey Belgrade
ETMA Ljubljana
Sweden Istanbul Rijeka
Siemens AB Adana Sarajewo
Stockholm Ankara Skopje
Eskilstuna Bursa Zagreb
Göteborg Izmir
Jönköping Samsun
Luleå
Malmö
Sundsvall
Non-European Companies and Representatives

Africa Ivory Coast Namibia
Siemens AG Siemens Resident
Algeria Succursale Côte d'Ivoire Engineer
Siemens Bureau Abidjan Windhoek
Alger
Algier Kenya Nigeria
Achelis (Kenya) Ltd. Electro Technologies
Angola Nairobi Nigeria Ltd. (Eltec)
Tecnidata Lagos
Luanda Libya
Siemens AG Rwanda
Burundi Branch Office Libya Etablissement Rwandais
SOGECOM Tripoli Kigali
Bujumbara
Mauritius Simbabwe
Egypt Rey & Lenferna Ltd. Electro Technologies
Siemens Resident Port Louis Corporation (Pvt.) Ltd.
Engineers Harare
Cairo-Mohandessin Morocco
Alexandria SETEL South Africa
Centech Société Electrotechnique Siemens Ltd.
Zamalek-Cairo et de Télécommunica- Johannesburg
tions S.A. Cape Town
Ethiopia Casablanca Durban
Addis Electrical Middleburg
Engineering Ltd. Mozambique Newcastle
Addis Abeba Siemens Resident Port Elizabeth
Engineer Pretoria
Maputo
F-2 EWA 4NEB 812 6120-02

Sudan Brazil Honduras

National Electrical & Siemens S.A. Representaciones Electro-
Commercial Company São Paulo industriales S. de R.L.
(NECC) Belém Tegucigalpa
Khartoum Belo Horizonte
Brasília Mexico
Swaziland Campinas Siemens S.A.
Siemens (Pty.) Ltd. Curitiba México, D.F.
Mbabane Florianópolis Culiacán
Fortaleza Gómez Palacio
Tanzania Porto Alegre Guadalajara
Tanzania Electrical Recife León
Services Ltd. Rio de Janeiro Monterrey
Dar-es-Salaam Salvador de Bahía Puebla
Vitoria
Tunesia Nicaragua
Sitelec S.A. Canada Siemens S.A.
Tunis Siemens Electric Ltd. Managua
Montreal, Québec
Zaire Toronto, Ontario Paraguay
SOFAMATEL S.P.R.L. Rieder & Cia., S.A.C.I.
Kinshasa Chile Asunción
INGELSAC
Zambia Santiago de Chile Peru
Electrical Maintenance Siemsa
Lusaka Ltd. Colombia Lima
Lusaka Siemens S.A.
Mining projects: Bogotá Uruguay
General Mining Baranquilla Conatel S.A.
Industries Ltd. Cali Montevideo
Kitwe Medellín
Venezuela
Costa Rica Siemens S.A.
Siemens S.A. Caracas
San José Valencia
Ecuador United States

America Siemens S.A. of America
Quito Siemens Industrial
Argentina OTESA Automation Inc.
Siemens S.A. Guayaquil Alpharetta, Georgia
Buenos Aires Quito
Bahía Blanca
Córdoba El Salvador
Mendoza Siemens S.A.
Rosario San Salvador
Bolivia Guatemala
Sociedad Comercial e Siemens S.A.
Industrial Hansa Ltd. Ciudad de Guatemala
La Paz
EWA 4NEB 812 6120-02 F-3

Siemens Addresses Worldwide S5-100U
Asia Jordan Philippine Islands

Siemens AG (Jordan Maschinen & Technik Inc.
Branch) (MATEC)
Bahrain Amman Manila
Transitec Gulf or
Manama A.R. Kevorkian Co. Qatar
or Amman Trags Electrical Engineering
Siemens Resident Engineer and
Abu Dhabi Korea (Republic) Air Conditioning Co.
Siemens Electrical Doha
Bangladesh Engineering Co., Ltd. or
Siemens Bangladesh Ltd. Seoul Siemens Resident Engineer
Dhaka Pusan Abu Dhabi
Hong Kong Kuwait Saudi Arabia

Jebsen & Co., Ltd. National & German Arabia Electric Ltd.
Hong Kong Electrical and Electronic (Equipment)
Service Co. (INGEECO) Jeddah
India Kuwait, Arabia Damman
Siemens India Ltd. Riyadh
Bombay Lebanon
Ahmedabad Ets. F.A. Kettaneh S.A. Sri Lanka
Bangalore Beirut Dimo Limited
Calcutta Colombo
Madras Malaysia
New Dehli Siemens AG Syria
Secundarabad Malaysian Branch Siemens AG
Kuala Lumpur (Damascus Branch)
Indonesia Damascus
P.T.Siemens Indonesia Oman
Jakarta Waleed Associates Taiwan
P.T. Dian-Graha Elektrika Muscat Siemens Liaison Office
Jakarta or Taipei
Bandung Siemens Resident TAI Engineering Co., Ltd.
Medan Engineers Taipei
Surabaya Dubai
Thailand
Iran Pakistan B. Grimm & Co., R.O.P.
Siemens Sherkate Siemens Pakistan Bangkok
Sahami Khass Engineering Co., Ltd.
Teheran Karachi United Arab Emirates
Islamabad Electro Mechanical Co.
Iraq Lahore Abu Dhabi
Samhiry Bros. Co. (W.L.L.) Peshawer or
Baghdad Quetta Siemens Resident Engineer
or Rawalpindi Abu Dhabi
Siemens AG (Iraq Branch) Scientechnic
Baghdad People's Republic of China Dubai
Siemens Represen- or
Japan tative Office Siemens Resident Engineer
Siemens K.K. Beijing Dubai
Tokyo Guangzhou
Shanghai
F-4 EWA 4NEB 812 6120-02

Asia (continued)
Yemen (Arab Republic)
Tihama Tractors &
Engineering Co.o., Ltd.
Sanaa
or
Siemens Resident Engineer
Sanaa
Australia
Australia
Siemens Ltd.
Melbourne
Brisbane
Perth
Sydney
New Zealand
Siemens Liaison Office
Auckland
EWA 4NEB 812 6120-02 F-5

Index
EWA 4NEB 812 6120-02

S5-100U Index
Index
A Block
Accumulator 8-10, 8-12 - call operations 8-33
Actual operand 7-14 - end symbol 9-4
Addition 8-31 - header 7-8
Address - ID 9-1, 9-5, 9-10
- absolute 5-9 - length 7-7
- relative 5-11 - parameters 7-14
Address assignment 6-7 - programming 7-8
- in RAM 6-15 - structure 7-6 - 7-8
- in the system data area 6-16 - type 7-5
AM flag 12-10 Boolean logic operation 8-2
Analog input module 11-1, 11-11 Broken wire 11-7
Analog modules BSTACK 5-12
- addressing 6-5 Bus cable 13-1
Analog output module 11-20 Bus terminal 13-1
Analog value Bus unit 2-2
- conversion 11-22 - installing 3-3
- output of (FB251) 9-14, 11-25,
- read in (FB250) 9-14, 11-17, C
11-22 Central Processing Unit (CPU) 2-1, 3-2
- scaling (FB250) 9-14, 11-22 Circuit diagram 7-3
Argument 9-5 Clock data
Arithmetic operations - 12-hour mode 12-10
- comparison 8-30 - 24-hour mode 12-10
- system 8-67 - area 12-8, 12-9,
Arithmetic unit 2-5 12-15
ASCII mode 15-53 - range definition 12-10
Assigning parameters 9-1 Clock pulse generator 8-73
Automation equipment Clock time correction factor 12-7, 12-35
- fault C-1 Closed-loop control module 15-41
Code converter
B - : 16 9-12
Back-up battery 4-8 - : B4 9-12
BASIC Comment 9-6
- creating a program in 15-56 - symbol 9-6
Basic operations 8-1 Communications module 15-52
Battery 4-8 - CP 512 Basic 15-55
- failure (OB34) 9-14 Comparator module 15-1
Binary coded representation 7-31, 7-32 Comparison
(BCD) - operation 8-30
Binary divider 8-71 Complement
Binary scaler 8-71 - one's 8-50
Bit pattern 11-11 - two's 8-50
Bit test operation 8-42 COMPRESS 7-30
Condition code generation 8-69
Control
- system flowchart (CSF) 7-2
EWA 4NEB 812 6120-02 1

Index S5-100U
Control Display generation operation 8-39

- deviation 9-21 Divider : 16 9-13
- variable 9-12 DO operation 8-54
- word 9-19
Controller E
- continuous action 9-15 Electromagnetic interference 3-22
Controller DB 9-15, 9-19 EMERGENCY OFF equipment 3-36
Conversion operation 8-50 Enable operation 8-41
Coordination byte Receive (KBE) 13-2, 13-10 Error
Coordination byte Send (KBS) 13-2, 13-8 - address 5-9
Correction rate - analysis 5-1, 5-5, 5-6
- algorithm 9-18 - indication 5-1
Correction value 12-35 - remedy 5-5, 5-6
Counter 2-4, 8-26 - 8-29 - parameter error 9-4, 9-8
- loading 8-25 Expansion capability
- operation 8-25 - maximum 2-8
- resetting 8-28, 8-29
- scanning 8-26 F
- setting 8-28, 8-29 Fault
Counter module - automation equipment C-1
- 25/500 kHz 15-17 FB250 11-22, 11-23
- 2×0 to 500 Hz 15-12 FB251 11-25
Counting pulse sensor Field transfer 8-66
- connection of 15-21 Filler 9-1, 9-5
CPU 2-1 Flags 2-4, 7-3
Crimp-snap-in FORCE VAR 12-19
- connection method 3-10 Formal operand 8-58
Four wire circuit 11-6
D Function module
Data block 7-5, 7-16 - addressing 6-7
- calling 8-33, 8-35 Function block 7-5, 7-11
- deleting 8-33, 8-35 - calling 7-14
- generating 8-33, 8-35 - header 7-12
Data cycle 2-7 - integrated 9-11
- interupt 2-7 - setting parameters 7-12, 7-15
Data exchange 13-7
DB1 9-1, 12-2 G
- function 7-17 GRAPH 5 7-1
DB1 parameter 9-10, 12-2 Grounding 3-3
- transfering 9-9
- setting 9-10 H
Decimal format 7-32 Hexadecimal representation 7-31
Default DB1 9-1, 13-5
Derivative action time 9-19 I
Design IM 2-2
- modular 1-2 IM 315 3-5
Diagnostic IM 316 3-5
- module 15-9 Increment operation 8-52
Digital input module 3-13 Input 7-3
Digital input/output module 3-18, 6-4 Input/output module 2-2
- address assignment 6-7
Digital logic operation 8-44
2 EWA 4NEB 812 6120-02

S5-100U Index
Installation of the S5-100U 3-1 O

- electrical 3-20, 3-21 OB2 10-1, 10-4
- horizontally 3-7 OB13 7-28
- mechanical 3-1 OB21 7-24
- mechanical, with external OB22 7-24
I/Os 3-4 On-delay 8-22, 8-23
- vertical 3-8 - stored 8-23
Integral action time (TN) 9-19 - timer 15-6
Interface Operand 7-1
- module 2-2, 3-5, 3-6 - areas 7-3
- serial 2-4 - ID 7-1
Interrupt Operating hours counter 12-7, 12-30
- disable 8-53 Operating mode
- PII 7-29, 10-3 - changing 4-2
- PIQ 7-29, 10-3 - display 4-1
- reaction time 10-7 - panel 4-2
Interrupt data cycle 2-7 - start-up 4-2
I/O bus 2-5, 2-6, 15-10 - switch 4-1
I/O modules 3-13, 5-14 Operating system 2-7
Operation 7-1, 8-1
J - basic 8-1
Jump - Boolean logic 8-2 - 8-7
- processing 8-57 - set/reset 8-7 - 8-9
- operation 8-56 - supplementary 8-1
- system 8-1
L Organization block 7-5, 7-9, 7-18
Ladder diagram (LAD) 7-1 - integrated 9-14
Leap year 12-10 Output 7-3
Lightning protection 3-30, 3-37 Overall reset 4-2
Linerization 11-8
Load operation 8-10, 8-11, 8-40, P
8-64 Parameter
Loading a time 8-14 - function block 7-12
Parameter block 9-1, 9-5
M Parameter error 9-4
Mode change 7-21 - correction 9-6
Modular design 1-2 - locating 9-8
Momentary contact relay/edge 8-71 - recognizing 9-8
evaluation Parameter error code 9-2, 9-7
Monitoring 5-10 - scanning 9-6
Mounting rail Parameter name 9-5
- standard 2-2 PID control algorithm
Multiplier: 16 9-16 (OB251) 9-15
PM flag 12-10
N Position
Nesting depth 7-6 - decoding 15-29
"NO" operation 8-38 - resolution 15-19, 15-26,
Normal mode 7-19 15-30
Number
- format 7-31
EWA 4NEB 812 6120-02 3

Index S5-100U
Position sensor Real-time clock

- connecting 15-20, 15-2 - integral 12-1
Positioning 15-46 - reading 12-21
- algorithm 9-18 - setting 12-5, 12-21
- closed-loop controlled 15-50 Receive Mailbox (EF) 13-2
- open-loop controlled 15-46 Reference
Positioning module IP 266 15-45 - point approach 15-31
Power supply - pulse 15-32
- frequency 11-7 - signal 15-32
- module 2-1, 3-2, 3-12 - variable 9-21
3-20 Reference potential 11-1
Printer communications module 15-52 Register contents
CP521 - loading and transfering 8-65
Printer mode 15-53 Removing the S5-100U 3-1, 3-2
Process image (PII, PIQ) 2-4, 7-29 Response time 7-27
Process image I/O tables 10-4 Retentive characteristics 2-5
- interrupt 6-12 Retriggering
- PII 6-8, 6-10, 10-3 - OB31 8-33
- PIQ 6-8, 6-11, 10-3 RLO 8-33
Processor 2-5
Program S
- block 7-5, 7-11 Sampling interval 9-18, 9-21
- memory 2-4, 7-30 Scan cycle time trigger 7-26
- structured 8-33 Scan monitoring time 7-26
Program check 4-11 Screw-type 3-18
Program processing 7-18 - connection method 3-9
- cyclical 7-26 SEARCH 5-11
- interrupt-driven 6-12, 7-29, 10-1 - function 4-11
- time-controlled 6-12, 7-28 Send Mailbox (SF) 13-2
Programmable controller Sensor lines 11-19
- design 2-1 Serial interface 2-4
Programming Sequence block 7-5, 7-11
- linear 7-4 Set operation 8-64
- structured 7-5 Set/reset operation 8-7 - 8-9
Prompt time 12-6, 12-25 Setpoint 9-19, 9-21
Proportional gain 9-19 Set time 15-5
Protective devices 3-36 Setting parameters
- against lightning 3-49 - for function blocks 7-15
PT 100 11-6 Shielding 3-29, 3-31
Pulse generator Shift operation 8-48
- connection of 15-21 Shift register 2-6
Pulse timer 8-20 - length 2-8
- extended 8-21 Shunt resistor 11-5
Simulator
R - module 15-7
Reaction time SINEC L1
- interrupt 10-5 - local area network 13-1
4 EWA 4NEB 812 6120-02

S5-100U Index
Slave 13-3, 13-5 U

Slot addressing 6-1 USTACK 5-1
SONAR BERO 11-23
Start ID 9-4, 9-5 W
START-UP 4-1, 7-24 Wiring
Starting up 4-4 - arrangement 3-29
Statement list (STL) 7-1 Wiring method
STATUS 4-8 - crimp-snap-in terminals 3-10
STATUS VAR 4-9 - screw-type terminals 3-9
Status word 12-12, 12-15
Stepper motor control 15-49
STOP operation 8-39
Substitution operation 8-58
Subtraction operation 8-31
Supplimentary operation 8-1, 8-31
System
- data 6-16
- operations 8-1, 8-64 - 8-67
- parameters 5-14
System data area 12-15
System data word 13-2
System characteristics
- defining in DB1 9-11
T
Terminal block 3-10
Temperature 11-3
- compensation 11-8
Test function
- STATUS 4-8
Test mode 7-19
Thermocouples 11-2
Time 8-17
- base 8-16, 8-17
- loading 8-14, 8-17
Time constant
- dominant 9-21
Timer 8-15 - 8-24
- module 15-4
- operation 8-15
- reset 8-15
- starting 8-15, 8-19
Transfer 8-12
- operation 8-10, 8-11, 8-64
Transfering a time 8-14
Two's complement 11-11
EWA 4NEB 812 6120-02 5

Siemens AG Sender (Please fill out)
AUT 125 Doku Name

Postfach 1963
D-92209 Amberg Company/Department
Fed. Rep. of Germany

Address
Suggestions: Corrections: Telephone

S5-100U (6ES5 998-0UB23)
Have you found any typographical errors while reading this manual? Please use this form to tell
us about them.
We would also welcome any ideas and suggestions you may have.
EWA 4NEB 812 6120-02a

Simatic S5: System Manual CPU 100/102/103

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SIMATIC S5

EWA 4NEB 812 6120-02a

Copyright© Siemens AG 1992

The reproduction, transmission or use of this document or its contents is not

EWA 4NEB 812 6120-02

EWA 4NEB 812 6120-02

Analog Value Processing

Diagnostics and Troubleshooting

Integrated Blocks and Their Functions

Interrupt Processing, for CPU 103 Version 8MA02 and Higher

How to Use This Manual .............................................

1 The SIMATIC S5 System Family .................................. 1 - 1

2 Technical Description ......................................... 2 - 1

2.1 Programmable Controller Design ............................. 2 - 1

2.2 Principle of Operation for the Programmable Controller . . . . . . . . . . . . . . 2 - 3

3 Installation Guidelines ......................................... 3 - 1

3.1 Installing S5-100U Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1

3.3 Electrical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

3.4 Wiring Arrangement, Shielding, and Measures to

3.5 Protective Devices and Insulation Monitoring Devices . . . . . . . . . . . . . . . 3 - 36

EWA 4NEB 812 6120-02 v

4 Start-Up and Program Tests ..................................... 4 - 1

4.1 Operating Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1

4.2 Starting Up a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3

4.3 Loading the Program into the Programmable Controller . . . . . . . . . . . . . . 4 - 5

4.4 Backing Up the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7

4.5 Program-Dependent Signal Status Display “STATUS” .............. 4 - 8

4.6 Direct Signal Status Display “STATUS VAR” ..................... 4 - 9

4.8 Forcing Variables, “FORCE VAR” ............................ 4 - 10

4.9 Search Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11

4.10 Program Check, for CPU 103 and Higher ....................... 4 - 11

5 Diagnostics and Troubleshooting ................................ 5 - 1

5.1 Indication of Errors by LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.2 CPU Malfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1

5.3 Program Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 9

5.4 I/O Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14

5.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14

5.6 The Last Resort ......................................... 5 - 15

vi EWA 4NEB 812 6120-02

6.1 Slot Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1

6.2 Digital Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4

6.3 Analog Modules ......................................... 6 - 5

6.4 Combined Input Modules and Output Modules . . . . . . . . . . . . . . . . . . . . 6 - 6

6.5 The Structure of Process Image Input and Output Tables . . . . . . . . . . . . 6 - 8

6.6 Interrupt Process Images Tables and Time-Controlled Program

6.7 RAM Address Assignments ................................. 6 - 15

7 Introduction to STEP 5 ......................................... 7 - 1

7.1 Writing a Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1

7.2 Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.3 Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7

7.4 Program Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

EWA 4NEB 812 6120-02 vii

7.4.5 Interrupt-Driven Program Processing, for CPU 103

7.5 Processing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 30

7.6 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 31

8.1 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1

8.2 Supplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 39

8.3 System Operations, for CPU 103 and Higher . . . . . . . . . . . . . . . . . . . . . 8 - 64

8.4 Condition Code Generation ................................. 8 - 69