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LM2662/LM2663 Switched Capacitor Voltage Converter

January 1999

LM2662/LM2663
Switched Capacitor Voltage Converter
General Description Features
The LM2662/LM2663 CMOS charge-pump voltage con- n Inverts or doubles input supply voltage
verter inverts a positive voltage in the range of 1.5V to 5.5V n Narrow SO-8 Package
to the corresponding negative voltage. The LM2662/LM2663 n 3.5Ω typical output resistance
uses two low cost capacitors to provide 200 mA of output n 86% typical conversion efficiency at 200 mA
current without the cost, size, and EMI related to inductor n (LM2662) selectable oscillator
based converters. With an operating current of only 300 µA frequency: 20 kHz/150 kHz
and operating efficiency greater than 90% at most loads, the
n (LM2663) low current shutdown mode
LM2662/LM2663 provides ideal performance for battery
powered systems. The LM2662/LM2663 may also be used
as a positive voltage doubler. Applications
The oscillator frequency can be lowered by adding an exter- n Laptop computers
nal capacitor to the OSC pin. Also, the OSC pin may be used n Cellular phones
to drive the LM2662/LM2663 with an external clock. For n Medical instruments
LM2662, a frequency control (FC) pin selects the oscillator n Operational amplifier power supplies
frequency of 20 kHz or 150 kHz. For LM2663, an external n Interface power supplies
shutdown (SD) pin replaces the FC pin. The SD pin can be n Handheld instruments
used to disable the device and reduce the quiescent current
to 10 µA. The oscillator frequency for LM2663 is 150 kHz.

Basic Application Circuits

Voltage Inverter Splitting VIN in Half

DS100003-1

Positive Voltage Doubler

DS100003-3

DS100003-2

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Absolute Maximum Ratings (Note 1) Output Short-Circuit Duration to GND (Note 2) 1 sec.
If Military/Aerospace specified devices are required, Power Dissipation (TA = 25˚C) (Note 3) 735 mW
please contact the National Semiconductor Sales Office/ TJ Max (Note 3) 150˚C
Distributors for availability and specifications. θJA (Note 3) 170˚C/W
Supply Voltage (V+ to GND, or GND to OUT) 6V Operating Junction Temperature
Range −40˚C to +85˚C
LV (OUT − 0.3V) to (GND + 3V)
Storage Temperature Range −65˚C to +150˚C
FC, OSC, SD The least negative of (OUT − 0.3V)
or (V+ − 6V) to (V+ + 0.3V) Lead Temperature (Soldering, 10 seconds) 300˚C
V+ and OUT Continuous Output Current 250 mA ESD Rating 2 kV

Electrical Characteristics
Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V+ = 5V, FC = Open, C1 = C2 = 47 µF.(Note 4)
Symbol Parameter Condition Min Typ Max Units
V+ Supply Voltage RL = 1k Inverter, LV = Open 3.5 5.5
Inverter, LV = GND 1.5 5.5 V
Doubler, LV = OUT 2.5 5.5
IQ Supply Current No Load FC = V+ (LM2662)
1.3 4
LV = Open SD = Ground (LM2663) mA
FC = Open 0.3 0.8
ISD Shutdown Supply Current
10 µA
(LM2663)
VSD Shutdown Pin Input Voltage Shutdown Mode 2.0 (Note 5)
V
(LM2663) Normal Operation 0.3
IL Output Current 200 mA
ROUT Output Resistance (Note 6) IL = 200 mA 3.5 7 Ω
fOSC Oscillator Frequency (Note 7) OSC = Open FC = Open 7 20
kHz
FC = V+ 55 150
fSW Switching Frequency (Note 8) OSC = Open FC = Open 3.5 10
kHz
FC = V+ 27.5 75
IOSC OSC Input Current FC = Open ±2
µA
FC = V+ ± 10
PEFF Power Efficiency RL (500) between V+ and OUT 90 96 %
IL = 200 mA to GND 86
VOEFF Voltage Conversion Efficiency No Load 99 99.96 %
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
beyond its rated operating conditions.
Note 2: OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be avoided. Also, for tem-
peratures above 85˚C, OUT must not be shorted to GND or V+, or device may be damaged.
Note 3: The maximum allowable power dissipation is calculated by using PDMax = (TJMax − TA)/θJA, where TJMax is the maximum junction temperature, TA is the
ambient temperature, and θJA is the junction-to-ambient thermal resistance of the specified package.
Note 4: In the test circuit, capacitors C1 and C2 are 47 µF, 0.2Ω maximum ESR capacitors. Capacitors with higher ESR will increase output resistance, reduce output
voltage and efficiency.
Note 5: In doubling mode, when Vout > 5V, minimum input high for shutdown equals Vout − 3V.
Note 6: Specified output resistance includes internal switch resistance and capacitor ESR.
Note 7: For LM2663, the oscillator frequency is 150 kHz.
Note 8: The output switches operate at one half of the oscillator frequency, fOSC = 2fSW.

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Test Circuits

DS100003-4

DS100003-5

FIGURE 1. LM2662 and LM2663 Test Circuits

Typical Performance Characteristics (Circuit of Figure 1)

Supply Current vs Supply Current vs

Supply Voltage Oscillator Frequency

DS100003-37
DS100003-38

Output Source
Resistance vs Supply
Voltage

DS100003-39

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Typical Performance Characteristics (Circuit of Figure 1) (Continued)

Output Source Output Source

Resistance vs Resistance vs
Temperature Temperature

DS100003-40 DS100003-41

Efficiency vs Load
Current

DS100003-42

Output Voltage Drop Efficiency vs

vs Load Current Oscillator Frequency

DS100003-43
DS100003-44

Output Voltage vs
Oscillator Frequency

DS100003-45

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Typical Performance Characteristics (Circuit of Figure 1) (Continued)

Oscillator Frequency Oscillator Frequency

vs External vs Supply Voltage
Capacitance

DS100003-47

DS100003-46

Oscillator Frequency Oscillator Frequency

vs Supply Voltage vs Temperature

DS100003-48 DS100003-49

Oscillator Frequency Shutdown Supply

vs Temperature Current vs
Temperature
(LM2663 Only)

DS100003-50

DS100003-51

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Connection Diagrams
8-Lead SO (M)

DS100003-20 DS100003-21

Top View
Order Number LM2662M, LM2663M
See NS Package Number M08A

Pin Description
Pin Name Function
Voltage Inverter Voltage Doubler
1 FC Frequency control for internal oscillator: Same as inverter.
(LM2662) FC = open, fOSC = 20 kHz (typ);
FC = V+, fOSC = 150 kHz (typ);
FC has no effect when OSC pin is driven
externally.
1 SD Shutdown control pin, tie this pin to the ground Same as inverter.
(LM2663) in normal operation.
2 CAP+ Connect this pin to the positive terminal of Same as inverter.
charge-pump capacitor.
3 GND Power supply ground input. Power supply positive voltage input.
4 CAP− Connect this pin to the negative terminal of Same as inverter.
charge-pump capacitor.
5 OUT Negative voltage output. Power supply ground input.
6 LV Low-voltage operation input. Tie LV to GND LV must be tied to OUT.
when input voltage is less than 3.5V. Above
3.5V, LV can be connected to GND or left
open. When driving OSC with an external clock,
LV must be connected to GND.
7 OSC Oscillator control input. OSC is connected to an Same as inverter except that OSC cannot be
internal 15 pF capacitor. An external capacitor driven by an external clock.
can be connected to slow the oscillator. Also,
an external clock can be used to drive OSC.
8 V+ Power supply positive voltage input. Positive voltage output.

Circuit Description
The LM2662/LM2663 contains four large CMOS switches
which are switched in a sequence to invert the input supply
voltage. Energy transfer and storage are provided by exter-
nal capacitors. Figure 2 illustrates the voltage conversion
scheme. When S1 and S3 are closed, C1 charges to the sup-
ply voltage V+. During this time interval switches S2 and S4
are open. In the second time interval, S1 and S3 are open
and S2 and S4 are closed, C1 is charging C2. After a number
of cycles, the voltage across C2 will be pumped to V+. Since
the anode of C2 is connected to ground, the output at the DS100003-22

cathode of C2 equals −(V+) assuming no load on C2, no loss FIGURE 2. Voltage Inverting Principle
in the switches, and no ESR in the capacitors. In reality, the
charge transfer efficiency depends on the switching fre-
quency, the on-resistance of the switches, and the ESR of
the capacitors.

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Application Information diode and potentially latching-up. Therefore, the Schottky di-
ode D1 should have enough current carrying capability to
charge the output capacitor at start-up, as well as a low for-
SIMPLE NEGATIVE VOLTAGE CONVERTER
ward voltage to prevent the internal parasitic diode from
The main application of LM2662/LM2663 is to generate a turning-on. A Schottky diode like 1N5817 can be used for
negative supply voltage. The voltage inverter circuit uses most applications. If the input voltage ramp is less than 10V/
only two external capacitors as shown in the Basic Applica- ms, a smaller Schottky diode like MBR0520LT1 can be used
tion Circuits. The range of the input supply voltage is 1.5V to to reduce the circuit size.
5.5V. For a supply voltage less than 3.5V, the LV pin must be
connected to ground to bypass the internal regulator cir- SPLIT V+ IN HALF
cuitry. This gives the best performance in low voltage appli-
Another interesting application shown in the Basic Applica-
cations. If the supply voltage is greater than 3.5V, LV may be
tion Circuits is using the LM2662/LM2663 as a precision volt-
connected to ground or left open. The choice of leaving LV
age divider. Since the off-voltage across each switch equals
open simplifies the direct substitution of the LM2662/
VIN/2, the input voltage can be raised to +11V.
LM2663 for the LMC7660 Switched Capacitor Voltage Con-
verter.
CHANGING OSCILLATOR FREQUENCY
The output characteristics of this circuit can be approximated
For the LM2662, the internal oscillator frequency can be se-
by an ideal voltage source in series with a resistor. The volt-
lected using the Frequency Control (FC) pin. When FC is
age source equals −(V+). The output resistance Rout is a
open, the oscillator frequency is 20 kHz; when FC is con-
function of the ON resistance of the internal MOS switches,
nected to V+, the frequency increases to 150 kHz. A higher
the oscillator frequency, and the capacitance and ESR of C1
oscillator frequency allows smaller capacitors to be used for
and C2. Since the switching current charging and discharg-
equivalent output resistance and ripple, but increases the
ing C1 is approximately twice as the output current, the effect
typical supply current from 0.3 mA to 1.3 mA.
of the ESR of the pumping capacitor C1 is multiplied by four
in the output resistance. The output capacitor C2 is charging The oscillator frequency can be lowered by adding an exter-
and discharging at a current approximately equal to the out- nal capacitor between OSC and GND (See typical perfor-
put current, therefore, its ESR only counts once in the output mance characteristics). Also, in the inverter mode, an exter-
resistance. A good approximation is: nal clock that swings within 100 mV of V+ and GND can be
used to drive OSC. Any CMOS logic gate is suitable for driv-
ing OSC. LV must be grounded when driving OSC. The
maximum external clock frequency is limited to 150 kHz.
The switching frequency of the converter (also called the
where RSW is the sum of the ON resistance of the internal
charge pump frequency) is half of the oscillator frequency.
MOS switches shown in Figure 2.
Note: OSC cannot be driven by an external clock in the voltage-doubling
High value, low ESR capacitors will reduce the output resis- mode.
tance. Instead of increasing the capacitance, the oscillator
frequency can be increased to reduce the 2/(fosc x C1) term.
Once this term is trivial compared with RSW and ESRs, fur- TABLE 1. LM2662 Oscillator Frequency Selection
ther increasing in oscillator frequency and capacitance will FC OSC Oscillator
become ineffective.
Open Open 20 kHz
The peak-to-peak output voltage ripple is determined by the
V+ Open 150 kHz
oscillator frequency, and the capacitance and ESR of the
output capacitor C2: Open or V+ External Capacitor See Typical
Performance
Characteristics
N/A External Clock External Clock
Again, using a low ESR capacitor will result in lower ripple. (inverter mode only) Frequency

POSITIVE VOLTAGE DOUBLER

The LM2662/LM2663 can operate as a positive voltage dou- TABLE 2. LM2663 Oscillator Frequency Selection
bler (as shown in the Basic Application Circuits). The dou- OSC Oscillator
bling function is achieved by reversing some of the connec-
tions to the device. The input voltage is applied to the GND Open 150 kHz
pin with an allowable voltage from 2.5V to 5.5V. The V+ pin External See Typical Performance
is used as the output. The LV pin and OUT pin must be con- Capacitor Characteristics
nected to ground. The OSC pin can not be driven by an ex- External Clock External Clock Frequency
ternal clock in this operation mode. The unloaded output
voltage is twice of the input voltage and is not reduced by the (inverter mode only)
diode D1’s forward drop.
The Schottky diode D1 is only needed for start-up. The inter- SHUTDOWN MODE
nal oscillator circuit uses the V+ pin and the LV pin (con- For the LM2663, a shutdown (SD) pin is available to disable
nected to ground in the voltage doubler circuit) as its power the device and reduce the quiescent current to 10 µA. Apply-
rails. Voltage across V+ and LV must be larger than 1.5V to ing a voltage greater than 2V to the SD pin will bring the de-
insure the operation of the oscillator. During start-up, D1 is vice into shutdown mode. While in normal operating mode,
used to charge up the voltage at V+ pin to start the oscillator; the SD pin is connected to ground.
also, it protects the device from turning-on its own parasitic

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Application Information (Continued)

CAPACITOR SELECTION
As discussed in the Simple Negative Voltage Converter section, the output resistance and ripple voltage are dependent on the
capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the output resistance,
and the power efficiency is

Where IQ(V+) is the quiescent power loss of the IC device, and IL2ROUT is the conversion loss associated with the switch on-
resistance, the two external capacitors and their ESRs.
Low ESR capacitors (Table 3) are recommended for both capacitors to maximize efficiency, reduce the output voltage drop and
voltage ripple. For convenience, C1 and C2 are usually chosen to be the same.
The output resistance varies with the oscillator frequency and the capacitors. In Figure 3, the output resistance vs. oscillator fre-
quency curves are drawn for four difference capacitor values. At very low frequency range, capacitance plays the most important
role in determining the output resistance. Once the frequency is increased to some point (such as 100 kHz for the 47 µF capaci-
tors), the output resistance is dominated by the ON resistance of the internal switches and the ESRs of the external capacitors.
A low value, smaller size capacitor usually has a higher ESR compared with a bigger size capacitor of the same type. Ceramic
capacitors can be chosen for their lower ESR. As shown in Figure 3, in higher frequency range, the output resistance using the
10 µF ceramic capacitors is close to these using higher value tantalum capacitors.

DS100003-36

FIGURE 3. Output Source Resistance vs Oscillator Frequency

TABLE 3. Low ESR Capacitor Manufacturers

Manufacturer Phone Capacitor Type
Nichicon Corp. (708)-843-7500 PL, PF series, through-hole aluminum electrolytic
AVX Corp. (803)-448-9411 TPS series, surface-mount tantalum
Sprague (207)-324-4140 593D, 594D, 595D series, surface-mount tantalum
Sanyo (619)-661-6835 OS-CON series, through-hole aluminum electrolytic
Murata (800)-831-9172 Ceramic chip capacitors
Taiyo Yuden (800)-348-2496 Ceramic chip capacitors
Tokin (408)-432-8020 Ceramic chip capacitors

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Other Applications
PARALLELING DEVICES

Any number of LM2662s (or LM2663s) can be paralleled to reduce the output resistance. Each device must have its own pumping
capacitor C1, while only one output capacitor Cout is needed as shown in Figure 4. The composite output resistance is:

DS100003-24

FIGURE 4. Lowering Output Resistance by Paralleling Devices

CASCADING DEVICES
Cascading the LM2662s (or LM2663s) is an easy way to produce a greater negative voltage (as shown in Figure 5). If n is the
integer representing the number of devices cascaded, the unloaded output voltage Vout is (−nVin). The effective output resistance
is equal to the weighted sum of each individual device:

A three-stage cascade circuit shown in Figure 6 generates −3Vin, from Vin.

Cascading is also possible when devices are operating in doubling mode. In Figure 7, two devices are cascaded to generate 3Vin.
An example of using the circuit in Figure 6 or Figure 7 is generating +15V or −15V from a +5V input.
Note that, the number of n is practically limited since the increasing of n significantly reduces the efficiency and increases the out-
put resistance and output voltage ripple.

DS100003-25

FIGURE 5. Increasing Output Voltage by Cascading Devices

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Other Applications (Continued)

DS100003-26

FIGURE 6. Generating −3Vin from +Vin

DS100003-27

FIGURE 7. Generating +3Vin from +Vin

REGULATING Vout
It is possible to regulate the output of the LM2662/LM2663 by use of a low dropout regulator (such as LP2986). The whole con-
verter is depicted in Figure 8. This converter can give a regulated output from −1.5V to −5.5V by choosing the proper resistor ratio:

where, Vref = 1.23V

The error flag on pin 7 of the LP2986 goes low when the regulated output at pin 5 drops by about 5% below nominal. The LP2986
can be shutdown by taking pin 8 low. The less than 1 µA quiescent current in the shutdown mode is favorable for battery powered
applications.

DS100003-28

FIGURE 8. Combining LM2662/LM2663 with LP2986 to Make a Negative Adjustable Regulator

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Other Applications (Continued)

Also, as shown in Figure 9 by operating the LM2662/LM2663 in voltage doubling mode and adding a low dropout regulator (such
as LP2986) at the output, we can get +5V output from an input as low as +3.3V.

DS100003-29

FIGURE 9. Generating +5V from +3.3V Input Voltage

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LM2662/LM2663 Switched Capacitor Voltage Converter

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead SO (M)
Order Number LM2662M or LM2663M
NS Package Number M08A

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tems which, (a) are intended for surgical implant into device or system whose failure to perform can be rea-
the body, or (b) support or sustain life, and whose fail- sonably expected to cause the failure of the life support
ure to perform when properly used in accordance device or system, or to affect its safety or effectiveness.
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

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