EE31594

Quiz 2
Oct 26, 2019

This text consists of 6 problems with point as indicated to total 100 points

Read through the entire exam before beginning.

Briefly explain major steps, include units, and write your final answers.

No credit will be given if no work is shown.

 Exam policies
No food allowed during exam
No books allowed (closed book exam)
Calculators allowed (But YOU MAY NOT USE THE FOLLOWING FUNCTIONS:
graphing, integrals, derivatives)
No communication of any kind is allowed. No use of cell phones, computers, or any devices
besides scientific calculators.

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1. (15 points) Consider the instrumentation amplifier shown below with a common-mode
input voltage of +5V (dc) and a differential input signal of 10 mVpp sine wave. Let (2R1)
= 1kΩ, R2 = 0.5MΩ, and R3 = R4 = 10kΩ.
a. (3 points) Find the voltage at output node, vO. Assume the op amps are ideal.
b. (5 points) What is the output voltage, vO if the gains of the op-amps are not ideal, i.e., A1
= 1000, A2 = 1000, A3 = 100? You can still assume that the input and output impedance of
the op amps are ideal.
c. (7 points). If R2 and R3 has ±5% tolerance (but R1 and R4 has 0% tolerance), what is the
worst case CMRR? Assume that R1 and R4 don’t have any component variations.
vI1
A1 R4

R3
R2
2R1 A3 vO
R2
R3
R4
A2
vI2
Fig. 1

Solution
a. Assuming perfect matching, no need to concern about the 5V common mode input. Since
the overall gain is given by: (1+R2/R1)∙(−R4/R3) = 1001∙(1) = −1001V/V, the output voltage
vO = 0.01Vpp × 1001 = 10.01Vpp sine wave (sign inverted)
b. G1 = (1+R2/R1)/(1+(1+R2/R2)/A) ≈ 500.25V/V (A = 1,000), G2 = −R2/R1(1+(1+R2/R1)/A)
≈ 0.98V/V (A = 100), thus the gain is degraded from 1001 to 490.245V/V. vO = 0.01Vpp ×
490.245 = 4.90245Vpp sine wave (sign inverted)
c. The given structure has the common mode voltage tolerance as shown in Fig. 1S. Because
the same potential, vi,cm is applied to the virtual ground nodes, there’s no current through
2R1, consequently there’s no common mode output signal even though R2 has some
deviations. Therefore, G1,cm = 0, CMRR1 = ∞

A1 R4

R3 +ΔR3
R2
Vi,cm 2R1 i=0 A3 vO
R2
R3 -ΔR3
R4
A2

Fig. 1S.1
On the other hand, if there are the deviation on R3 in opposite direction as shown in Fig. 1S,
the difference amplifier amplifies the common mode signal. That is, if R3 in the top and
bottom are 10.5kΩ and 9.95kΩ, respectively, G2,cm = 2×0.5kΩ/10k = 0.1V/V. Thus, CMRR2
= 20log10(1001/0.1) ≈ 80 dB, overall CMRR at the worst case is CMRR1||CMRR2 = 80dB
2
2. (10 points) Consider the Superdiode circuit shown below, with R = 1kΩ. For vI = 10mV,
1V, −1V, what are the voltages that result at the rectifier output and at the output of the op
amp? Assume the op amp is ideal and that its output saturates ±12V. The diode has a 0.7V
drop at 1mA current.

vI
vA

vO
R

Fig. 2

Solution
See Exercise 3.24
When vI = 10mV, vO = 10mV and vA = 0.59V because ID = 10mV/1kΩ = 10μA and the
voltage drop across the diode is 0.7V – 2.3VTlog(1mA/10μA) ≈ 0.59V
When vI = 1V, vO = 1V and vA = 1.7V because ID = 1mA (1V/1kΩ)
When vI = −1V, vO = 0V and vA = −12V because the diode is turned-off and the loop around
the op amp is not formed, of the op amp is saturated.

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3. (20 points) Assume the op amps are ideal and the diode D1 and D2 has a finite voltage drop
(VD1 = VD2 = 0.7V).
a. (10 points) Draw the voltage transfer characteristic (VTC) of vI vs. v1
b. (5 points) Given the values of R1 = 3.24kΩ, R2 = 10.2kΩ, R3 = 20kΩ, and R4 = 20kΩ, find
peak output voltage (vO). Assume that this circuit is excited by Vp = 2V and C is very large.
c. (5 points) How is the VTC of vI vs. v1 changed if the polarities of D1 and D2 are reversed?
R2
C
D1
R4
R1
vI R3

D2 vO
v1

Fig. 3

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Solution
a. Please refer to the 3.81 in the problems.
R2 R2

D1
D1

R1 R1
vI vI
vI/R1 D2 D2
v1 v1

(a) (b)
Fig. 3S.1

If vI > 0, i.e., the positive voltage is applied to the inverting node of the op amp, the output
of the op amp becomes negative. Thus, D1 is turned-on and D2 is turned-off as shown in Fig.
3S.1 (a). The current by vI (vI/R1) is absorbed by the output of the amp (0 output impedance)
and cannot make any potential changes at the output. Thus, v1 = 0
If vI <0, i.e., the negative voltage is applied to the inverting node of the op amp, the output
of the op amp becomes positive. Thus, D1 is turned-off and D2 is turned-on as shown in Fig.
3S.1(b). Thus, vI <0, v1= −R2/R1vI (Inverting configuration). Therefore, VTC of v1 vs. vI is
given as follows.
Slope:~-R2/R1 v1

vI

b. The overall gain is (−R2/R1)∙(−R4/R3) and the capacitance can be ignored since it is very
big. Therefore, ~6.3V
c. Need to perform the same task with Fig. 3S.2. The noninverting is formed when vI > 0.
R2

D1

R1
vI

D2
v1

Fig. 3S.2

v1

vI

Slope:~-R2/R1

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4. (20 points) Fig. 4(a) shows a voltage doubler consisting of clamping circuit and peak
detector. The clamping circuit boosts the input sinusoidal (e.g., Vp + Vp, if the amplitude of
the sinusoid is Vp) and then, the peak detector catches the peak of the boosted voltage. Fig.
4(b) shows a Dickson multiplier consisting of diodes and capacitors, basically operating with
the same principles of the voltage doubler. The difference are 1) the input is a dc voltage
(indicated as a battery) and 2) turn-on/off of the diodes are governed by the clock signals Φ1
and Φ2 where there’s no overlapping (it means there no high simultaneously as shown
below). Assume that the amplitude of pulses (Φ1 and Φ2) are large enough to turn on diodes.
a. (5 points) Draw the time-domain waveform of V1 and vO of the Dickson multiplier in the
steady-state. Assume that there is a BIG load resistor and ignore the diode drops.
b. (15 points) If the multiple of the Dickson multiplier are cascaded (let’s say n, currently
there are 2 stages in Fig. 4(b)), what is the output of the n-stage Dickson multiplier? Assume
that there’s a BIG load resistor and ignore the diode drops.

Clamping Peak
Circuit Detector
D2
+
C1
V D1 C2 vO

(a)
D1 V1 D2
+

vI C1 C2 vO

Φ1
Φ2

High
Φ1
Ground
Φ2 Low
Ground
(b)

Solution
a. The operation is shown below.

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High
Φ1
Ground
Φ2 Low
Ground

Vin + 2VHigh
VO
V1
Vin + VHigh
b. Vo = Vin + nVhigh

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5. (15 points) Consider a peak rectifier fed by a 60-Hz sinusoid having a peak value Vp =
100V. Let the load resistance R = 10 kΩ.
a. (5 points) Find the value of the capacitance C that will result in a peak-to-peak ripple of
2V.
b. (5 points) Calculate the fraction of the cycle during which the diode is conducting.
c. (5 points) Calculate the average and peak values of the diode current.

+
V C vO

Fig. 5

Solution
Please refer to the Example 3.8
a. C = Vp/(Vr·f·R) = 100/(2×60×10×103) ≈ 83.3μF
b. ωΔt = √(2×2/100) = 0.2rad or Δt = 1.06ms
c. iD,av = 10(1+π√(2×100/2) = 324mA, iD,max = 10(1+2π√(2×100/2) = 638mA

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6. (20 points) This problem is about the design of a regulated power supply. Fig. 6(a) shows
the topology of the chosen regulated power supply where a center-tapped transformer
provides a full wave rectification with the diode D1 and D2 and then the regulated supply is
formed by using a Zener diode. Fig. 6 (b) shows a part of the datasheet for the diodes, D1
and D2 (1N4148). RISO is usually a very large resistance, you can ignore in the problem.
a. (4 points) What is the proper turn ratio, n (integer) of the center-tapped transformer to
protect the diodes, D1 and D2? Justify your answer. Hint: a rule of thumb is that at least 3
time larger reverse voltage must be guaranteed.
b. (8 points) The shunt (zener) regulator must supply as large as 25mA current. What is the
proper value of R (must be larger than >100Ω)? Assume that the zener must consume at least
5mA and availability of 5.1V zener diodes having rZ = 10Ω at Iz = 20mA, and the worst case
ripple is 0.5 V.
c. (8 points) When considering an allowable ripple, Vr = 0.5V, what is the proper value of C?
Justify your answer.
D1 R
n:1

+
C vO RL
Vac:
120Vrms@60Hz V
Nominal vO: 5V
D2 RISO

(a)

(b)
Fig. 6

Solution
a. The center-tapped transformer has PIV = 2vS – VD ≈ 2vS and the peak input amplitude (half
of the peak-to-peak voltage) =120√2 ≈ 170V, thus 340/n < PIV as shown in Fig. 6S.1

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Fig. 6S.1
If n = 14, 340/14 = 24.3V ≈ VR (=75V)/3. This value of n also develops ~12V across the
capacitor. Thus, if n ≥ 14, the diodes are fine but n ≤ 17 for the proper regulation.
b. Now, the problem is simplified into the Zener regulator as shown in Fig. 6S.2
vS R ripple: 0.5V
IZ,min = 5mA
+

C vO vO = 4.95V
RL

RISO

Fig. 6S.2
Given the parameters about the Zener: VZ = 5.1V and rZ = 10Ω at Iz = 20mA, VZ0 can be
calculated as follows. VZ0 = VZ – IZ∙rZ = 5.1V – 0.02×10 = 4.9V
In the regulator, the Zener must consume at least 5mA (IZmin = 5mA), thus VZ,min = 4.9 + 10×
0.005 = 4.95V, which is the minimum output voltage as shown in Fig. 6S.2 (If vO < 4.95V,
IZ < 5mA). One thing to note is that the maximum vO = 5.5V (0.5V ripple), IZ must not exceed
60mA (10×0.06 + 4.9V).
Thus, the voltage across R is given as: ~12 (n = 14) − 0.7 − Vr (0.5) = 10.8V. In addition, the
IR = 30mA because of IL, max = 25mA and IZ = 5mA. Therefore, R = (10.8 − 4.95)/30mA =
195Ω or smaller than that. One more thing to check is that R = (170/n – 1.2)/85mA < 100Ω,
therefore, n < 18 (R ≈ 96Ω if n = 18)

Fig. 6S.3
c. As shown in Fig. 6S.3, Vr ≈ I/fC (C ≈ I/(f·Vr)), IL,max = 25mA and IZ = 5mA, Vr = 0.5V, f =
120Hz (full-wave rectifier), thus C = 500μF or larger if you set I > 30mA.

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