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    4.3.2 ADC Evaluation Board AD9228 Features

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    Manjeer Majumder
    The document describes an evaluation board for the AD9228 four-channel analog-to-digital converter (ADC). Key features of the ADC evaluation board include: it can operate at up to 65 megasamples per second with 12-bit or 10-bit digital output in various formats; it has excellent linearity; and it consumes 119 milliwatts of power per channel. An adapter board was created to connect the evaluation board to Spartan3 and Virtex4 FPGA boards due to incompatible connectors. The Spartan3 FPGA board features a Xilinx FPGA that supports high clock speeds and standards like LVDS, and has been configured to interface with the LVDS outputs of the ADC board.

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    4.3.2 ADC Evaluation Board AD9228 Features

    Uploaded by

    Manjeer Majumder
    28 views3 pages
    The document describes an evaluation board for the AD9228 four-channel analog-to-digital converter (ADC). Key features of the ADC evaluation board include: it can operate at up to 65 megasamples per second with 12-bit or 10-bit digital output in various formats; it has excellent linearity; and it consumes 119 milliwatts of power per channel. An adapter board was created to connect the evaluation board to Spartan3 and Virtex4 FPGA boards due to incompatible connectors. The Spartan3 FPGA board features a Xilinx FPGA that supports high clock speeds and standards like LVDS, and has been configured to interface with the LVDS outputs of the ADC board.

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    The document describes an evaluation board for the AD9228 four-channel analog-to-digital converter (ADC). Key features of the ADC evaluation board include: it can operate at up to 65 megasamples per second with 12-bit or 10-bit digital output in various formats; it has excellent linearity; and it consumes 119 milliwatts of power per channel. An adapter board was created to connect the evaluation board to Spartan3 and Virtex4 FPGA boards due to incompatible connectors. The Spartan3 FPGA board features a Xilinx FPGA that supports high clock speeds and standards like LVDS, and has been configured to interface with the LVDS outputs of the ADC board.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    28 views3 pages

    4.3.2 ADC Evaluation Board AD9228 Features

    Uploaded by

    Manjeer Majumder
    The document describes an evaluation board for the AD9228 four-channel analog-to-digital converter (ADC). Key features of the ADC evaluation board include: it can operate at up to 65 megasamples per second with 12-bit or 10-bit digital output in various formats; it has excellent linearity; and it consumes 119 milliwatts of power per channel. An adapter board was created to connect the evaluation board to Spartan3 and Virtex4 FPGA boards due to incompatible connectors. The Spartan3 FPGA board features a Xilinx FPGA that supports high clock speeds and standards like LVDS, and has been configured to interface with the LVDS outputs of the ADC board.

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    4.3.

    2 ADC evaluation board AD9228 features [11]:

     It is a high speed four channel programmable ADC evaluation board.


     It is programmable with 12 bit or 10 bit digital data output in MSB or LSB first frame
    format through an external SPI (Serial peripheral interface) slow control.
     Serial data, data and frame clocks are in LVDS I/O type.
     Excellent linearity with DNL error maximum +/- 0.3LSB.
     Supports sampling rate up to 65 MSPS.
     Supports DDR operation up to 390 MHz for high speed data acquisition.
     1.8V power supply operation.
     Consumes 119 mW power per channel at 65 MSPS.

    4.3.2.1 Interface standards for ADC evaluation board AD9228:

    The ADC board analog inputs also have the LVDS standard. Although the ADC chip AD9228 is
    having differential standard inputs for clock as well as analog inputs, the evaluation board is
    provided with single-ended to differential converters for each of the differential inputs. The
    digital outputs however are in LVDS format, and provide serial data corresponding to each
    analog channel.

    4.3.2.2 ADC board default settings:

     Data output is in 12 bits, MSB first output frame format.


     Test pattern output is “100000000000” binary output, in the absence of analog input
    signal.

    ADC board has TYCO make PCB mount connector with part no. 6469169-1 for I/O interfacing
    which is difficult to interface with the FPGA kit I/O connector. For this an adaptor board was
    made with a mating connector to ADC on one side and a mating connector to FPGA board (for
    both Spartan3 & Virtex4 kit) on other side. Adaptor board is a double sided PTH type PCB board
    with FR4 material and dimensions 90 mm X 40 mm.
    4.3.3 Spartan3 FPGA board features [12]:

     Sparan3 device XC3S200FT256 fabricated with 90 nm CMOS technology, Supporting


    system clock rate upto 326 MHz.
     JTAG logic compatible with IEEE 1149.1/1532.
     Supports DDR mode (I/O blocks supports DDR output operation).
     Maximum up to 4 DCM blocks for clock skew elimination and frequency synthesis.
     Up to 216 Kbits of total block RAM in XC3S200FT256 package.
     Up to 30 Kbits total distributed RAM in XC3S200FT256 package.
     Upto 173 user I/Os and 76 differential I/O pairs.
     A total of 12 dedicated multipliers in XC3S200FT256 package.

    4.3.3.1 Interface standards of spartan3 FPGA board:

    Xilinx Spartan3 device XC3S200 package FT256 has been used equipped with 173 user I/O and
    76 differential I/O standards which can be configured to support any of the differential standards.
    Supported standards are LDT_25, LVDS_25, BLVDS_25, LVDSEXT_25, ULVDS_25, and
    RSDS_25. Similarly many other single-ended standards like GTL, GTLP, HSTL_I,
    LVCMOS15, LVCMOS33, LVCMOS25 LVTTL etc. In this project work, ports have been
    configured for LVDS_25 to interface the ADC board differential serial outputs whose details are
    given in next chapter. Other ports have been configured with single ended LVTTL standard.

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