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R.M.K ENGINEERING COLLEGE
Linear Integrated Circuits
(EC8453)

Department : ECE
Batch/Year : 2019-2023
Created by :Dr.V.Sumitra
Dr.Jasmine Hepzhibha
Mrs.S.Rosaline
Mr.R.SathyaVignesh

Date : 3.4.2021
Table of Contents
S.No Contents Page
Number
1 Course Objectives 7
2 Pre Requisites 9
3 Syllabus 11
4 Course outcomes 14
5 CO- PO/PSO Mapping 16
6 Unit 3 – Analog Multiplier and PLL 19

6.1 Lecture Plan 20

6.2 Activity based learning 21

6.3 Lecture Notes 23

3.1 Analog Multipliers 25

3.2 Terminologies associated voltage of the 25

multiplier characteristics

3.3 Analog multiplier using an Emitter 30

coupled Transistor pair

3.4 Gilbert Multiplier cell 32

3.5 Variable Trans conductance Technique 35

3.6 Analog Multiplier ICs 36

3.7 Applications of Multiplier Ics: 38

3.8 Operation of Phase Locked Loop 45

Table of Contents
S.No Contents Page
889 Number
3.9 Voltage Controlled Oscillator 54
3.10 Monolithic PLL IC 565 applications 57
3.11 Monolithic PLL IC 565 applications: 60

6.4 Assignments 65

6.5 Part A Questions & Answers 66

6.6 Part B Questions 71

6.7 Supportive online Certification courses 72

6.8 Real time Applications in day to day life and to 78

Industry
6.9 Contents beyond the Syllabus 82

7 Assessment Schedule 85

8 Prescribed Text Books & Reference Books 87

9 Mini Project suggestions 89

Course Objectives
Subject Name: Linear Integrated Circuits
Subject Code: EC8453
EC8453 LINEAR INTEGRATED CIRCUITS
COURSE OBJECTIVES

The student should be made to:

 To introduce the basic building blocks of linear integrated circuits

 To learn the linear and non-linear applications of operational

amplifiers

 To introduce the theory and applications of analog multipliers and

PLL

 To learn the theory of ADC and DAC

 To introduce the concepts of waveform generation and introduce

some special function ICs
Pre Requisites

Subject Name: Linear Integrated Circuits

Subject Code: EC8453

Subject Name : Engineering Mathematics I
Subject Code : MA8151
Semester :1
Reason : For mathematical analysis

Subject Name: Physics for Electronics Engineering

Subject Code : PH8252
Semester :2
Reason : Students should be familiar with the essential principles of
semiconductor devices

Subject Name : Circuit Analysis

Subject Code : EC8251
Semester :2
Reason : Students should be familiar with the analysis of different
circuits and applying basic theorem such as Thevenin’s
theorem, Principle of Superposition etc

Subject Name: Electronic Devices

Subject Code : EC8252
Semester :2
Reason : Knowledge about basic Electronics Components

Subject Name: Electronic Circuits - I

Subject Code : EC8351
Semester :3
Reason : Students should be familiar with various biasing techniques
and the analysis of Electronic Circuits
Syllabus

Subject Name: Linear Integrated Circuits

Subject Code: EC8453

EC8453 LINEAR INTEGRATED CIRCUITS LTPC
3003

UNIT I BASICS OF OPERATIONAL AMPLIFIERS 9

Current mirror and current sources, Current sources as active loads,

Voltage sources, Voltage References, BJT Differential amplifier with
active loads, Basic information about op-amps – Ideal Operational
Amplifier - General operational amplifier stages -and internal circuit
diagrams of IC 741, DC and AC performance characteristics, slew rate,
Open and closed loop configurations – JFET Operational Amplifiers –
LF155 and TL082.

UNIT II APPLICATIONS OF OPERATIONAL AMPLIFIER 9

Sign Changer, Scale Changer, Phase Shift Circuits, Voltage Follower, V-

to-I and I-to-V converters, adder, subtractor, Instrumentation amplifier,
Integrator, Differentiator, Logarithmic amplifier, Antilogarithmic
amplifier, Comparators, Schmitt trigger, Precision rectifier, peak
detector, clipper and clamper, Low-pass, high-pass and band-pass
Butterworth filters.

UNIT III ANALOG MULTIPLIER AND PLL 9

Analog Multiplier using Emitter Coupled Transistor Pair - Gilbert Multiplier

cell – Variable transconductance technique, analog multiplier ICs and
their applications, Operation of the basic PLL, Closed loop analysis,
Voltage controlled oscillator, Monolithic PLL IC 565, application of PLL for
AM detection, FM detection, FSK modulation and demodulation and
Frequency synthesizing and clock synchronisation.
EC8453 LINEAR INTEGRATED CIRCUITS LTPC
3003

UNIT IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG

CONVERTERS 9

Analog and Digital Data Conversions, D/A converter – specifications -

weighted resistor type, R-2R Ladder type, Voltage Mode and Current-
Mode R - 2R Ladder types - switches for D/A converters, high speed
sample-and-hold circuits, A/D Converters – specifications - Flash type -
Successive Approximation type - Single Slope type – Dual Slope type -
A/D Converter using Voltage-to-Time Conversion - Over-sampling A/D
Converters, Sigma – Delta converters.

UNIT V WAVEFORM GENERATORS AND SPECIAL

FUNCTION ICS 9

Sine-wave generators, Multivibrators and Triangular wave generator,

Saw-tooth wave generator, ICL8038 function generator, Timer IC 555,
IC Voltage regulators – Three terminal fixed and adjustable voltage
regulators - IC 723 general purpose regulator - Monolithic switching
regulator, Low Drop – Out(LDO) Regulators - Switched capacitor filter IC
MF10, Frequency to Voltage and Voltage to Frequency converters, Audio
Power amplifier, Video Amplifier, Isolation Amplifier, Optocouplers and
fibre optic IC.

TOTAL: 45 PERIODS
Course Outcomes
At the end of the course, the student should be able to:

 Design basic building blocks of Op-amp.

 Design Linear and non linear applications of Op-amp.

 Use analog multiplier IC and PLL for signal processing applications.

 Design ADC and DAC using Op-amp.

 Design Waveform generator circuits using Op-amp and IC555 timer.

 Analyze special function ICs.

Course Outcomes and Blooms K Level

Course Statement Blooms

Outcomes K_Level

CO1 Design basic building blocks of Op-amp K4

CO2 Design Linear and non linear applications of K4

Op-amp.

CO3 Use analog multiplier IC and PLL for signal K3

processing applications.

CO4 Design ADC and DAC using Op-amp. K4

CO5 Design Waveform generator circuits using Op- K3

amp and IC555 timer.

CO6 Analyze special function ICs. K3

CO-PO/PSO mapping
Program Outcomes PSO
Course Level of PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
Outcome Outcome 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
ADC
K3 K4 K4 K5 K3/ A3 A2 A3 A3 A3 A3 A2 K3 K3 K3
K5/
K6

CO1 K4 3 2 2 2 3 1 - - - - 1 1 3 3 3

CO2 K4 3 3 3 2 3 1 - - - - 1 1 3 3 3

CO3 K3 3 2 2 1 3 1 - - - - 1 1 3 3 3

CO4 K4 3 3 3 2 3 1 - - - - 1 1 3 3 3

CO5 K3 3 2 2 1 3 1 - - - - 1 1 3 3 3
CO-PO/PSO mapping

CO6 K3 3 2 2 1 3 1 - - - - 1 1 3 3 3

Average 3 2 2 2 3 1 - - - - 1 1 3 3 3
CO
Mapping
CO-PO/PSO mapping
After Successful Completion of the course, the students
should be able to
Course Statement Highest
Outcomes Cognitive
Level
CO1 Design basic building blocks of Op-amp K4

CO2 Design Linear and non linear applications of Op-amp. K4

CO3 Use analog multiplier IC and PLL for signal processing K3
applications.
CO4 Design ADC and DAC using Op-amp. K4

CO5 Design Waveform generator circuits using Op-amp K3

and IC555 timer.
CO6 Analyze special function ICs. K3
7.LECTURE PLAN
EC8453 LINEAR INTEGRATED CIRCUITS LTPC3003

UNIT III ANALOG MULTIPLIER AND PLL

S. Topic No. Propose Actual Pertain Taxonomy Mode

No of d date Lecture ing CO level of
. Peri Date Deliver
ods y

1 1 29.3.21 29.3.21
Analog Multiplier using
Emitter Coupled Transistor K2 MD1
Pair

2 Gilbert Multiplier cell 1 30.3.21 30.3.21 K2 MD1

3 1 31.3.21 31.3.21
Variable transconductance
CO3
technique, analog
K2 MD2
multiplier ICs and their
applications

4 1 1.4.21 1.4.21
Operation of the basic
K2 MD1
PLL, Closed loop analysis,
5 1 3.4.21 3.4.21
Voltage controlled
K2 MD1
oscillator

6 Monolithic PLL IC 565 1 5.4.21 5.4.21 K2 MD1&2

7 1 7.4.21 7.4.21
application of PLL for AM
K2 MD1
detection, FM detection

8 1 8.4.21 8.4.21
FSK modulation and
demodulation and
K2 MD1
Frequency synthesizing
and clock ynchronization.

9 Revision 1 9.4.21 9.4.21 K2 MD1

8.Activity based learning –UNIT III

1. Identify the ICs.

(a)

(b)

(c)

2. Identify the application of PLL:

.
8.Activity based learning –UNIT III

3. Name the functional blocks in the Phase locked loop block diagram:

4. Identify the circuit :

9.LECTURE NOTES
UNIT III
ANALOG MULTIPLIER AND PLL

3.1 Analog Multipliers:

A multiple produces an output V0which is proportional to the product of two inputs Vx and Vy.
V 0= KVxVy
where K is the scaling factor = (1/10) V-1.

There are various methods available for performing analog

multiplication. Four of such techniques, namely,
1. Logarithmic summing technique
2. Pulse height/width modulationTechnique
3. Variable trans conductance Technique
4. Multiplication using Gilbert cell and
5. Multiplication using variable trans conductance technique.
An actual multiplier has its output voltage V0defined by
where φx and φy are the offsets associated with signals Vx and Vy,ε is the error signal associated with K
and φ0is the offset voltage of the multiplier output.

3.2 Terminologies associated voltage of the multiplier characteristics:

Accuracy:
This specifies the derivation of the actual output from the ideal output, for any combination of X and Y
inputs falling within the permissible operating range of the multiplier.
Linearity:
This defines the accuracy of the multiplier. The Linearity Error can be defined as the maximum
absolute derivation of the error surface. This linearity error imposes a lower limit on the multiplier accuracy.

22
Fig 3.1 Linearity of multiplier

The figure shows the response of the output as a function of one input voltage Vx when the other Vy is assumed
constant.

It represents the maximum percentage derivation from the ideal straight line output. An error surface is formed by
plotting the output for different combinations of X and Y inputs.

23
Square Law Accuracy:

Square – law curve is obtained with the X and Y inputs connected together and applied with the same input signal.
The maximum derivation of the output voltage from an ideal square –law curve expresses the squaring mode
accuracy.

Fig 3.2 Squaring mode accuracy

Bandwidth:
The Bandwidth indicates the operating capability of an analog multiplier at higher frequency values. Small signal 3 dB
bandwidth defines the frequency f0at which the output reduces by 3dBfrom its low frequency value for a constant
input voltage. This is identified individually for the X and Y input channels normally.
The transconductance bandwidth represents the frequency at which the transconductance of the multiplier drops by
3dB of its low frequency value. This characteristic defines the application frequency ranges when used for phase
detection or AM detection.

24
Quadrant:
The quadrant defines the applicability of the circuit for bipolar signals at
its inputs. First – quadrant device accepts only positive input signals, the
two quadrant device accepts one bipolar signal and one uni polar signal
and the four quadrant device accepts two bipolar signals.
Logarithmic summing Technique:
This technique uses the relationship
lnVx + lnVy =ln(VxVy)
As shown in figure the input voltages Vx and Vy are converted to
their logarithmic equivalent, which are then added together by a
summer.
An antilogarithmic converter produces the output voltage of the
summer. The output is given by,Vz = ln-1 (ln(Vx Vy )) = Vx Vy .

Fig. 3.3 logarithmic summing method

The relationship between I0and VBEof the transistor is given by

(VBE /VT )
IC= I0e

It is found that the transistor follows the relationship very accurately in the range of 10nA to 100mA. Logarithmic
multiplier has low accuracy and high temperature instability. This method is applicable only to positive values of
Vx and Vy.

Limitation:
This type of multiplier is restricted to one quadrant operation only.
Pulse Height/ Width ModulationTechnique:

Fig.3.4 Pulse Height/ Width Modulation Technique

26
3.3 Analog multiplier using an Emitter coupled Transistorpair:

Fig.3.5 multiplier circuit using an emitter coupled pair

27
The dc transfer characteristics of the emitter – coupled pair is
shown in figure. It shows that the emitter coupled pair can be used as a
simple multiplier using this configuration.

When the differential input voltage V1 << VT,

IEE=K0 (V 2 -VBE)/2V
T
Substituting above eqn. , we get IC= K0V1(V2- VBE)/2VT

Fig. 3.6 DC Transfer characteristics of emitter coupled pair

The current IEE is the bias current for the emitter – coupled pair.
If the current IEE is made proportional to a second input signal V2, then

IEE =K0 (V2 - VBE)/2VT

Substituting above eqn. , we get

∆IC = K0V1 (V2 - VBE)/2VT

28
3.4 Gilbert Multipliercell:

The Gilbert multiplier cell is a modification of the emitter coupled cell and this allows four – quadrant multiplication.
Therefore, it forms the basis of most of the integrated circuit balanced Multipliers. Two cross- coupled emitter- coupled
pairs in series connection with an emitter coupled pair form the structure of the Gilbert multiplier cell.

Fig. 3.8 Gilbert multiplier cell

It consist of emitter coupled pair of transistors Q1 and Q2 in series with a

cross coupled emitter coupled transistor pair Q3 to Q6.
A constant source Iee is connected in the emitter circuit of Q1 and Q2 to
bias them.
Vx and Vy are two differential inputs which are to be multiplied together.
Due to symmetry in the cross coupled devices Iee gets equally divided
among various branches of the circuit and eliminates any common mode
shift in the output voltage Vo.

29
Fig. 3.7 A simple modulator using a differential amplifier
Analysis :
Assume all transistors are of same type
I1 = I3 + I4 , I2= I5 +I6 , Iee=I1+I2
Let gm(3,4) and gm(5,6) are variable Trans conductance of transistor pairs
Q3 ,Q4 and Q5 and Q6 respectively.

Where transconductance gm is given by Iee / Vt ,Vt- thermal equivalent

voltage

Current unbalance in the differential pairs of Q3, Q4 and Q5, Q6 are given by
I3-I4 = gm(3 4) Vx
. I5-I6 = gm(5 6) Vx

The differential output voltage is given by

Vo= ( I3 – I4) Rl - ( I5 – I6) Rl
Vo= Rl[ (I3-I4) –(I5 –I6)]
Substituting values of I3 – I4 and I5 - I6 we get
Vo=Rl [gm(3 4) Vx - gm(5 6) Vx]

But gm(3 4) = I1 / Vt and gm(5 6) = I2/ Vt

30
Vo= Rl[I1 / Vt * Vx - I2/ Vt * Vx]
Vo= Rl Vx / Vt[I1 – I2]

Re is very large I1 Re >> Vt and I2 Re >> Vt

I1 – I2 = Vy / Re

V0 = Rl Vx Vy / Vt Re

Let K= Rl / Re Vt where k is a constant

Vo= k Vx Vy
Output is directly proportional to the product of two inputs Vx and Vy
Limitations :
Gilbert cell works well when Vx < Vy

31
3.5 Variable Transconductance Technique:

The variable transconductance technique makes use of the dependence characteristic of the transistor transconductance
parameter on the emitter current bias applied. Asimple
differential circuit arrangement depicting the principle is shown in figure.

Fig. 3.9 Differential stage of the Tran conductance multiplier

32
The relationship betweenV0and Vx.is given by
V0=gmRLVXwhere
gm= IEE/VT
is the transconductance of the s t a g e .

Application of a second input Vyto the reference current source of the differential amplifier can vary gm.

Thus, if REIEE>>VBE, the bias voltage Vyi s related toI EE by t he relation Vy=IEER E.
Then, the overall voltage transfer expression is given by

V0= gmRLVx= (Vy/VTRE)VxRL

=V V R V R
x y L/ T E

3.6 Analog MultiplierICs

Analog multiplier is a circuit whose output voltage at any instant is proportional to the product of instantaneous value of two
individual input voltages.
Important applications of these multipliers are multiplication, division, squaring and square – rooting of signals, modulation
and d e m o d u l a t i o n .
These analog multipliers are available as integrated circuits consisting of op-amps and other circuit elements. The
Schematic of a typical analog multiplier, namely, AD633 is shown in figure.

Fig. 3.10 Multiplier IC and its symbol

33
 The AD633 multiplier is a four – quadrant analogmultiplier.
 It possesses high input impedance; this characteristic makes the
loading effect on the signal sourcenegligible.
 It can operate with supply voltages ranging from ±18V.The
 IC does not require externalc o m p o ne nt s .
 Thetypicalrangeofthetwoinputsignalsis±10V.

Fig. 3.11 Multiplier IC symbol

34
Schematic representation of a multiplier:
The schematic representation of an analog multiplier is shown in figure. The output V0is the
product of the two inputs Vxand Vyis divided by a reference voltage Vref. Normally, the reference voltage
Vref is internally set to 10V. Therefore, V0=VxVy/10.Inother words, the
basic input – output relationship can be defined by
KVx Vy when K = 1/10, a constant.
Thus for peak input voltages of 10V, the peak magnitude of output
voltage is 1/10 *10 *10 =10V.
Thus, it can be noted that, as long as Vx < 10V and Vy < 10V, the
multiplier output will notsaturate.
Multiplier quadrants:
The transfer characteristics of a typical four-quadrant multiplier are shown in figure. Both the inputs can be
positive or negative to obtain the corresponding output as shown in the transfer characteristics.

3.7 Applications of Multiplier Ics:

The multiplier ICs are used for the following purposes:

 Voltage Squarer
 Frequency doublers
 Voltage divider
 Square rooter
 Phase angle detector
 Rectifier

Fig.3.11 Transfer characteristics of a typical four-quadrant multiplier

35
Voltage Squarer:

Figure shows the multiplier ICconnected as a squaring circuit. The inputs can be positive or negative,
represented by any corresponding voltage level between 0 and 10V. The input voltageVi to be squared is simply
connected to both the input terminals, and hence we have, Vx = Vy = Vi and the output is V0 = KVi2. The circuit thus performs the

squaringoperation.Thisapplicationcanbeextendedforfrequencydoublingapplications.

Fig. 3.12 voltage squarer circuit

Frequency doublers:

Figure shows the squaring circuit connected for frequency doubling operation. A
sine-wave signal Vi has a peak amplitude of Avand frequency of f Hz.
Then, the output voltage of the doublers circuit is given by

Vo=Av sin2*3.14*ft*Avsin2*3.14*ft/10=Av2sin22*3.14*ft
=Av2/20(1−cos4)

Assuming a peak amplitude Avof 5V and frequency f of 10KHz,

V0=1.25–1.25 cos2 20000) t.

The first term represents the dc term of 1.25V peak amplitude. The input and
output waveforms are shown in figure. The output waveforms ripple with twice
the input frequency in the rectified output of the input signal. This forms the
principle of application of analog multiplier as rectifier of ac signals.

36
Fig. 3.13 circuit diagram

Fig. 3.14 input –output waveform of frequency doubler

The dc component of output V0 can be removed by connecting a 1µF coupling capacitor between the output
terminal and a load resistor, across which the output can be observed

37
.
Voltage Divider:

In voltage divider circuit the division is achieved by connecting the

multiplier in the feedback loop of an op-amp.
The voltages Vden and Vnum represent the two input voltages, Vdm
forms one input of the multiplier, and output of op-amp VoA forms the
second input.
The output VOA forms the second input. The output VOM of the
multiplier is connected back of op- amp in the feedback loop. Then the
characteristic operation of the multiplier gives
Vom= KVOAVdm (1)

As shown in figure, no input signal current can flow into the inverting input terminal of op-amp,
which is at virtual ground.

Therefore, at the junction a, i1+i2=0,

the current i1= Vnum/ R,
where R is the input resistance
and the current i2= Vom/R.
With virtual ground existing at a,
V1+V2=Vnum/R +Vom / R
KVOAVd= -Vnum
KVOAVd=-Vnum/KVden

Where
Vnum andVden are the numerator and denominator voltages respectively.
Therefore, the voltage division operation is achieved.

Vnum can be a positive or negative voltage and Vden can have only positive values to ensure
negative feedback.

When Vdm is changed, the gain 10/Vdm changes, and this feature is used in automatic gain control
(AGC)circuits.

38
Fig. 3.15 Divider circuit

SquareRooter:

The divider voltage can be used to find the square root of a signal by connecting both
inputs of the multiplier to the output of the op-amp. Substituting equal in magnitude but opposite in polarity (with respect to
ground) to Vi.

But we know that Vomi s one- term (Scale factor) of V0* V0or -Vi = Vom = V2/10

Solving for V0and eliminating √-1 yields. V0= √10|Vi|

Eqn. states that V0 equals the square root of 10 times the absolute
magnitude of Vi.

39
The input voltage Vi must be negative, or else, the op-amp saturates.
The range of Vi is between -1 and -10V. Voltages less than -1V will cause inaccuracies in the result.
The diode prevents negative saturation for positive polarity Vi signals. For positive values of Vi the diode connections are reversed.

Phase Angle detector:

The multiplier configured for phase angle detection measurement is shown in figure.

When twosine-waves of the same frequency are applied to the inputs of the multiplier, the output V0has adc component and an
ACcomponent.

The trigonometric identity shows that Sin A sin B =1/2 (cos (A-B) – cos (A+B)).
When the two frequencies are equal, but with different phase angles,

e.g. A=2πft +θ for signal Vxand B= 2πft f or signal Vy,

then using the identity
[sin (2ft+ )][sin2ft)]=1/2[cos -cos(4ft+ )]=1/2(dc- the double frequency term)
Therefore, when the two input signals Vx and Vy are applied to the multiplier,
V0 (dc)is given by

Where Vxp and Vyp are the peak voltage amplitudes of the signals Vxand Vy.

Thus, the output V0(dc)depends on the factor cos θ.

A dc voltmeter can be calibrated as a phase angle meter when the product of Vxpand Vypis made equal to 20.
Then, a (0-1) V range dc voltmeter candirectly read cos θ, with the meter calibrated directly in degrees from a cosine table.
The input and output waveforms are shown infigure.

Then the above eqn becomes V0 (dc)= cos θ, if we make the product Vxp Vyp= 20 or in other words, Vxp – Vyp=4 . 4 7 V.

40
Fig. 3.16 Phase angle measurement circuit diagram

Fig. 3.17 input- output waveforms of phase angle detector

41
3.8 Operation of Basic Phase LockedLoop

Fig. 3.18 Block diagram of PLL

The PLL consists of

i) Phase detector
ii) LPF
iii) VCO.
The phase detector or comparator compares the input frequency fIN with feedback f requencyf OUT.
The output of the phase detector is proportional to the phase difference between fin& fOUT.
 The output of the phase detector is a dc voltage & therefore is often referred to as the error voltage.
 The output of the phase detector is then applied to the LPF, which removes the high frequency noise and produces a dc level.
This dc level in turn, is input to the VCO.
 The output frequency of VCO is directly proportional to the dc level. The VCO frequency is compared with input frequency
and adjusted until it is equal to the inputfrequencies.
 PLL goes through 3 states,

i) free running
ii) Capture
iii) Phase lock.

42
Before the input is applied, the PLL is in free running state. Once the input frequency is applied the VCO
frequency starts to change and PLL is said to be in the capture mode. The VCO frequency continuous to change until it
equals the input frequency and the PLL is in phase lock mode. When Phase locked, the loop tracks any change in the input

frequency through its repetitive a c t i o n .

Ifan input signal vsof frequency fsis applied to the PLL, the phase detector compares the phase and frequency
of the incoming signal to that of the output voof the VCO. Ifthe two signals differ in frequenc yo fthe in comings

ignalto thatofthe outputvoof the VCO.

The phase detector is basically a multiplier and produces the sum (fs+ fo) and difference (fs- fo)

components at its output.

The high frequency component (fs+ fo) is removed by the low pass filter and the difference frequency

component is amplified then applied as control voltage vcto VCO.

The signal vcshifts the VCO frequency in a direction to reduce the frequency difference between fsand fo. Once
this action starts, we say that the signal is in the capture range. The VCO continues to change frequency till its output frequency is
exactly the same as the input signal frequency. The circuit is then said to be locked. Once locked, the output frequency foof VCO
is identical to fs except for a finite phase difference φ. This phase difference φ generates a corrective control voltage vc to shift the
VCO frequency from f0to fs and thereby maintain the lock. Once locked, PLL tracks the frequency changes of the input signal.
Thus, a PLL goes through three stages
(i) free running,
(ii) capture and
(iii) locked or tracking.
Capture range:
The range of frequencies over which the PLL can acquire lock with an inputs signal is called the capture range.

This parameter is also expressed as percentage of fo.

Pull-in time:

The total time taken by the PLL to establish lock is called pull-in time. This depends on the initial phase and frequency difference

between the two signals as well as on the overall loop gain and loop filter characteristics.

43
PhaseDetector

Phase detector compares the input frequency and VCO frequency and
generates DC voltage i.e., proportional to the phase difference between the two frequencies. Depending on
whether the analog/digital phase detector is used, the PLL is called either an analog/digital type
respectively. Even though most monolithic PLL integrated circuits use analog phase detectors.
Ex for Analog: Double-balanced mixer
Ex for Digital: Ex-OR, Edge trigger, monolithic Phase detector.
Ex-OR PhaseDetector:

This uses an exclusive OR gate. The output of the Ex-OR gate is high only
when fIN or fOUT is high.
The DC output voltage of the Ex-OR phase detector is a function of the
phase difference between its two outputs.

The maximum dc output voltage occurs when the phase difference is Π

radians or 180 degrees. The slope of the curve between 0 or Π radians is the conversion gain kp of the
phase detector for eg; if the Ex-OR gate uses a supply voltage
Vcc = 5V,
the conversion gain Kp is
Kp=5/3.14=1.59 rad

Advantages of Edge Triggered Phase Detector over Ex-OR are

The dc output voltage is linear over 2Π radians or 360 degrees, but in Ex-OR it is Π radians or
180degrees.
Better Capture, tracking & locking characteristics.
Edge triggered type of phase detector using RS Flip – Flop. It is formed from a pair of cross coupled NOR
gates.
RS FF is triggered, i.e., the output of the detector changes its logic state on the positive edge of the inputs
fIN & fOUT

Monolithic Phasedetector:

It consists of 2 digital phase detector, a charge pump and an amplifier.

Phase detector 1 is used in applications that require zero frequency and phase difference at lock.

Phase detector 2, if quadrature lock is desired, when detector 1 is used in the main loop, detector
can also be used to indicate whether the main loop is in lock or out of lock.

44
Low Pass Filter:

The function of the LPF is to remove the high frequency components in the output of the phase
detector and to remove the high frequency noise. LPF controls the characteristics of the phase locked loop. i.e.,
capture range, lock ranges,bandwidth
Lock range(Trackingrange):

The lock range is defined as the range of frequencies over which the PLL systemfollows the changes in
the input frequency IN
.Capture range:
Capture range is the frequency range in which the PLL acquires phase lock. Capture range is always
smaller than the lock range.

Filter Bandwidth:

Filter Bandwidth is reduced, its response time increases. However reduced Bandwidth reduces the
capture range of the PLL. Reduced Bandwidth helps to keep the loop in lock through momentary losses of signal and also
minimizes n o i s e .

3 . 9 V o l t a g e C o n t r o l l e d O s c i l l a t o r (VCO):

The third section of PLL is the VCO; it generates an output frequency

that is directly proportional to its input voltage. The maximum output frequency of NE/SE
566 is 500 Khz.
F e e d b a c k p a t h a n d o p t i o n a l divider:

Most PLLs also include a divider between the oscillator and the feedback input
t o t h e p h a s e d e t e c t o r t o p r o d u c e a f r e q u e n c y s y n t h e s i z e r. A p r o g r a m m a b l e d i v i d e r i s
p a r t i c u l a r l y u s e f u l i n r a d i o Tr a n s m i t t e r a p p l i c a t i o n s , s i n c e a l a r g e n u m b e r o f t r a n s m i t
frequencies can be produced from a single stable, accurate, but expensive, quartz
c r y s t a l – c o n t r o l l e d r e f e r e n c e oscillator.

Some PLLs also include a divider between the reference clock and the reference input to the
p h a s e d e t e c t o r.

45
Feedback path and optional divider:

If this divider divides by M, it allows the VCO to multiply the reference frequency by N/M.
It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency
may be constrained by other issues, and then the reference divider is u s e f u l .
Frequency multiplication in a sense can also be attained by locking the PLL to the 'N'th
harmonic of the signal.

The equations governing a phase-locked loop with an analog multiplier as the

phase detector may be derived as follows.

Let the input to the phase detector be x c ( t ) and the output of the voltage- controlled
oscillator (VCO) is x r ( t ) with frequency ω r ( t ),

then the output of the phase detector x m ( t ) is given by

The VCO frequency may be written as a function of the VCO input y( t ) as where g v is the sensitivity of the
VCO and is expressed in Hz /V.

Hence the VCO output takes the form

where

The loop filter receives this signal as input and produces an output
x f ( t ) = F filter ( x m ( t ))

Where Filter is the operator representing the loop filter transformation .

When the loop is closed, the output from the loop filter becomes the input to the VCO
thus y ( t ) = x f ( t ) = F filter ( x m ( t ))

We can deduce how the PLL reacts to a sinusoidal input signal:

xc ( t ) = Ac sin(ω ct ).

46
We can deduce how the PLL reacts to a sinusoidal input signal:
xc(t) =Acsin(ωct).
The output of the phase detector then is:

This can be rewritten into sum and difference components using

trigonometric identities:

Control System Analysis/ Closed Loop Analysis OfPLL

Phase locked loops can also be analyzed as control systems by applying the Laplace transform. The loop
response can be written as:

Where

Θo is the output phase in radians

Θi is the input phase in radians
Kp is the phase detector gain in volts per radian
Kv is the VCO gain in radians per volt-second
F(s) is the loop filter transfer function(dimensionless)

47
The simplest filter is a one-pole RC circuit. The loop transfer function in
this case is:

The loop response becomes:

This is the form of a classic harmonic oscillator. The denominator can be

related to that of a second order system:

Where
ζ is the damping factor
ωn is the natural frequency of the loop.

For the one-pole Rc filter,

48
The loop natural frequency is a measure of the response time of the loop, and the damping
factor is a measure of the overshoot and ringing. Ideally, the natural frequency should be high and the
damping factor should be near 0.707 (critical damping). With a single pole filter, it is not possible to control
the loop frequency and damping factor independently.
For the case of critical damping,

A slightly more effective filter, the lag-lead filter includes one pole and one zero. This can be
realized with two resistors and one capacitor. The transfer function for this filter is

This filter has two time constants

τ1=C(R1+R2)
τ2=CR2

Substituting above yields the following natural frequency and damping factor

The loop filter components can be calculated independently for a given natural frequency and damping factor

Real world loop filter design can be much more complex eg using higher order filters to reduce various types
or source of phase noise.

49
Applications of PLL:
The PLL principle has been used in applications such as
 FM stereo decoders
 motor speed control
 Tracking f i l t e r s
 FM modulation and demodulation
 FSK m od ul a t i on
 Frequency multiplier
 Frequency synthesis etc.

3.9 Voltage ControlledOscillator:

Fig. 3.19 Block diagram of VCO

50
Fig. 3.19 Pin diagram of VCO

Referring to the circuit in the above figure, the capacitor c1is linearly charged or discharged
by a constant current source/sink. The amount of current can be controlled by changing the voltage vc
applied at the modulating input (pin 5) or by changing the timing resistor R1 external to the IC c h i p .
The voltage at pin 6 is held at the same voltage as pin 5.
Thus, if the modulating voltage at pin 5 is increased, the voltage at pin 6 also increases, resulting in
less voltage across R1and thereby decreasing the charging current. The voltage at pin 6 is held
at the same voltage as pin 5.

Thus, if the modulating voltage at pin 5 is increased, the

voltage at pin 6 also increases, resulting in less voltage across R1 and
thereby decreasing the charging current.

51
The voltage across the capacitor C1is applied to the inverting
input terminal of Schmitt trigger via buffer amplifier. The output voltage swing
of the Schmitt trigger is designed to Vcc an d 1.5 Vcc.IfRa= Rbin the positive
feedback loop, the voltage at the non-inverting input terminal of Schmitt
trigger swings from 0.5 Vccto 0.25Vcc.

When the voltage on the capacitor c1exceeds 0.5 Vccduring charging, the
output of the Schmitt trigger goes LOW (0.5 Vcc). The capacitor now
discharges and when it is at 0.25 Vcc, the output of Schmitt trigger goes
HIGH (Vcc).

Since the source and sink currents are voltage waveform

across c1which is also available at pin4.

The square wave output of the Schmitt trigger is inverted by buffer amplifier
at pin 3. The output waveforms are shown near the pins 4 and 3.The output
frequency of the VCO can be given as follows:

where V+ is Vcc.

The output frequency of the VCO can be changed either by

(i) R1,
(ii) c1or
(iii) the voltage vc a t the modulating input terminal pin 5.

The voltage vcc a n be varied by connecting a R1R2circuit as shown in the figure below.

The components R1and c1are first selected so that VCO output frequency lies in the centre
of the operating frequency range.

Now the modulating input voltage is usually varied from 0.75 Vcc to Vcc which can produce a frequency
variation of about 10 to 1.

The signetics NE/SE 560 series is monolithic phase locked loops. The SE/NE 560, 561, 562, 564, 565 & 567
differ mainly in operating frequency range, poser supply requirements & frequency & bandwidth adjustment
ranges.

52
3.10 Monolithic Phase Locked Loops (PLL IC565):

Fig. 3.20 Pin diagram of PLL IC565

Basic Block Diagram Representation of IC 565

The important electrical characteristics of the 565 PLL are,

 Operating frequency range: 0.001Hz to 500Khz.
 Operating voltage range: ±6 to±12v
 Input level required for tracking: 10mv rms min to 3 Vpp max
 Input impedance: 10 K ohms typically.
 Output sink current: 1mA
 Output source current: 10mA

53
Fig. 3.21 External connections of VCO

The center frequency of the PLL is determined by the free running frequency of the VCO, which is given by

fOUT=1.2/ 4R1C1

where R1&C1 are an external resistor & a capacitor connected to pins 8 & 9.

The VCO free running frequency fOUT is adjusted externally with R1 & C1 to be at the center of the input
frequency range.
C1 can be any value; R1 must have a value between 2 k ohms and 20 Kohms.

Capacitor C2 connected between 7 &+V.

The filter capacitor C2 should be large enough to eliminate variations in the demodulated output voltage in order to
stabilize the VCO frequency.

The lock range fL & capture range fc of PLL is given by,

fL= ±7.8fout/VHz

Where fOUT=free running frequency of VCO(Hz)

V = (+Vcc)-(-Vcc) volts

fC=±[fL/(2Π)(3.6)(103)C2] ½

54
Fig. 3.22 Block diagram of IC565

3.11 Monolithic PLL IC 565 applications:

The output from a PLL system can be obtained either as the voltage signal vc(t)corresponding
to the error voltage in the feedback loop, or as a frequency signal at VCO output terminal.

The voltage output is used in frequency discriminator applications whereas the frequency
output is usedin signal conditioning, frequency synthesis or clock recovery applications.

55
Fig. 3.23 circuit diagram of LM565 PLL

When PLL is locked to an input frequency, the error voltage vc(t) is

proportional to (fs-fo). If the input frequency is varied as in the case of FM signal vc will also vary in
order to maintain the lock. Thus the voltage output serves as a frequency discriminator which
converts the input frequency changes to voltage changes.

In the case of frequency output, if the input signal is comprised of many frequency components
corrupted with noise and other disturbances, the PLL can be made to lock, selectively on one
particular frequency component at the input.
The output of VCO would then regenerate that particular frequency (because of
LPF which gives output for beat frequency) and attenuate heavily other frequencies. VCO output thus
can be used for regenerating or reconditioning a desired frequency signal (which is weak and buried in
noise) out of many undesirable frequency signals.

56
Some of the typical applications of PLL are discussed below.

Frequency Multiplier:

Frequency divider is inserted between the VCO & phase comparator. Since the output of thedivider is
locked to the fIN, VCO is actually running at a multiple of the input frequency.
The desired amount of multiplication can be obtained by selecting a proper divide-by-N network,
where N is an integer.

Fig. 3.24 Frequency multiplier using PLL

57
Frequency Shift Keying (FSK)demodulator:

In computer peripheral & radio (wireless) communication the binary data or code is transmitted by
means of a carrier frequency that is shifted between two preset frequencies. Since a carrier frequency
is shifted between two preset frequencies, the data transmission is said to use a FSK. The frequency
corresponding to logic 1 & logic 0 states are commonly called the mark & space frequency.
For example, When transmitting teletype writer information using a modulator-demodulator (modem)
a 1070-1270 (mark-space) pair represents the originate signal, while a 2025-2225 Hz (mark-space)
pair represents the answer signal.

Fig. 3.24 FSK

58
FSK Generator:

The FSK generator is formed by using a 555 as an astable multivibrator, whose

frequency is controlled by the state of transistorQ1.

In other words, the output frequency of the FSK generator depends on the logic state
of the digital data input.
150 Hz is one the standards frequencies at which the data are commonly transmitted.
When the input is logic 1, the transistor Q1 is off. Under the condition, 555 timer works in its normal
mode as an astable multivibrator
i.e., capacitor C charges through RA& RBto 2/3 Vcc & discharges through RBto 1/3
Vcc. Thus capacitor C charges & discharges between 2/3Vcc & 1/3 Vcc as long as the input is logic1.
The frequency of the output waveform is given by,

When the input is logic 0, (Q1 is ON saturated) which in turn connects the resistance Rc
acrossRA.This action reduces the charging time of capacitor C1 increases the output frequency,
which is given by,

By proper selection of resistance Rc, this frequency is adjusted to equal the space
frequency of 1270 Hz. The difference between the FSK signals of 1070 Hz & 1270 Hz is 200 Hz, this
difference is called “frequency shift”.
The output 150 Hz can be made by connecting a voltage comparator between the output of the ladder
filter and pin 6 of PLL.
The VCO frequency is adjusted with R1 so that at fIN= 1070Hz.
FSK Demodulator:
The output of 555 FSK generators is applied to the 565 FSK demodulator.
Capacitive coupling is used at the input to remove dc line.
At the input of 565,the loop locks to the input frequency & tracks it between the 2 frequencies.
R1 & C1 determine the free running frequency of the VCO, 3 stages RC ladder filter is used to remove the
carrier component from the output.

59
Applications:

In digital data communication and computer peripheral, binary data is transmitted by means
of a carrier frequency which is shifted between two preset frequencies. This type of data transmission is
called frequency shift keying (FSK) technique. The binary data can be retrieved usingFSKdemodulator. The
figure below shows FSK demodulator using PLL for tele-typewriter signals of 1070 Hz and 1270 Hz. As the
signal appears at the input, the loop locks to the input frequency and tracks it between the two frequencies
with a corresponding dc shift at the output. A three stage filter removes the carrier component and the

output signal is made logic compatible by a voltage comparator.

Fig. 3.25 FSK demodulator circuit

60
AMDemodulation:

A PLL may be used to demodulate AM signals as shown in the figure below. The PLL is
locked to the carrier frequency of the incoming AM signal. The output of VCO which has the same frequency
0
as the carrier, but unmodulated is fed to the multiplier. Since VCO output isalways90 before being fed to the
multiplier. This makes both the signals applied to the multiplier and the difference signals, the
demodulated output is obtained after filtering high frequency components by the LPF. Since the PLL
responds only to the carrier frequencies which are very close to the VCO output, a PLL AM detector exhibits
high degree of selectivity and noise immunity which is not possible with conventional peak detector type AM

modulators.

Fig. 3.26 AM demodulator

61
FMDemodulation:

If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of the input signal. The filtered
error voltage which controls the VCO and maintains lock with the input signal is the demodulated FM

output.

The VCO transfer characteristics determine the linearity of the demodulated output. Since, VCO used in IC

PLL is highly linear, it is possible to realize highly linear FM demodulators.

Frequency multiplication/division:

The block diagram shown below shows a frequency multiplier/divider using PLL. A divide by
N network is inserter between the VCO output and the phase comparator input.Inthe locked state,the VCO
output frequency fois given by fo= Nfs.The multiplication factor can be obtained by selecting a pr ope r

s c a l ing f a c t o r N o f t he counter.

Frequency multiplication can also be obtained by using PLL in its harmonic locking mode. If
the input signal is rich in harmonics e.g. square wave, pulse train etc., then the VCO can be directly locked to
the n-th harmonic of the input signal without connecting any frequency divider in between. However, as
the amplitude of the higher order harmonics becomes less, effective locking may not take place for high

values of n. Typically n is kept less than10.

Fig. 3.27 Frequency Divider

62
The circuit of the figure above can also be used for frequency division. Since the VCO output (a
square wave) is rich in harmonics, it is possible to lock the m-th harmonic of the VCO output with the input signal fs.
The output fo of VCO is now given by

f o=fs/m

PLL Frequency Synthesis:

In digital wireless communication systems (GSM, CDMA etc), PLL's are used to provide the Local
Oscillator (LO) for up-conversion during transmission, and down-conversion during reception.
Inmost cellular handsets this function has been largely integrated into a single integrated circuit to

reduce the cost and size of the handset.

However due to the high performance required of base station terminals, the transmission and
reception circuits are built with discrete components to achieve the levels of performance required.
GSMLO modules are typically built with a Frequency Synthesizer integrated circuit, and discrete

resonator VCO's

Principle of PLL synthesizers

A phase locked loop does for frequency what the Automatic Gain Control does for voltage.
It compares the frequencies of two signals and produces an error signal which is proportional

to the difference between the input frequencies

The error signal is then low pass filtered and used to drive a voltage-controlled oscillator
(VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to

the input of the system, producing a negative feedback loop.

If the output frequency drifts, the error signal will increase, driving the frequency in the
opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input.
This input is called the reference and is derived from a crystal oscillator, which is very

stable infrequency.

63
The block diagram below shows the basic elements and arrangement of a PLL based frequency synthesizer.

Fig. 3.28 PLL based frequency synthesizer

The key to the ability of a frequency synthesizer to generate multiple frequencies is the
divider placed between the output and the feedback input. This is usually in the form of a digital counter,
with the output signal acting as a clock signal.

The counter is preset to some initial count value, and counts down at each cycle of the
clock signal. When it reaches zero, the counter output changes state and the count value is reloaded.
This circuit is straightforward to implement using flip-flops, and because it is digital in nature, is very easy
to interface to other digital components or a microprocessor.
This allows the frequency output by the synthesizer to be easily controlled by a digital
system.

64
Example:

Suppose the reference signal is 100 kHz, and the divider can be preset to any value
between 1 and The error signal produced by the comparator will only be zero when the output of the
divider is also 100 kHz. For this to be the case, the VCO must run at a frequency which is 100 kHz x the

divider count value.

Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count of 2, 1
MHz for a count of 10 and so on. Note that only whole multiples of the reference frequency can be

obtained with the simplest integer N dividers. Fractional N dividers are readily available

Practical considerations:

In practice this type of frequency synthesizer cannot operate over a very wide range of
frequencies, because the comparator will have a limited bandwidth and may suffer from aliasing problems.
This would lead to false locking situations, or an inability to lock at all. In addition, it is hard to make a high

frequency VCO that operates over a very wide range.

This is due to several factors, but the primary restriction is the limited capacitance range
of varactor diodes. However, in most systems where a synthesizer is used, we are not after a huge range,
but rather a finite number over some defined range, such as a number of radio channels

in a specific band.

Many radio applications require frequencies that are higher than can be directly input to
the digital counter. To overcome this, the entire counter could be constructed using high-speed logic such
as ECL, or more commonly, using a fast initial division stage called a pre scaler which reduces the frequency

to a manageable level.

Since the pre scaler is part of the overall division ratio, a fixed pre scaler can cause
problems designing a system with narrow channel spacing’s - typically encountered in radio applications.
This can be overcome using a dual-modulus pre scaler.
Usually the output of a frequency comparator is in the form of short error pulses, but the input of the VCO
must be a smooth noise- free DC voltage. (Any noise on this signal naturally causes frequency modulation

of the V C O .

Heavy filtering will make the VCO slow to respond to changes, causing drift and slow response time, but
light filtering will produce noise and other problems with harmonics. Thus the design of the filter is critical
to the performance of the system and in fact the main area that a designer will concentrate on when

building a synthesizer system.

65
PROBLEMS

1. Calculate the lock range and Capture range for a 565 PLL with free running
frequency F0=500Hz, Fv=5V and –V=4V.

Sol,
8𝑓
∆𝑓𝐿 = ∓ 𝑉0 𝐻𝑍
𝑓0 =500HZ
V=9 V
∆𝑓𝐿 = ∓444.44𝐻𝑍
Capture Range
∆𝑓𝐿
∆𝑓𝑐 = ∓ 𝐻𝑍
2𝜋 3.6 1000 𝐶2

∆𝑓𝑐 =443.24HZ

2. A PLL has a running frequency of 500 Hz and BW of LPF is 10KHz. Will the loop
acquire a lock for a input signal of 600 KHz? Justify your answer.

Sol,
𝑓𝑠 +𝑓0 = 600 KHZ + 500 KHZ= 1100 KHZ
𝑓𝑠 − 𝑓0 = 100 KHZ
As both the components are outside the pass band of LPF, the loop will not acquire
lock.
3. For a VCO circuit, the control voltage 𝑉𝐶 = 10.465 𝑉, 𝑅 𝑇 = 15𝐾Ω, 𝐶𝑇 =0.001F
and 𝑉𝑐𝑐 =12V. Determine
(a) Output Frequency
(b) Change in output frequency if modulating input is varied from 7V to 8V.
Sol,
2(𝑉𝑐𝑐−𝑉𝑐)
𝑓0 = 𝑅 𝐶 𝑉𝑐𝑐
𝑇 𝑇
=17.06KHz

2∆𝑉𝐶
∆𝑓0 =
𝐶1𝑅1𝑉𝑐𝑐

= 11.11 KHz
10.Assignment:

1. Design a PLL based FM detector

2. Design a frequency divider / multiplier using IC 565

3. Design a PLL based FSK modulator and demodulator

4. Illustrate with an example application of Analog multiplier IC

5. Calculate the lock range and Capture range for a 565 PLL with free running frequency
F0=500Hz, Fv=5V and –V=4V
6. A PLL has a running frequency of 500 Hz and BW of LPF is 10KHz. Will the loop acquire a
lock for a input signal of 600 KHz? Justify your answer.

.
68
11.Part A Question and Answer
Unit-III
1. How do you convert a basic multiplier to a squaring and square root circuit?
[K1-CO3]
For Voltage Squarer: The input voltage Vi to be squared is simply connected to both the
input terminals and hence we have, Vx =Vy = Vi and the output is V0 = KV2i.
For Square rooter: the divider circuit can be used to find the square root of a signal by
connecting both the inputs of the multiplier to the output of the op-amp.

2. What are the applications of PLL for AM detection? [K1-CO3]

The PLL can be used as an AM detector for demodulating the amplitude modulated
signals.

3. Define : (a) Capture range and (b) Lock range of Phase Locked Loop (PLL)
[K1-CO3]
Capture range : The range of frequencies over which the PLL can acquire lock with an
input signal is called the capture range. This parameter is expressed as percentage of fo.
Lock-in Range : The range of frequencies over which the PLL can maintain lock with the
incoming signal is called the lock-in range or tracking range. The lock-in range is
expressed as a percentage of fo, the VCO frequency.

4. Mention two applications of analog multiplier. [K1-CO3]

Voltage squarer , Frequency doubler

5. What is four quadrant multiplier? [K1-CO3]

The four-quadrant operation indicates that the output voltage is directly proportional to
the product of the two input voltages regardless of the polarity of the inputs and such
multipliers can be operated in all the four quadrants of operation.
69
6. Draw the circuit diagram of a PLL circuit using as a FM detector. [K1-CO3]

7. Enlist any four applications of NE 565 PLL. [K3-CO3]

AM detection
FM detection
FSK modulation /demodulation
Frequency multiplication

8. Draw the block diagram of IC 566 VCO (Voltage Controlled Oscillator) [K1-
CO3]

9. What is meant by frequency synthesizing? [K1-CO3]

A Frequency Synthesizer allows the designer to generate a variety of output
frequencies as multiples of a single reference frequency. The frequency synthesizer
produces a large number of precise frequencies, which are derived from a single reference
source of frequency, a stable crystal controlled oscillator.
70
10. Define lock range of a PLL. [K1-CO3]
The range of frequencies over which the PLL can maintain lock with the
incoming signal is called the lock-in range or tracking range. It is expressed as a percentage
of fo , the VCO frequency.
11. A PLL frequency multiplier has an input frequency of “f” and a decade
counter is included in the loop. What will be the frequency of the PLL output?
[K3-CO3]
fo = 1 / 10secs
12. Mention any two applications of PLL. [K1-CO3]
Frequency translation, AM detection, FM Demodulation, FSK Demodulator.
13. What is a two quadrant multiplier? [K1-CO3]
A two quadrant multiplier functions properly if one input is held positive and the other is
allowed to swing in both positive and negative.
14. What are the advantages of variable transconductance technique? [K2-CO3]
Provides very good accuracy
Provides four quadrant operation
Reduced error atleast by 10 times
15. VCO is also called V-f converter. Why? [K1-CO3]
The VCO converts the applied input voltage to an output frequency. Hence, it is called
voltage to frequency converter.
16. What are the advantages of emitter coupled transistor pair? [K3-CO3]
Low drift because of its symmetrical IC construction.
Very high input resistance
High CMRR
17. With a reference to a VCO, define voltage to frequency conversion factor Kv.
[CO3-L1]
Voltage to frequency conversion factor Kv is defined as KV = ∆f0 /∆Vc

18. What is VCO? [CO3-L1]

The VCO is a free running multivibrator and operates at a set frequency called free running
frequency. This frequency can be shifted to the either side by applying a dc control voltage.
The frequency deviation is directly proportional to the dc control voltage and hence it is
called Voltage Controlled Oscillator.
71
19. Draw the relation between the capture ranges and lock range in a PLL. [K1-
CO3]

20. List the basic building blocks of a PLL? [K1-CO3]

A phase locked loop consists to a phase detector, low pass filter, amplifier and a VCO in
feedback loop.
21. What are the important characteristics of a PLL? [K1-CO3]
The important characteristics of a PLL are: lock-in range, capture range and pull-in-time.
22. What is the need of LPF in a PLL? [K1-CO3]
The LPF not only removes the high frequency components and noise, but also controls the
dynamic characteristics of the PLL. The LPF controls the capture range and lock range of a
PLL.
23. Which is greater ‘Capture range’ or ‘Lock-in range’? [K1-CO3]
The lock-in range is usually greater than the capture range. The capture range depends
upon the LPF characteristics.
24. What is the range of modulation input voltage applied to a VCO? [K1-CO3]
The modulating input voltage is usually varied from 0.75 Vcc to Vcc which can produce a
frequency variation of about 10 to 1.
25. Mention few monolithic PLL ICs? [K1-CO3]
Signetics SE/NE 560 series – 560,561,562,564,565 and 567 are monolithic PLLs.
26. Mention few applications of analog multiplier? [K1-CO3]
Frequency doubling, Phase angle detection, Squaring, Multiplication, Division
72
27. What is transconductance multiplier? [K1-CO3]
Log-amps require the input and reference voltages to be of the same polarity. This restricts
log-antilog amplifiers to one quadrant operation. A technique that provides four quadrant
multiplication is trans-conductance multiplier.
28. What are the types of phase detector? [K1-CO3]
Analog phase detector and Digital Phase detector
29. What are the performance parameters of a multiplier? [K1-CO3]
Accuracy, Linearity, Bandwidth, Feed through voltage, Scale factor
30. Define scale factor of multiplier? [K1-CO3]
Scale factor is the constant (k) relating the output voltage and the product of two input
voltages.
K= Vo / V1V2
31. Define Pull-in time. [K1-CO3]
The total time taken by the PLL to establish lock is called pull-in time. It depends on the
initial phase and frequency difference between the two signal levels as well as on the
overall loop gain and loop filter characteristics.
32. What are the three stages through which PLL operates? [CO3-L3]
i.Free running ii. Capture iii. Locked/tracking
33. A PLL frequency multiplier has an input frequency of “f” and a decade
counter is included in the loop. What will be the frequency of the PLL output? .
[K1-CO3]

Output of PLL = 10f

73
12. Part B Questions
Unit-III

With neat diagram explain the design of

1.
(i)Frequency Synthesizer
(ii) Frequency Division circuit using PLL IC 565 (K2, CO1)
(i) Discuss the principle of operation of NE 565 PLL circuit
2.
(ii) How can PLL be modeled as a frequency multiplier?
3. Explain the Application of PLL as AM detection, FM detection and FSK
demodulation
4. Explain the basic blocks of PLL and determine
expressions for lock in range and capture range
(i) With neat simplified internal diagram explain the working principle of
5.
operational Transconductance Amplifier(OTA)
(ii) Explain the application of VCO for FM generation
With suitable block diagram explain the operation of
6.
566 voltage controlled oscillator. Also derive an expression for the frequency of
the output waveform generated
7. Explain the working principle of four quadrant variable form transconductance
multiplier
8. Draw the analog multiplier IC and explain its features and Explain the
application of analog multiplier IC
(i) Explain Analog Multiplier using Emitter Coupled Transistor
9.
(ii) Explain Gilbert Multiplier cell in detail
13.Supportive online Certification courses:

UNIT III :

NPTEL/SWAYAM:

Analog ICs

By Prof. K. Radhakrishna Rao | IIT Madras

8 Weeks

https://nptel.ac.in/courses/108/106/108106068/

COURSERA

Introduction to Electronics

https://www.coursera.org/lecture/electronics/2-1-introduction-to-op-amps-and-ideal-

behavior-Q5Di2

UDEMY:

Electronics : The Operational Amplifier

https://www.udemy.com/course/operational-amplifiers/

Phase Lock Loop System Design Theory and Principles

https://www.udemy.com/course/phase-lock-loop-online-course-rahsoft-system-design-

theory/
Test Yourself

UNIT III ANALOG MULTIPLIER AND PLL

1.Determine output voltage of analog multiplier provided with two input signal Vx and Vy.

a) Vo = (Vx ×Vx) / Vy
b) Vo = (Vx ×Vy / Vref
c) Vo = (Vy ×Vy) / Vx
d) Vo = (Vx ×Vy) / Vref2
2..Match the following:
a) 1-ii, 2-i, 3-iii
b) 1-ii, 2-ii, 3-ii
c) 1-iii, 2-I, 3-ii
d) 1-I, 2-iii, 3-i
3. Find the voltage range at which the multiplier can be used as a squarer circuit?
a) 0 – Vin
b) Vref – Vin
c) 0 – Vref Lis

d) All of the mentioned 1. O

4. Which circuit can be used to take square root of a signal?
a) Divider circuit 2. T
b) Multiplier circuit
c) Squarer circuit
3. F
d) None of the mentioned
5.Which among the following is multiplier technique?
a) logarithmic summing circuit
b) Multiplier circuit
c) pulse width technique
d) both a and c
Test Yourself

6.The output of gilbert multiplier cell is

a) Vo=V1+V2
b) Vo=V1-V2
c) Vo=kV1V2
d) None of the mentioned

7.The heart of four quadrant variable transconductance multiplier cirucuit is

a)lineralized transconductance amplifier

b) differential V-I converter
c)both a and b
d)gilbert multiplier cell alone

8.IC AD 533 can be used as

a) multiplier
b) squarer
c) divider
d) All of the mentioned

9.OTA stands for

a)Operational Transducer Amplifier

b) Operational Transconductance Amplifier
c Operation Transistor Amplifier
d) None of the mentioned

10.OTA is basically

a) current to voltage converter

b) voltage to current converter

c) both a and b

d) constant input source

Test Yourself

11.Limitations of logarithmic summing technique?

a) good accuracry
b) four quadrant operation
c) temperature instability
d) All of the mentioned

12.IC AD 534 can be used as

a) divider and square rooter

b) divider or square rooter
c) divider
d) square rooter

13.The phase angle detection using multiplier is obtained by

a) the frequency doubler circuit with two inputs of same frequency but different amplitude
and phases
b) the frequency doubler circuit with two inputs of same frequency but same amplitude
and phases
c) the frequency doubler circuit with two inputs of same frequency but different amplitude
and same phases

d) the frequency doubler circuit with two inputs of same frequency but same amplitude
and different phases

14.The voltage divider circuit using multiplier is that the output is

a) addition of two input signals

b) division of two input signals
c) voltage is divided among the input signals equally
d) All of the mentioned

15.Application of gilbert cell

a) as three quadrant linear multiplier

b) in switching
c) temperature instability
d) in function generator
Test Yourself

16.The basic PLL operation consists of

a) phase detector, low pass filter, amplifier,VCO

b) phase detector, highpass filter, amplifier,VCO
c) detector,filter, amplifier,VCO
d) phase detector,filter, amplifier

17. For what kind of input signal, the frequency divider can be avoided
frequency multiplier?
a) Triangular waveform
b) Square waveform
c) Saw tooth waveform
d) Sine waveform

18.The range of frequencies over which the PLL can maintain the lock with
the incoming signal is called

a) Lock range
b) tracking range
c) capture range
d) both a and b

19. The range of frequencies over which the PLL can acquire the lock with
the incoming signal is calleda) Lock range
b) pull in time
c) capture range
d) both a and b

20.The total time taken by the PLL to establish a lock is called

a) Lock range
b) pull in time
c) capture range
d) pull out time
Test Yourself

21. Calculate the output frequency in a frequency multiplier if, fin = 200Hz is
applied to a 7 divide by N-network.
a) 1.2kHz
b) 1.1kHz
c) 1.4kHz
d) 1.5kHz

22.The lock in frequency is

a) 8.84fo/V
b) 10fo/V
c) 7.84fo/V
d) 1.9kHz

23.Filters used in PLL are

a)loop filer and sideband filter

b) active filter
c) passive filter
d) all the above

24. Determine the offset frequency of frequency translation, when the

output and input frequency are given as 75kHz and 1000Hz.
a) 35 kHz
b) 20 kHz
c) 29 kHz
d) 14 kHz

25. The frequency corresponding to logic 1 state in FSK is called

a) Space frequency
b) Mark frequency
c) Both mark and space frequency
d) None of the mentioned
14 .REAL TIME APPLICATIONS IN DAY TO DAY LIFE
The incredible versatile op amp in medical apps

Operational amplifiers (op amps) are a staple in modern electronics. Found in

everything from industrial flow metering to ultrasound imaging, versatility is their
appeal. This building block is unique in that no other single integrated circuit (IC) can
be used in so many different applications and configurations. Besides providing
amplification, op amps can realize a wide range of functions such as summing,
buffering, subtraction, integration, differentiation, filtering, inversion, and current-to-
voltage conversion, to name a few. This article focuses on medical applications, but
could easily cover industrial, consumer, or communications, as the same fundamental
op amp building blocks are common to a variety of applications. We’ll also discuss
“specialty op amps” and new functionality that can be found in today’s op amps.
Healthcare products are no longer restricted to hospitals and clinical settings. Today’s
consumer can purchase a wide variety of home healthcare electronics including
automatic blood pressure monitors, fingertip pulse oximeters, digital thermometers,
and blood glucose monitors. Op amps, used in medical platforms that include
diagnostics, therapy, monitoring, imaging, and instrumentation, can be found in
almost any block diagram. In the main signal path, secondary circuits and power
supplies, their uses are countless.

Let’s take a close look at a low-power portable pulse oximeter. Then, at a higher level,
we’ll discuss a few other applications and the common op-amp building blocks they
share.
Pulse oximetry
A pulse oximeter is a noninvasive device that measures the percentage of hemoglobin
saturated with oxygen (SPO2) and the pulse rate of a patient. Typically clipped to a
fingertip or earlobe, the pulse oximeter can be used in a variety of settings: operating
rooms to monitor oxygenation and pulse rate while under anesthesia, during machine
assisted ventilation, and as an added safety measure during outpatient procedures.
Numerous op amp circuits are used in the pulse oximeter. These same building blocks
are widely used in other medical and non-medical applications. Figure 1 shows a
typical finger tip pulse oximeters.
The pulse oximeter works by measuring the light absorption or reflection of
Hemoglobin, which absorbs light differently when carrying oxygen (oxyhemoglobin)
than when not (deoxyhemglobin). Red (R) and infrared light (IR) sources are used
along with a photodiode detector to measure the amount of light that passes or
reflects through the tissue sample. Hemoglobin saturated with oxygen will absorb IR,
while hemoglobin carrying low levels of oxygen will absorb red light. TheThe R/IR ratio
is compared to a lookup table to yield the SPO2. A typical SPO2 of 0.5 indicates
approximately 100% SPO2, while a ratio of 2 indicates 0% SPO2.

Fig. 1. Fingertip pulse oximeter.

Fig. 2. A typical block diagram for a pulse oximeter consists of numerous op

amps and other components used in this application.
Figure 2 shows a typical block diagram for a pulse oximeter. While this may appear to be
relatively simple application, the block diagram shows that there are numerous
components. Op amps are used to convert current to voltage (I to V), drivean ADC
(analog-to-digital converter), drive LED excitation sources, buffer a microprocessor input,
and process audio. Many of these op amp building blocks can be found in just about any

electronic device.

The pulse oximetry light is provided by two light emitting diodes (LED). A red LED
emits light in the 600-nm (nanometer) to 700-nm region, while an IR LED emits in
the 800-nm to 900-nm region. The two LEDs are switched on and off at a high
rate by the current sources formed by U1 and U2. The transmitted or reflected
light is detected by photodiode D3, which produces a small current proportional to
the light detected. This current is converted to a voltage via a precision FET-input
op amp that is typically used in photodiode detectors or current-to-voltage
converters. FET-input op amps require very little input bias current, ensuring that
the majority of the photodiode current passes through the feedback resistor,
providing accurate data.

The output of the I-to-V converter is then filtered, either actively or passively; an
active filter provides another opportunity for an op amp to be used. The signal is
then fed to a buffer op amp, which interfaces to the microprocessor to indicate a
no-connection fault if the pulse oximeter falls off the patient.

The signal is also fed to ADC driver U5, which sets the signal to the appropriate
amplitude and offset settings, which are compatible with the ADC. Depending on
the system requirements, the ADC driver can be realized with traditional op amps
or a differential amplifier, which is a special class of op amps that we’ll discuss in
more detail later. In this portable application, a low-power op amp is most
appropriate. The signal is then digitized and analyzed by the microprocessor.
U1 and U2, precision micropower op amps, form the heart of the current sources that drive
the red and IR LEDs. The two LEDs require different currents, so a dual op amp is a smart
choice to save board area and lower cost. The voltage from the DAC (digital-to-analog
converter) is fed to U1 and U2 via analog switch SW1. The op amps have limited output
current capability, therefore external FET pass transistors (Q1 and Q2) are used. The
voltage across RISET1 and RISET2 sets the current through the LEDs.
The op amp U6 provides the drive signal to a speaker or transducer for audible monitoring
purposes. This application is a good example is of where and how op amps can be used in
medical electronics. Though physically small, the pulse oximeter puts a lot of electronics
right at your fingertips!
No matter whether the application is digital X-ray, industrial flow metering, white goods, or
flow cytometry, the same op amp building blocks can be found in all these applications, as
shown in Fig. 3 . Flow cytometry, illuminates single cells with a laser and then detects the
scattered light. The scattered light signature tells the story of the cell condition. In digital
X-ray applications that use indirect conversion, the X-ray radiation must first be converted
to light via a scintillator, which is then fed to a photodiode detector. Both the flow
cytometry and digital X-ray use a photodiode detector (I to V converter) and then send the
signal to an ADC, first passing through an ADC driver. This pattern is repeated for just
about any signal acquisition chain, the main difference being how the signals are captured.

Fig. 3. Flow cytometry block diagram.

15.CONTENT BEYOND THE SYLLABUS

Specilaity Opamps

 Specialty op amps

Specialty op amps, derivatives of traditional op amps, are used in many applications

including medical. Let’s take a look at a few.

Differential amplifiers are a special class of op amps; they are ideally suited for
driving high-speed and precision ADCs and for driving video signals over unshielded
twisted pair (UTP) cables. Similar to traditional op amps, differential amplifiers can
process differential or single-ended signals at their inputs, but differential amplifiers
have balanced differential outputs while op amps have a single-ended output.
Differential amplifiers also have a dedicated pin that controls the output common-
mode voltage. If a system uses an ADC, it’s likely that a differential amplifier drives it;
with a DAC, a differential amplifier often buffers the output.

Instrumentation amplifiers (in-amps) are used as a key interface between patient and
equipment, as they have very high input impedance, and low input offset and bias
currents. The differential inputs are balanced so that the input source and output can
be independent of any load reference. In-amps also have very high common-mode
rejection, so that coupled noise pick up and ground drops are kept to a minimum.
Instrumentation amps can be found in ECG and EEG machines.

Variable-gain amplifiers (VGA) and programmable-gain amplifiers (PGA) can be

lumped into one category. These amplifiers, which do not require feedback or gain-
setting resistors, can change their gain with an analog voltage or a digital interface.
Their input and outputs can be either single-ended or differential. VGAs or PGAs are
commonly found in automatic gain-control (AGC) applications, wide-dynamic-range
data-acquisition systems, equipment that uses photodiode circuits, and ultrasound
front-ends.
Package, power, and pinout
Portable electronics must be small size and low power, as their area and current
budgets are extremely small. The wafer-level chip-scale package (WLCSP), the smallest
available, actually eliminates the package. As shown in Fig. 4 , a dual low-power op
amp, the package is the die itself with bumped eutectic solder dots. This minimizes
board area and reduces the effects of parasitics. One drawback to this package option
is the limited number of parts offered in it. Traditional small packages such as SOT23,
SC70, LFCSP, and DFN are still great choices. Some of the new packages also feature
an exposed paddle, which lower the package thermal resistance and increases
reliability.

Fig.1 Wafer-level chipscale.

Typically powered by batteries, the current budget for portables is small. Therefore,
low supply voltages and currents are critical. Some new op amps dissipate only a few
hundred nanowatts of power. When discussions turn to body area networks (BAN) or
WBAN (wireless BAN), power is of the utmost concern. In BAN applications, the user
wears devices that collect body data at a local level. Some work has already been
done to power these devices from body heat, with a thermoelectric generator (TEG)
worn on the users wrist to convert body heat to voltage. Now that is low power!
The traditional op amp pin-out has been around for over 40 years, with virtually no
change until recently. Analog Devices first introduced a new high-performance pin-
out with a dedicated feedback pin, as shown in Figure 5 . The new pin-out can be
found on some of the company’s newest high-speed amplifiers and differential
amplifiers.
The new pin-out is essentially the same as the traditional op amp pinout, except that pins
have been rotated counterclockwise (CCW) one position. The CCW shift provides two
benefits. First, it allows for all the input and outputs to be on one side. This greatly
simplifies the layout and reduces board parasitics. Second, mutual coupling that occurs
between pin 3 (non-inverting input) and pin 4 (–Vs) in the traditional pinout leads to
degraded second-harmonic distortion. By rotating the pinout one pin CCW, the coupling is
broken. Improvements to second-harmonic distortion can be significant; a gain of greater
than 10 dB between traditional pinouts and the dedicated feedback pin is not uncommon.

Fig. 2.Dedicated feedback pinout.

16.Assessment Schedule
ASSESSMENT SCHEDULE

Assessment Proposed Date Actual Date

Unit 1 Assignment 5-3-2021 5-3-2021
Assessment
Unit Test 1 - -

Unit 2 Assignment 12-03-2021 12-03-2021

Assessment
Internal Assessment 1 26-3-2021

Retest for IA 1 30-3-2021

Unit 3 Assignment 3-4-2021

Assessment
Unit Test 2 -

Unit 4 Assignment 12-4-2021

Assessment
Internal Assessment 2 23-4-2021

Retest for IA 2 26-4-2021

Unit 5 Assignment 6-5-2021

Assessment
Revision Test 1 11-5-2021

Revision Test 2 13-5-2021

Model Exam 19-5-2021

Remodel Exam 23-5-2021

University Exam
17.Prescribed Text Books
&
Reference Books
PRESCRIBED TEXT BOOK AND REFERENCES:

TEXT BOOK:
1. D.Roy Choudhry, Shail Jain, ―Linear Integrated Circuits‖, New Age
International Pvt. Ltd., 2018, Fifth Edition.

2. Sergio Franco, ―Design with Operational Amplifiers and Analog

Integrated Circuits‖, 4th Edition, Tata Mc Graw-Hill, 2016.

REFERENCES:
1. Ramakant A. Gayakwad, ―OP-AMP and Linear ICs‖, 4th Edition,
Prentice Hall / Pearson Education, 2015.

2. Robert F.Coughlin, Frederick F.Driscoll, ―Operational Amplifiers and

Linear Integrated Circuits‖, Sixth Edition, PHI, 2001.

3. B.S.Sonde, ―System design using Integrated Circuits‖ , 2nd Edition,

New Age Pub, 2001.

4. Gray and Meyer, ―Analysis and Design of Analog Integrated

Circuits‖, Wiley International,5th Edition, 2009.

5. William D.Stanley, ―Operational Amplifiers with Linear Integrated

Circuits‖, Pearson Education,4th Edition,2001.

6. S.Salivahanan & V.S. Kanchana Bhaskaran, ―Linear Integrated

Circuits‖, TMH,2nd Edition, 4th Reprint, 2016.
18. Mini Project
Suggestions
MINI PROJECT SUGGESTIONS

Sl. Title Link Competence

NO
1. Electronics https://bestengineeringprojects. Analyze
Thermometer using com/electronics-thermometer-
Op-amp 741 IC using-op-amp-741-ic/

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Using Op-amp 741 com/electronic-fuse-using-op-
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3. Sound detector https://bestengineeringprojects. Create

circuit using op- com/sound-detector-circuit-
amp 741 using-op-amp-741/

4. Sound Operated https://www.electronicsforu.com Evaluate

Intruder Alarm /electronics-projects/sound-
operated-intruder-alarm

5. Head Phone https://www.youtube.com/watch Analyze

Amplifier ?v=v_D7-gm2NHE

6. Tone control for https://bestengineeringprojects. Create

Guitar amplifier com/tone-control-for-guitar-
using op-amp 741 amplifier-using-741/

7. Temperature https://bestengineeringprojects. Create

deviation indicator com/temperature-deviation-
using op-amp indicator-using-op-amp-741/

8. Listening Bug using https://www.youtube.com/watch Analyze

op-amp 741 ?v=fXTi2alpdE8

9. Adjustable ripple https://bestengineeringprojects. Create

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10. Microphone https://bestengineeringprojects.co Create

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MINI PROJECT SUGGESTIONS

Sl. Title Link Competence

NO
11. Operational https://bestengineeringprojects. Analyze
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12. A variable audio https://bestengineeringprojects. Evaluate

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operated switch v=ND1FgsNhnLA
using LDR and 741
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16. High/Low voltage https://bestengineeringprojects.co Create

cut-out using op- m/highlow-voltage-cut-out-using-
amp 741 op-amp-741/
17. LED Chaser Circuit https://www.youtube.com/watch? Create
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18. LED Flasher Circuit https://www.youtube.com/watch? Analyze

v=38kVFDdDC8A

19. 10 Minute timer https://www.circuitstoday.com/10- Create

circuit. minute-timer-circuit

20. Flashing LED unit https://www.circuitstoday.com/fla Create

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21. Rain alarm circuit https://www.circuitstoday.com/rai Analyze

n-alarm-circuit

22. Missing pulse https://www.circuitstoday.com/mi Evaluate

detector circuit ssing-pulse-detector-circuit-using-
using NE555 ne555
Thank you

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