Noise: Introduction To Low-Noise Design

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Noise

Lecture 5
I ntroduction to
Low -N oise Design

Behzad Razavi
Electrical Engineering Department
University of California, Los Angeles
Outline

• Low-Noise Op Amps
• kT/C Noise
• Application Example

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A Few Refreshers

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Basic Principles

• Noise trades with power, bandwidth, and


linearity.
• Avoid source followers.
• Minimize the number of noise contributors:

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Noise in Telescopic Cascode Op Amp

• Main noise contributors:


- M1 and M2
- M7 and M8
• Need to minimize (VGS-VTH)1,2
 wide input transistors
• Need to maximize (VGS-VTH)7.8
 large voltage headroom
consumption
• Change to PMOS input
devices for lower flicker
noise.

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Thermal Noise in Folded-Cascode Op Amp

• 6 Noise contributors
• Change to PMOS input for lower flicker noise.
• Need to maximize overdrives of M7,8 and M9,10.
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Thermal Noise in Simple Two-Stage Op Amp

• Noise contributed by second stage must be


made negligible.
• 4 Noise Contributors
• Easy to make noise of M3,4 negligible as well 
Best noise performance for moderate voltage
gain. 7
High-Gain Two-Stage Op Amp

• Noise contributed by second stage is negligible.


• 4 Noise contributors
• Noise contributed by M7,8 may not be negligible.
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Basic Design Procedure

• Start with a power budget.


• Allocate about half to first stage.
• Select overdrives of first stage
devices according to VDD.
• Give M7,8 a greater overdrive than
other devices in first stage.
• Select device dimensions for
first stage, starting with Lmin.
• Calculate input-referred noise.
• If M1,2 thermal contribution is
large, increase their W.
• If M1,2 flicker contribution is
large, increase their W and L
(and change to PMOS input).

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kT/C Noise

• With a 1-pF capacitor, the sampled noise is


64.3 µVrms.

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Circuit Example: Multiply-by-2 Stage
Sampling Mode Amplification Mode

Actual Circuit

Sampling Mode Amplification Mode

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