Scribd
Upload
42 views3 pages

Index

This document appears to be the first dissertation report of Vinay Patil submitted in partial fulfillment of a Master's degree in Electronics and Telecommunication Engineering. The report discusses the development of verification IP for the AXI4 protocol using the Universal Verification Methodology. It provides an overview of the AXI4 protocol, verification methodology, SystemVerilog, UVM classes used, and the UVM testbench components developed including the UVC for the AXI4 master and slave. Results are presented on verifying features of the AXI4 protocol like the handshake process, burst addressing, and read/write burst transactions.

Uploaded by

'Vinay Patil
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
42 views3 pages

Index

This document appears to be the first dissertation report of Vinay Patil submitted in partial fulfillment of a Master's degree in Electronics and Telecommunication Engineering. The report discusses the development of verification IP for the AXI4 protocol using the Universal Verification Methodology. It provides an overview of the AXI4 protocol, verification methodology, SystemVerilog, UVM classes used, and the UVM testbench components developed including the UVC for the AXI4 master and slave. Results are presented on verifying features of the AXI4 protocol like the handshake process, burst addressing, and read/write burst transactions.

Uploaded by

'Vinay Patil
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
Download as docx, pdf, or txt
Download as docx, pdf, or txt
You are on page 1/ 3

FIRST DISSERTATION REPORT

(July 2019 - June 2020)


On

Development of Verification IP for AXI-4 Protocol


using Universal Verification Methodology

By
Vinay Patil
MIS NO: 121835015

In
VLSI and ES
(Electronics & Telecommunication Engineering)
Under the guidance of
Dr. Mrs. Vaishali Ingale

DEPARTMENT OF ELECTRONICS AND


TELECOMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING, PUNE
Department of Electronics and Telecommunication Engineering
College of Engineering, Pune

CERTIFICATE
This is to certify that the thesis titles “Development of Verification IP for AXI4
Protocol using Universal Verification Methodology” Submitted by Vinay Patil (121835015)
in partial fulfilment of the requirements for the award of Master of Technology degree in
Electronics and Telecommunication Engineering, with specialization in VLSI and Embedded
Systems during year 2019-20 at College of Engineering, Pune is an authenticate work by him
under my supervision and guidance.

Certified by

Dr. Mrs. V. V. Ingale Dr. S. P. Mahajan


Project Guide Head of Department

Date :

Place :
Index
1 Introduction 1
2 Review of Literature 3
3 Objective 5
4 Methodology 6
4.1 AXI4 Protocol 6
4.1.1 AXI4 Interface Channel 6
4.1.2 AXI4 Protocol Features 8
4.2 Verification 8
4.3 System Verilog 9
4.4 Universal Verification Methodology (UVM) 9
4.4.1 uvm_object 10
4.4.2 uvm_component 10
4.4.3 uvm_transaction 10
4.4.4 uvm_root 10
4.5 UVM Testbench 10
4.5.1 UVM Test 11
4.5.2 UVM Environment 11
4.5.3 UVM Scoreboard 11
4.5.4 UVM Agent 11
4.5.5 UVM Sequence 11
4.5.6 UVM Driver 11
4.5.7 UVM Monitor 11
4.6 UVM Verification Component 12
4.6.1 UVC for AXI4 Master 12
4.6.2 UVC for AXI4 Slave 12
5 Result 13
5.1 handshake Process in AXI4 Protocol 14
5.2 Burst Address 14
5.3 Expected Results for Read burst 14
5.4 Expected Results for Write burst 14
6 Reference 15

You might also like