Irjet V5i3295 PDF
Irjet V5i3295 PDF
Irjet V5i3295 PDF
Key-Words: - Microprocessors, FPGA, VHDL,ISE,HDL The fig.1.shows the block diagram of easy 16 bit
microprocessor. The processor catch a mark by essential
1. INTRODUCTION pieces. There is an register array by eight 16 bit registers,
there is an arithmetic and logic unit, a shifter, a program
16 bit microprocessor contains quantity of essential modules counter, an instruction register, a comparator, an address
which is together composed the processor. The processor register, and a control unit. Each of these blocks connected
using 16 bit data bus for communicate from various blocks via a generic 16 bit tristate data bus [5]. This have 16 bit
like General purpose registers, Arithmetic logic unit, CU address bus.
(control unit), memory, comparator, program counter,
address register, instruction register and shift register. With
the development into integrated circuit technology the
strength of the processor get increased tremendously.
Microprocessors are extensively used into the embedded
sector rooted on general purpose application and special
purpose application. Microprocessors are used in
instruments to make it intelligent using behavioral encoding.
The CPU design by various sections which is beneficial in
performing diffrent functions.
A microprocessor is programmable tool it Take in digital The Prime VHDL component part is the Arithmetic and logic
data inputs, procedure that according from the instruction unit or ALU. The ALU is the basic building block by the
stored into that memory and supply effect as output. that central processing unit from a computer. Depend into where
may be look as a programmable logic device it may be used the ALU is designed that manage make the CPU much
to command a growth either until turn on/off devices. The effective. that execute a deal of arithmetic and logical
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International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 03 | Mar-2018 www.irjet.net p-ISSN: 2395-0072
operations similar similarly add and subtract and some Determines which shift operation to perform. The shift
logical manipulation such as AND, OR, and XOR. entity can perform a shift left, shift right, also rotate left, also
rotate right operation.
B. Comparator
G. Tri register
The comparator match two values also returns a „1‟ or „0‟
depend at the sample by comparison.The compare method is The tri register is related towards the data bus also can
chosen through the significance of input port sel. through stand information through the data bus also into the same
input a and b are similar set the value eq since port sel. time expedition information by the data bus.
through ports a and b go through the common value, the port
output returns „1‟ and if only the values are not equal, 2. COMPOSITION AND TESTING:
certainly output returns „0‟.
The ALU inputs A also B are the two input buses at which the
C. Control ALU manipulation are featured. Output bus C regress the
result by the ALU operation.Input select (sel) patch up which
The control section supplies the essential signal to texture of the arithmetic either logical operation is performed.
the data flow properly via the CPU also perform the required
functions. Into the program the architecture contains a state Set input operation
machine so causes each convenient signal tariff to update
rooted towards the present state also input signals also 0000 Addition
making a next state instead of the state machine. The 0001 Substraction
command get a some inputs also a lot by outputs. 0010 Multipication
Perform each of the states instead of an instruction 0011 Division
executions the essential moves from complete the 0100 Anding
instruction.
0101 Oring
D. Register 0110 Xoring
0111 Noring
The register section is applied instead of the address register
1000 Xnoring
also the instruction register. These registers are applied
from hold at the input data on a increase edge by the clock
input also drive output with the hold data.This contains Table 1.ALU Function Table
three ports. Port is the input port also q is the output port.
Port clk (clock) controls as the data is picked into the The table displays the comparison modes and values. every
register entity. When a flourish edge happens towards input operations function into two input values also return a single
clock, the tariff by input a is fixed since output q. This also bit output. present bit is applied to command the stream by
accept 1 nanosecond obstacle to remove delta obstacle manipulation inside the processor as long as executing
problems till simulation. instructions. The comparator lie by a large case statement
where all branch to the case statement contains a IF. If state
E. Register Array tested is real, a „1‟ value is fixed; else „0‟ is fixed. Every
statement take place after 1nanosecond to discard delta
The reg array block is used until through the set of registers delay problems.
inside the CPU in order to used, To store intermediate tariff
during instruction. From write a location into the reg array
elected input sel (select) from the location since to be
written , input data through the data until be written , also
set a increase edge in the input clk (clock). since read a
location by reg array, set input sel until the location towards
get read and set input en to a „1‟; the data is output on port
q.
F. Shift
© 2018, IRJET | Impact Factor value: 6.171 | ISO 9001:2008 Certified Journal | Page 1305
International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 03 | Mar-2018 www.irjet.net p-ISSN: 2395-0072
The suitable work from the processor is validated. The [3] Volnei A . Pedroni “Circuit Design & Simulation
simulation result demonstrate so the processor is eligible by with VHDL, 2nd Edition
implementing the given modules into the design.through the
programming keep done in VHDL, an VHDL simulator is [4] Brown, Digital Logic with VHDL Design
applied to test the functionality by the CPU. The VHDL RTL
report by the CPU is spurious by a task VHDL simulator. This [5] Stephen Brown;V Zvonko “ Fundamentals of
way we keep used Model Sim SE 6.5 simulator also xilinx ISE digital logic with VHDL”,Mc Graw Hill International
13.2. An simulator requirement two inputs, the description 2ndEdition,2006
through the design also the stimulus until drive the design.
[6] Charles H,Roth,Jr,”Digital System Design using
occasionally formation are self-stimulating also not require
VHDL,2nd Edition
any external stimulus, but at most state VHDL designers
utilization a VHDL test bench of one kind either another until [7] Mark Z wolinski, “Digital System Design with
drive the design entity tested. VHDL” Prentice Hall, 2000
3. CONCLUSIONS
REFERENCES:
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