Digital Logic Design Laboratory Manual: Objective

WOLKITE UNIVERSITY

COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
DIGITAL LOGIC DESIGN LABORATORY MANUAL

Lab 1: LOGIC GATES
Objective
To get acquainted with different standard integrated circuits (ICs).
To study the basic logic gates: AND, OR, INVERT, NAND, NOR, and XOR.
To understand formulation of Boolean function and truth table for logic circuits.
Apparatus
Analog/Digital Training System

IC Type 7400 Quadruple 2-input NAND gates
IC Type 7402 Quadruple 2-input NOR gates
IC Type 7404 Hex Inverters
IC Type 7408 Quadruple 2-input AND gates
IC Type 7432 Quadruple 2-input OR gates
IC Type 7486 Quadruple 2-input XOR gate
Theory
Analog/Digital Training System:
The Analog/Digital Training System consists of DC power supply, breadboard, pulse generator
and a digital probe.
Useful features include:
1. DC Power Supply:
Fixed DC Outputs: +5V & -5V
Variable DC Outputs: +3V to +15V, -3V to -15V
2. Breadboard:
Terminal strips arranged for easy connection of standard ICs
3. Pulse Generator:
Variable duty cycle: (set to 50%)
Frequency range: 1Hz 10MHz
Amplitude: 0VP-P - 10 VP-P
4. Digital Probe
Digital logic design Lab
Page 1
Digital Integrated ICs

Digital ICs are a collection of resistors, diodes and transistors fabricated on a single piece of
semiconductor material usually silicon and referred to as chip. The chip is enclosed in a
protective plastic or ceramic package with pins extended out for connecting the IC to other
devices. The most common type of package is a dual-in-line package (DIP) as shown in figure
1.1. The pins are numbered counterclockwise when viewed from the top of the package with
respect to an identifying notch or dot at on end of the chip. The DIP below is a 14-pin package.
16, 20, 24, 28, 40 and 64 pin packages are also available.
The fabricated resistors, diodes and transistors reside in the chip are called logic gates. Different
chip may contain different amount of these logic gates.
Fig. 1.1: (a) Dual-In-Line Package (b) Top view showing Pin numbers
Page 2
Fig. 1.2: The complete designed and connected circuit

Basic Logic Gates
1. AND A multi-input circuit in which the output is 1 only if all inputs are 1.
2. OR A multi-input circuit in which the output is 1 when any input is 1.
3. INVERT The output is 0 when the input is 1, and the output is 1 when the input is 0.
4. NAND AND followed by INVERT.
5. NOR OR followed by INVERT.
6. EX-OR The output of the Exclusive OR gate, is 0 when its two inputs are the same and
its output is 1 when its two inputs are different.
Truth Table Representation of the output logic levels of a logic circuit for every possible
combination of levels of the inputs. This is best done by means of a systematic tabulation.
PROBLEM
Implement 3 input AND gate using 2 input AND gates and 3 input OR gate using 2 input
OR gates.
Implement NAND gate using AND gates and NOR using OR gates
Study DE Morgans theorem and its implementation
Learn the implementation of Universal gates
Page 3
LAB 2: HALF ADDER, FULL ADDER, DECODER, ENCODER MULTIPLEXER AND

DEMULTIPLEXER
Half adder:
A half adder has two inputs for the two bits to be added and two outputs one from the sum S and
other from the carry c into the higher adder position. Above circuit is called as a carry signal from
the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.
(1) Construct the half adder circuit shown and complete the truth table for all combinations of
inputs A and B.
(2) Determine the Boolean expressions for the SUM and CARRY outputs
SUM =________________________________________________
CARRY = _____________________________________________
(3) How many bits can the circuit ADD at the same time?
(4) What is the limitation of the half adder circuit?
(5) Implement half adder in lab and verify its operation.
Full adder
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so.
In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.
Page 4
(1) Construct the full adder circuit shown below using XOR, AND and OR gates and complete
the truth table for all combinations of inputs.
(2) Implement full adder in lab and verify its operation.

DECODERS
AIM: To realize a decoder circuit using basic gates and to verify IC 74LS139
Learning Objective:
To learn about working principle of decoder
To learn and understand the working of IC 74LS139
To realize using basic gates as well as universal gates
COMPONENTS REQUIRED:
IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Connecting Patch chords, & IC
Trainer Kit
THEORY:
A decoder is a combinational circuit that connects the binary information from n input lines to
a maximum of 2n unique output lines.
Page 5
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
Outputs the device has 2 enable inputs (Two active low).
MULTIPLEXER AND DEMULTIPLEXER

AIM: To design and set up the following circuit
To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
To design and set up a 1:4 DE multiplexer (DE-MUX) using only NAND gates.
To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
Learning objective
To learn about various applications of multiplexer and de-multiplexer
To learn and understand the working of IC 74153 and IC 74139
To learn to realize any function using Multiplexer
THEORY
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit
that is selected. The general multiplexer circuit has 2n input signals, n control/select signals and
1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of
Page 6
selection signals. The general de-multiplexer circuit has 1 input signal, n control/select signals
and 2n output signals. De-multiplexer circuit can also be realized using a decoder circuit with
enable.
Components Required:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Connecting Patch Cords & IC Trainer
Kit.
i)
4:1 MULTIPLEXER
ii)
1:4 DE-MULTIPLEXER
Labs 3 FLIP FLOPS

AIM: Truth Table verification of
R-S type Flip Flop.
D type Flip Flop.
J-K Flip Flop.
Page 7
LEARNING OBJECTIVE:
To learn about various Flip-Flops
To learn and understand the working of Master slave FF
To learn about applications of FFs
COMPONENTS REQUIRED:
IC 7408, IC 7404, IC 7402, IC 7400, Connecting Patch Cords & IC Trainer Kit.
THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The latch
(flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits. Usually
there are two outputs, Q and its complementary value.
Some of the most widely used latches are listed below.
SR LATCH:
An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design
using cross-coupled NAND gates as shown. The truth tables of the circuits are shown below. A
clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
enabled S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter.
When the clock is high, the output follows the D input, and when the clock goes low, the state is
latched.
Page 8

Digital Logic Design Laboratory Manual: Objective

Uploaded by

Copyright:

Available Formats

Digital Logic Design Laboratory Manual: Objective

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Logic Design Laboratory Manual: Objective

Uploaded by

Copyright:

Available Formats

WOLKITE UNIVERSITY

COLLEGE OF ENGINEERING AND TECHNOLOGY

DIGITAL LOGIC DESIGN LABORATORY MANUAL

Analog/Digital Training System

Fixed DC Outputs: +5V & -5V

Variable DC Outputs: +3V to +15V, -3V to -15V

Terminal strips arranged for easy connection of standard ICs

Variable duty cycle: (set to 50%)

Frequency range: 1Hz 10MHz

Amplitude: 0VP-P - 10 VP-P

Digital Integrated ICs

Digital logic design Lab

Fig. 1.2: The complete designed and connected circuit

Digital logic design Lab

LAB 2: HALF ADDER, FULL ADDER, DECODER, ENCODER MULTIPLEXER AND

Digital logic design Lab

(2) Implement full adder in lab and verify its operation.

MULTIPLEXER AND DEMULTIPLEXER

Labs 3 FLIP FLOPS

To learn about various Flip-Flops

To learn and understand the working of Master slave FF

To learn about applications of FFs

You might also like