IEEE 802.23af

IEEE Std 802.

3af-2003
(Amendment to IEEE Std 802.3-2002, including IEEE Std 802.3ae-2002)

IEEE Standards

802.3af
TM
IEEE Standard for Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements
Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
IEEE Computer Society

Sponsored by the LAN/MAN Standards Committee
Published by The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA 18 June 2003
Print: SH95132 PDF: SS95132
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IEEE Std 802.3af-2003

(Amendment to IEEE Std 802.3-2002, including IEEE Std 802.3ae-2002)
IEEE Standard for Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specic requirements
Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications
Amendment: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
Sponsor
LAN/MAN Standards Committee of the IEEE Computer Society

Approved 12 June 2003
IEEE-SA Standards Board

Abstract: Support for optionally powering a 10BASE-T, 100BASE-TX or 1000BASE-T DTE device via the Power Interface (PI) using physical layers defined in Clauses 14, 25, and 40. The Power Sourcing Equipment (PSE) is located at an endpoint or midspan, separate from and between the MDIs, and provides power to the Powered Device (PD) over the Link Section. The PSE detection protocol distinguishes a compatible PD from non-compatible devices and precludes the application of power and possible damage to non-compatible devices. The PSE monitors the Maintain Power Signature (MPS) and removes power when it is no longer requested or required. Optional management function requirements are specified. Keywords: 802.3af, Link Section, midspan, MPS, PD, PI, POE, power, Power over Ethernet, PSE
The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2003 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 18 June 2003. Printed in the United States of America.
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SH95132 SS95132
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Introduction to IEEE Std 802.3af-2003

[This introuduction is not part of IEEE Std 802.3af-2003, IEEE Standard for Information technology Telecommunications and information exchange between systemsLocal and metropolitan area networks Specic requirements CSMA/CD Access Method and Physical Layer Specications Amendment: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)] This amendment is part of a family of standards for local and metropolitan area networks. The relationship between the standard and other members of the family is shown below. (The numbers in the gure refer to IEEE standard numbers.1)
802.10 SECURITY
802 OVERVIEW & ARCHITECTURE*
. 802.1 MANAGEMENT
802.2 LOGICAL LINK
802.1 BRIDGING
DATA LINK LAYER
802.3 MEDIUM ACCESS 802.3 PHYSICAL
802.16 MEDIUM ACCESS 802.16 PHYSICAL PHYSICAL LAYER
* Formerly IEEE Std 802.1A.
This family of standards deals with the Physical and Data Link layers as dened by the International Organization for Standardization (ISO) Open Systems Interconnection (OSI) Basic Reference Model (ISO/IEC 7498-1: 1994). The access standards dene five types of medium access technologies and associated physical media, each appropriate for particular applications or system objectives. Some access standards have been withdrawn and other types are under investigation. The standards dening the technologies noted above are as follows: IEEE Std 8022 IEEE Std 802.1B and 802.1k [ISO/IEC 15802-2] IEEE Std 802.1D IEEE Std 802.1E [ISO/IEC 15802-4] Overview and Architecture. This standard provides an overview to the family of IEEE 802 Standards. LAN/MAN Management. Denes an OSI management-compatible architecture, and services and protocol elements for use in a LAN/MAN environment for performing remote management. Media Access Control (MAC) Bridges. Species an architecture and protocol for the interconnection of IEEE 802 LANs below the MAC service boundary. System Load Protocol. Species a set of services and protocol for those aspects of management concerned with the loading of systems on IEEE 802 LANs.
1The
IEEE standards referred to in the above gure and list are trademarks owned by the Institute of Electrical and Electronics Engineers, Incorporated. 2The IEEE 802 Overview and Architecture Specication, originally known as IEEE Std 802.1A, has been renumbered as IEEE Std 802. This has been done to accomodate recognition of the base standard in a family of standards. References to IEEE Std 802.1A should be considered as references to IEEE Std 802.
Copyright 2003 IEEE. All rights reserved.
iii
IEEE Std 802.1F IEEE Std 802.1G [ISO/IEC 15802-5] IEEE Std 802.1H [ISO/IEC TR 11802-5] IEEE Std 802.2 [ISO/IEC 8802-2] IEEE Std 802.3 IEEE Std 802.5 [ISO/IEC 8802-5] IEEE Std 802.10 IEEE Std 802.11 [ISO/IEC DIS 8802-11] IEEE Std 802.15 IEEE Std 802.16
Common Denitions and Procedures for IEEE 802 Management Information. Remote Media Access Control (MAC) Bridging. Species extensions for the interconnection, using non-LAN communication technologies, of geographically separated IEEE 802 LANs below the level of the logical link control protocol. Media Access Control (MAC) Bridging of Ethernet V2.0 in Local Area Networks. Logical Link Control. CSMA/CD Access Method and Physical Layer Specications. Token Ring Access Method and Physical Layer Specications. Interoperable LAN/MAN Security. Wireless LAN Medium Access Control (MAC) and Physical Layer Specications. Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specications for: Wireless Personal Area Networks. Standard Air Interface for Fixed Broadband Wireless Access Systems.
In addition to the family of standards, the following is a recommended practice for a common Physical Layer technology: IEEE Std 802.7 IEEE Recommended Practice for Broadband Local Area Networks.
Conformance test methodology

An additional standard, IEEE Std 1802.3 provides conformance test information for 10BASE-T.

This standard contains state-of-the-art material. The area covered by this standard is undergoing evolution. Revisions are anticipated to this standard within the next few years to clarify existing material, to correct possible errors, and to incorporate new related material.
iv
Participants
The following is a list of chairs and editors at the time the IEEE 802.3 Working Group balloted this standard:
Geoffrey O. Thompson, ChairPhase 1 Robert M. Grow, ChairPhase 2 David J. Law, Vice Chair Robert M. Grow, SecretaryPhase 1 Steven B. Carlson, SecretaryPhase 2 Steven B. Carlson, Chair, 802.3af Task Force Michael S. McCormack, EditorPhase 1, 802.3af Task Force John J. Jetzt, EditorPhase 2, 802.3af Task Force Chad M. Jones, Comment Editor, 802.3af Task Force
The following is a list of voters at the time the IEEE 802.3 Working Group balloted this standard:
Martin Adams Oscar Agazzi Don Alderrou Thomas Alexander Khaled Amer Keith Amundsen Tony Anderson Ralph Andersson Jack Andresen Mehran Ataee Phil Auld Gerard E. Bachand Andy Baldman Hugh Barrass Bob Barrett Howard Baumer Denis Beaudoin Michal Beck Mike Bennett Sidney Berglund John L. Bestel Vipul Bhatt Jeff E. Bisberg Michel Bohbot Brad Booth Paul Bottorff Gary Bourque Kirk Bovill Richard Brand Andrew Brierley-Green Rhett Brikovskis Rick Brooks Benjamin Brown Kevin Brown Steve F. Buck Lisa Buckman James Burgess Scott Burton Robert Busse Roy Bynum Donald Caldwell Richard Cam Justin Chang Xiaopeng Chen Zinan Chen Hon Wah Chin Kuen Chow George Claseman Terry Cobb Doug Coleman Rgis Colla Herb Congdon Edward Cornejo Richard Cross Brian Cruikshank Chris Cullin David Cunningham John D'Ambrosia Robert Dahlgren Kevin Daines John Dallesasse Rupert S. Dance Yair Darshan Peter Dartnell Piers Dawe Michael deBie Tom Debiec Joel Dedrick Chris Di Minico Wael Diab Thomas Dineen Hamish Dobson David W. Dol Dan Dove Daniel S. Draper Brian Drever Mike Dudek Richard Dugan David Dwelley Clay Eddings Frank J. Effenberger John Egan George Eisler Martin Elhj John F. Ewen Jean-Loup Ferrant Jens Fiedler Norival Figueira Robert G. Finch Farzin Firoozmand Alan Flatman Roger Fraser Howard Frazier Ladd Freitag Krister Frojdh Yukihiro Fujimoto Darrell Furlong Justin Gaither Denton Gentry John George Ali Ghiasi Pat Gilliland Moty Goldis Matthew Goldman Timothy D. Goodman Rich Graham Eric B. Grann C. Thomas Gray Jonathan E. Greenlaw Ajay Gummalla Michael Hackert Stephen Haddock Sharam Hakimi Farid Hamidy Johannes Hansen Del Hanson Marwan Hassoun Tom Hatley Adam Healey Ronen Heldman Itzik Hendel Ken Herrity James H. Hesson Henry Hinrichs David Hinzel Ryan Hirth Jay Hoge David W. Hyer Haruhiko Ichino Osamu Ishida Steve Jackson Michael R. Jacobson Brent Jaffa Eric Jang Woo-Hyuk Jang Jack L. Jewell Wenbin Jiang Clarence Joh David Kabal Shinkyo Kaku Mohan Kalkunte Puru Kamat Roger Karam Dave Kaufman N. Patrick Kelly John J. Kenny Dawson Kesling David E. Kohl Paul Kolesar Glen Kramer Gerard Kuyt Hans Lackner Lawrence J. Lamers William Lane Daun Langston Ryan Latchman Quang Le Eugene Lee Wesley Lee Amir Lehr Lisa Leo Robert H. Leonowich Avinoam Levy Tom Lindsay Fengkun Liu Fred A. Lucas Meilissa R. Lum Jeffrey Lynch Eric R. Lynskey Henning Lysdal Brian MacLeod Ariel Maislos David W. Martin Koichiro Mashiko Thomas Mathey Ziad Albert Matni Hideyuki Matsuo Bob Mayer Kent McCammon Philip L. McCarron Jo Beth Metzger Richard Michalowski Jacob (Kobi) Mizrahi Fred Mohamadi Dirk S. Mohl Cindy Montstream Paul B. Moore Robert Moore Shohei Moriwaki Robert Muir Shimon Muller Denis Murphy Thomas Murphy Brian Murray Gerard Nadeau Ken Naganuma
Hari Naidu Karl Nakamura Nersi Nazari Kristian Nelson Paul Nikolich Michael Nootbaar Bob Noseworthy Satoshi Obara Stephen Oh Peter Ohln Toshio Ooka Philip Orlik George Oughton Robert R. Pace Don Pannell Elwood T. Parsons Dipak M. Patel Alex Pavlovsky John Payne Petar Pepeljugoski Gerry Pesavento Armin Pitzer Timothy R. Plunkett Jeff Porter William Quackenbush Jim Quilici Patrick W. Quinn
John Quirk Rick Rabinovich Jurgen Rahn Naresh Raman Jennifer G. Rasimas Dan Rausch Peter Rautenberg Maurice Reintjes Lawrence Rennie Ramez Rizk Shawn Rogers Dan Romascanu Tume Rmer Floyd Ross Larry Rubin Hyunsurk Ryu Dolors Sala Anthony Sanders Mark Sankey Akira Sasaki Raj Savara Klaus Schulz Peter Schwartz Khorvash Sedvash Steve Selee Koichiro Seto Vadim Shain
Robbie Shergill Jian Song Patrick H. Stanley Nick Stapleton Claus Stetter Donald S. Stewart Dean M. Stoddart Mario Stoltz Hiroshi Suzuki Daniel Svensson Steve Swanson Tad Szostak Rich Taborek Bharat Tailor Akio Tajima Mike Tate Pat Thaler R. Jonathan Thatcher Walter Thirion Bruce Tolley Paul Torgerson Rick Townsend Edward Turner Bulent Tusiray Bor-long Twu Sterling A. Vaden Schelto van Doorn
Peter Van Laanen Erik van Oosten Vinod Kumar Venkatavaraton Ramakrishna Vepa Grard Vergnaud David Vogel Martin Wagner Tim Warland Jeff Warren Ted Washburn Fred Weniger Tony Whitlow Bill Wiedemann John Wolcott King Won Shin-Hee Won David Wong Edward Wong Leo Wong Percy Wong Stefan M. Wurster Doug Yoder Jason Yorks Leonard Young Hank Zannini Bob Zona
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The following members of the balloting committee voted on this revision of the standard. Balloters may have voted for approval, disapproval, or abstention.
Ilian Atias Jacob Ben Ary Benjamin Brown Scott Burton Jeff Cain Steven B. Carlson Yawgeng Chau Keith Chow Chris Cullin Guru Dutt Dhingra Yair Darshan Wael Diab Christopher T. Diminico Thomas Dineen Dr. Sourav Dutta David McLean Dwelly Mordechai Goldis Rich Graham Robert M. Grow Stephen Haddock Khosrow Haratian Marian Hargis Steven M. Hemmah Peeya Iwagoshi Raj Jain John J. Jetzt Chad Jones Roger A. Karam E. S. Kramer William Lane David J. Law Pi-Cheng Law Amir Lehr Daniel Levesque Vincent Lipsio Jeff Lynch Jose Morales Ahmad Mahinfallah Kyle Maus Patrick McCaughey Michael McCormack Steve Methley George Miao Joseph Moran Robert Muir Ken Naganuma Paul Nikolich Bob O'Hara Satoshi Obara Donald R. Pannell Subbu Ponnuswamy Vikram Punj Maurice Reintjes Thomas Ruf Frederick Schindler Charles Spurgeon Clay Stocklin Steven Swanson Pat Thaler Geoffrey O. Thompson Jerry Thrasher Sterling Vaden Oren Yuen
When the IEEE-SA Standards Board approved this standard on 12 June 2003, it had the following membership: Don Wright, Chair Howard M. Frazier, Vice Chair Judith Gorman, Secretary
H. Stephen Berger Joe Bruder Bob Davis Richard DeBlasio Julian Forster* Toshio Fukuda Arnold M. Greenspan Raymond Hapeman Donald M. Heirman Laura Hitchcock Richard H. Hulett Anant Jain Lowell G. Johnson Joseph L. Koepnger* Tom McGean Steve Mills Daleep C. Mohla William J. Moylan Paul Nikolich Gary Robinson Malcolm V. Thaden Geoffrey O. Thompson Doug Topping Howard L. Wolfman
*Member Emeritus
Also included are the following nonvoting IEEE-SA Standards Board liaisons:
Alan Cookson, NIST Representative Satish K. Aggarwal, NRC Representative
Catherine Berger IEEE Standards Project Editor
vii
Contents
REVISIONS TO IEEE Std 802.3-2002 1. (Changes to) Introduction .................................................................................................................... 2 1.4 (Changes to) Definitions .............................................................................................................. 2 1.5 (Changes to) Abbreviations ......................................................................................................... 2 14. (Changes to) Twisted-pair medium attachment unit (MAU) and baseband medium, type 10BASE-T.................................................................................................................................... 3 (Changes to) Reconciliation Sublayer (RS) and Media Independent Interface (MII) ......................... 4 (Changes to) 10 Mb/s, 100 Mb/s, 1000 Mb/s, and 10 Gb/s Management ........................................... 6 30.1 (Changes to) Overview .............................................................................................................. 6 30.9 Management for Power Sourcing Equipment (PSE) ............................................................... 11 30.10 Layer management for Midspan ............................................................................................. 14 40. (Changes to) Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 1000BASE-T........................................................................................ 17
22. 30.
ANNEXES (Changes to) Annex 30A (normative) GDMO specification for IEEE 802.3 managed object classes ......... 18 (Changes to) Annex 30B (normative) GDMO and ASN.1 definitions for management............................... 26
NEW MATERIAL TO IEEE Std 802.3-2002 33.Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)27 33.1 Overview.................................................................................................................................... 27 33.2 Power sourcing equipment......................................................................................................... 29 33.3 Powered devices......................................................................................................................... 49 33.4 Additional Electrical specifications ........................................................................................... 57 33.5 Environmental............................................................................................................................ 66 33.6 Management function requirements .......................................................................................... 67 33.7 Protocol Implementation Conformance Statement (PICS) proforma for Clause 33, DTE Power via MDI.................................................................................................................. 71 Annex 33A (informative) PSE Detection of PDs ......................................................................................... 86 Annex 33B (informative) Cabling guidelines............................................................................................... 89 Annex 33C (informative) Recommended test configurations and procedures............................................. 90 33C.1Recommended PSE output test procedures ....................................................................... 91
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33C.2Recommended PSE AC disconnect-detection test procedures........................................ 104 33C.3Recommended PSE detection signature test procedures ................................................. 107 33C.4Recommended PD detection signature test procedures ................................................... 110 33C.5Recommended PD power supply test procedures............................................................ 113 Annex 33D (informative) PSE-PD stability ............................................................................................... 117 33D.1 Recommended PSE design guidelines and test setup ..................................................... 117 33D.2 Recommended PD design guidelines.............................................................................. 119 Annex 33E (informative) Cabling resistance unbalance ........................................................................... 120
ix
List of special symbols

For the benet of those who have received this document by electronic means, what follows is a list of special symbols and operators. All special symbols and operators are taken from the SYMBOL font set supported on most Windows, MacIntosh, and UNIX systems. If any of these symbols or operators fail to print out correctly on your machine, the editors apologize, and hope that this table will at least help you to sort out the meaning of the resulting funny-shaped blobs and strokes. Special symbols formed from the SYMBOL font set may be prepared in the following way: First, change to SYMBOL font. There is an entry under Format, Characters for this purpose. Then, while continuously holding down the ALT key, enter the three- or four-digit code using the numbers on your numeric keypad (the NumLock feature must be ON for this to work). Alternatively, cut and paste the symbols you need from this page. Those editors who are using Mac or UNIX may use window pull-down menus to insert symbol-font characters. Special symbols and operators
Frame V character code ALT-042 ALT-043 ^ ALT-033 ALT-060 ALT-0163 ALT-061 ALT-0185 ALT-0179 ALT-062 ALT-0220 ALT-0206 ALT-0207 ALT-0177 ALT-0176 ALT-0229 Ctrl-q Shft-q Ctrl-q Shft-p ALT-0134 ALT-0135
Printed Character
Meaning Boolean AND Boolean OR, Arithmetic addition Boolean XOR Boolean NOT Less than Less than or equal to Equal to Not equal to Greater than or equal to Greater than Assignment operator Indicates membership Indicates nonmembership Plus or minus (a tolerance) Degrees (as in degrees Celsius) Summation Big dash (Em dash) Little dash (En dash) Dagger Double dagger
Font Symbol Symbol Times Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Symbol Times Times Times Times
+
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< = >
IEEE Standard for Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specic requirements
Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications
Amendment: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
[These changes are part of IEEE Std 802.3-2002.] EDITORIAL NOTEThis amendment is based on the current edition of IEEE Std 802.3-2002 plus changes incorporated by IEEE Std 802.3ae-2002. The editing instructions dene how to merge the material contained here into this base document set to form the new comprehensive standard as created by the addition of IEEE Std 802.3ae-2002. Editing instructions are shown in bold italic. Four editing instructions are used: change, delete, insert, and replace. Change is used to make small corrections in existing text or tables. The editing instruction species the location of the change and describes what is being changed either by using strikethrough (to remove old material) or underscore (to add new material). Delete removes existing material. Insert adds new material without disturbing the existing material. Insertions may require renumbering. If so, renumbering instructions are given in the editing instruction. Editorial notes will not be carried over into future editions. Replace is used to make large changes in existing text, subclauses, tables, or gures by removing existing material and replacing it with new material. Editorial notes will not be carried over into future editions because the changes will be incorporated into the base standard.
AMENDMENT TO IEEE Std 802.3
1. Introduction
1.4 Denitions
Replace 1.4.170 with the following:
1.4.170 Medium Dependent Interface (MDI): The mechanical and electrical or optical interface between the transmission medium and the MAU (e.g., 10BASE-T) or the PHY (e.g., 1000BASE-T) and also between the transmission medium and any associated (optional per IEEE 802.3 Clause 33) Powered Device (PD) or Endpoint Power Sourcing Equipment (PSE).
Insert the following denitions alphabetically into 1.4. Renumber the denitions as required.
1.4.x Endpoint PSE: Power Sourcing Equipment (PSE) that is located at an endpoint. 1.4.x Link Section: The portion of the link from the PSE to the PD. 1.4.x Midspan: An entity located within a link segment that is distinctly separate from and between the Medium Dependent Interfaces (MDIs). 1.4.x Midspan PSE: Power Sourcing Equipment (PSE) that is located in the Midspan. 1.4.x PSE Group: A PSE or a collection of PSEs that can be related to the logical arrangement for management within an encompassing system. 1.4.x Power Interface (PI): The mechanical and electrical interface between the Power Sourcing Equipment (PSE) or Powered Device (PD) and the transmission medium. In an Endpoint PSE and in a PD the Power Interface is the MDI. 1.4.x Twisted Pair Medium Dependent Interface (TP MDI): The mechanical and electrical interface between the transmission medium and the Medium Attachment Unit (MAU) or PHY, e.g., (10BASE-T, 100BASE-TX, or 1000BASE-T). 1.4.x Power Sourcing Equipment (PSE): A DTE or midspan device that provides the power to a single link section. DTE powering is intended to provide a single 10BASE-T, 100BASE-TX, or 1000BASE-T device with a unied interface for both the data it requires and the power to process these data. 1.4.x Powered Device (PD): A device that is either drawing power or requesting power from a PSE.
1.5 Abbreviations
Insert the following items alphabetically in 1.5.
MPS PD PI PSE SELV
Maintain Power Signature Powered Device Power Interface Power Sourcing Equipment Safety Extra Low Voltage
CSMA/CD
14. Twisted-pair medium attachment unit (MAU) and baseband medium, type 10BASE-T
14.3.1.1 Isolation requirement
Change the rst paragraph of this subclause as follows:
A MAU that encompasses the PI of a PD within its MDI (see 33.1.3) shall provide isolation between all external conductors, including frame ground, and all MDI leads including those not used by 10BASE-T. A MAU that does not encompass the PI of a PD within its MDIthe MAU shall provide isolation between the DTE Physical Layer circuits including frame ground and all MDI leads including those not used by 10BASE-T. This electrical separation shall withstand at least one of the following electrical strength tests.
14.10.4.5.11 Isolation requirements

Replace item 1 of the table in this subclause with the following:
1a
Isolation, MDI leads to DTE Physical Layer circuits
14.3.1.1
Any of the three tests listed in 14.3.1.1. Function provided by MAUs that do not encompass the PI of a PD within their MDI. Any of the three tests listed in 14.3.1.1. Function provided by MAUs that encompass the PI of a PD within their MDI.
1b
Isolation, MDI leads to all external conductors
14.3.1.1
22. Reconciliation Sublayer (RS) and Media Independent Interface (MII)

22.2.4 Management functions Change the third paragraph of this subclause as follows: The MII basic register set consists of two registers referred to as the Control register (Register 0) and the Status register (Register 1). All PHYs that provide an MII shall incorporate the basic register set. All PHYs that provide a GMII shall incorporate an extended basic register set consisting of the Control register (Register 0), Status register (Register 1), and Extended Status register (Register 15). The status and control functions dened here are considered basic and fundamental to 100 Mb/s and 1000 Mb/s PHYs. Registers 2 through 1012 are part of the extended register set. The format of Registers 4 through 10 are dened for the specic Auto-Negotiation protocol used (Clause 28 or Clause 37). The format of these registers is selected by the bit settings of Registers 1 and 15. Change Table 226 as follows: Table 226MII management register set
Basic/Extended Register address Register name MII 0 1 2,3 4 5 6 7 8 9 10 11 12 1113, through 14 15 16 through 31 Control Status PHY Identier Auto-Negotiation Advertisement Auto-Negotiation Link Partner Base Page Ability Auto-Negotiation Expansion Auto-Negotiation Next Page Transmit Auto-Negotiation Link Partner Received Next Page MASTER-SLAVE Control Register MASTER-SLAVE Status Register PSE Control register PSE Status register Reserved Extended Status Vendor Specic B B E E E E E E E E E E E Reserved E B B E E E E E E E E E E E B E GMII
CSMA/CD
22.2.4.3 Extended capability registers Change the rst paragraph of this subclause as follows: In addition to the basic register set dened in 22.2.4.1 and 22.2.4.2, PHYs may provide an extended set of capabilities that may be accessed and controlled via the MII management interface. ElevenNine registers have been dened within the extended address space for the purpose of providing a PHY-specic identier to layer management, and to provide control and monitoring for the Auto-Negotiation process, and to provide control and monitoring of power sourcing equipment. Add the following two new subclauses after subclause 22.2.4.3.8 and renumber current subclause 22.2.4.3.9 as 22.2.4.3.11. 22.2.4.3.9 PSE Control register (Register 11) Register 11 provides control bits that are used by a PSE. See 33.6.1.1. 22.2.4.3.10 PSE Status register (Register 12) Register 12 provides status bits that are supplied by a PSE. See 33.6.1.2.
30. 10 Mb/s, 100 Mb/s, 1000 Mb/s and 10 Gb/s Management

30.1 Overview
Change the rst paragraph of this subclause as follows: This clause provides the Layer Management specication for DTEs, repeaters, and MAUs, and Midspans based on the CSMA/CD access method. The clause is produced from the ISO framework additions to Clause 5, Layer Management; Clause 19, Repeater Management; and Clause 20, MAU Management. It incorporates additions to the objects, attributes, and behaviors to support 100 Mb/s, 1000 Mb/s and 10 Gb/s, full duplex operation, MAC Control, and Link Aggregation and DTE Power via MDI. 30.1.1 Scope Change the rst paragraph of this subclause as follows: This clause includes selections from Clauses 5, 19, and 20. It is intended to be an entirely equivalent specication for the management of 10 Mb/s DTEs, 10 Mb/s baseband repeater units, and 10 Mb/s integrated MAUs. It also includes the additions for management of MAC Control, DTEs and repeaters at speeds greater than 10 Mb/s, embedded MAUs, and PHYs and DTE Power via MDI. Implementations of management for DTEs, repeater units, and embedded MAUs should follow the requirements of this clause (e.g., a 10 Mb/s implementation should incorporate the attributes to indicate that it is not capable of 100 or 1000 Mb/s operation,; half duplex DTE should incorporate the attributes to indicate that it is not capable of full duplex operation, etc.). 30.1.2 Relationship to objects in IEEE 802.1F Change the second paragraph of this subclause as follows: oResourceTypeID This object class is mandatory and shall be implemented as defined in IEEE 802.1F. This object is bound to oMAC-Entity, oRepeater, oMidSpan and oMAU as defined by the NAME BINDINGs in 30A.8.130A.10.1. Note that the binding to oMAU is mandatory only when MII is present. The Entity Relationship Diagrams, Figures 303 and 304, shows these bindings pictorially. 30.1.4 Management model Change the second last paragraph of this subclause as follows: The above items are dened in 30.3, 30.4, 30.5, 30.6, 30.7 and 30.8 through 30.10 of this clause in terms of the template requirements of ISO/IEC 10165-4: 1991. 30.2.2.1 Text description of managed objects Insert the following text immediately after the description of oWIS: oMidSpan The top-most managed object class of the Midspan containment tree shown in Figure 304. Note that this managed object class may be contained within another superior managed object class. Such containment is expected, but is outside the scope of this standard.
CSMA/CD
oPSEGroup The PSE Group managed object class is a view of a collection of PSEs. oPSE The managed object of that portion of the containment trees shown in Figure 303 and Figure 304. The attributes and actions defined in this subclause are contained within the oPSE managed object. 30.2.3 Containment Change the rst paragraph of this subclause as follows: A containment relationship is a structuring relationship for managed objects in which the existence of a managed object is dependent on the existence of a containing managed object. The contained managed object is said to be the subordinate managed object, and the containing managed object the superior managed object. The containment relationship is used for naming managed objects. The local containment relationships among object classes are depicted in the entity relationship diagrams, Figure 303 and Figure 30 4. This These gures shows the names of the object classes and whether a particular containment relationship is one-to-one or one-to-many. For further requirements on this topic, see IEEE Std 802.1F-1993. PSE management is only valid in a system that provides management at the next higher containment level, that is, either a DTE, repeater or Midspan with management.
Replace the existing Figure 303 with the following new gure:
oAggregator 30.7.1
oAggregationPort 30.7.2
oAggPortStats 30.7.3
oAggPortDebugInformation 30.7.4
oRepeater 30.4.1
oMACControlEntity 30.3.3
oResourceTypeID
oGroup 30.4.2
oMACEntity 30.3.1
oMACControlFunctionEntity 30.3.4
oRepeaterPort 30.4.3
oPHYEntity 30.3.2
oResourceTypeID
oPSE 30.9.1
oMAU 30.5.1
oMAU 30.5.1
oPSE 30.9.1
oResourceTypeID Present if MII Repeater System
oAutoNegotiation 30.6.1
oAutoNegotiation 30.6.1
oResourceTypeID Present if MII DTE System
oWIS 30.8.1
Denotes one-to-many relationship Denotes one-to-one relationship
Figure 303Repeater and DTE System Eentity relationship diagram
CSMA/CD
Insert new Figure 304 as follows:
oMidSpan 30.10.1
oResourceTypeID
oPSEGroup 30.10.2
oPSE 30.9.1 Midspan system
Denotes one-to-many relationship Denotes one-to-one relationship
Figure 304Midspan entity relationship diagram
30.2.5 Capabilities Change the rst paragraph of this subclause as follows: This standard makes use of the concept of packages as dened in ISO/IEC 10165-4: 1992 as a means of grouping behaviour, attributes, actions, and notications within a managed object class denition. Packages may either be mandatory, or be conditional, that is to say, present if a given condition is true. Within this standard capabilities are dened, each of which corresponds to a set of packages, which are components of a number of managed object class denitions and which share the same condition for presence. Implementation of the appropriate basic and mandatory packages is the minimum requirement for claiming conformance to IEEE 802.3 Management. Implementation of an entire optional capability is required in order to claim conformance to that capability. The capabilities and packages for IEEE 802.3 Management are specied in Tables 301, 302 and 303 through 304. Insert the following paragraphs at the end of this subclause: For managed PSEs, the PSE Basic Package is mandatory and the PSE Recommended Package is optional. For a managed PSE to be conformant to this standard, it shall fully implement the PSE Basic Package. For a managed PSE to be conformant to the optional Recommended Package it shall implement that entire package. PSE management is optional with respect to all other CSMA/CD management. For managed Midspans, the Midspan managed object class shall be implemented in its entirety. All attributes and notications are mandatory. Midspan management is optional with respect to all other CSMA/CD management.
Insert the following new table after Table 303: Table 304PSE Capabilities
oResourceTypeID managed object aResourceTypeIDName aResourceInfo oMidSpan managed object class (30.10.1) aMidSpanID aMidSpanPSEGroupCapacity aMidSpanPSEGroupMap nMidSpanPSEGroupMapChange oPSEGroup managed object class (30.10.2) aPSEGroupID aPSECapacity aPSEMap nPSEMapChange oPSE managed object class (30.9.1) aPSEID aPSEAdminState aPSEPowerPairsControlAbility aPSEPowerPairs aPSEPowerDetectionStatus aPSEPowerClassification aPSEInvalidSignatureCounter aPSEPowerDeniedCounter aPSEOverLoadCounter aPSEShortCounter aPSEMPSAbsentCounter acPSEAdminControl Common Attributes Template aCMCounter ATTRIBUTE GET X ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ATTRIBUTE ACTION GET GET GET GET-SET GET GET GET GET GET GET GET X X X X X X X X X X X X ATTRIBUTE ATTRIBUTE ATTRIBUTE NOTIFICATION GET GET GET X X X X ATTRIBUTE ATTRIBUTE ATTRIBUTE NOTIFICATION GET GET GET X X X X ATTRIBUTE ATTRIBUTE GET GET X X
10
PSE Basic Package (Mandatory) PSE Recommended Package (Optional) Midspan Basic Capability (Mandatory)
CSMA/CD
Insert the following subclause after subclause 30.8
30.9 Management for Power Sourcing Equipment (PSE)

30.9.1 PSE managed object class This subclause formally denes the behaviours for the oPSE managed object class attributes and actions. 30.9.1.1 PSE attributes 30.9.1.1.1 aPSEID ATTRIBUTE APPROPRIATE SYNTAX: INTEGER BEHAVIOUR DEFINED AS: The value of aPSEID is assigned so as to uniquely identify a PSE among the subordinate managed objects of the containing object.; 30.9.1.1.2 aPSEAdminState ATTRIBUTE APPROPRIATE SYNTAX: An ENUMERATED VALUE that has one of the following entries: enabled PSE functions enabled disabled PSE functions disabled BEHAVIOUR DEFINED AS: A read-only value that identies the operational state of the PSE functions. An interface which can provide the PSE functions specified in Clause 33 will be enabled to do so when this attribute has the enumeration enabled. When this attribute has the enumeration disabled the interface will act as it would if it had no PSE function. The operational state of the PSE function can be changed using the acPSEAdminControl action. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the PSE Enable bit specified in 33.6.1.1.3.; 30.9.1.1.3 aPSEPowerPairsControlAbility ATTRIBUTE APPROPRIATE SYNTAX: BOOLEAN BEHAVIOUR DEFINED AS: Indicates the ability to control which PSE Pinout Alternative (see 33.2.2) is used for PD detection and power. When true the PSE Pinout Alternative used can be controlled through the aPSEPowerPairs attribute. When false the PSE Pinout Alternative used cannot be controlled through the aPSEPowerPairs attribute. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Pair Control Ability bit specified in 33.6.1.2.10; 30.9.1.1.4 aPSEPowerPairs ATTRIBUTE APPROPRIATE SYNTAX: An ENUMERATED VALUE that has one of the following entries:
11
signal spare
PSE Pinout Alternative A PSE Pinout Alternative B
BEHAVIOUR DEFINED AS: A read-write value that identies the supported PSE Pinout Alternative specified in 33.2.2. A GET operation returns the PSE Pinout Alternative in use. A SET operation changes the PSE Pinout Alternative used to the indicated value only if the attribute aPSEPowerPairsControlAbility is true. If the attribute aPSEPowerPairsControlAbility is false a SET operation has no effect. The enumeration signal indicates that PSE Pinout Alternative A is used for PD detection and power. The enumeration spare indicates that PSE Pinout Alternative B is used for PD detection and power. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Pair Control bits specified in 33.6.1.1.2.; 30.9.1.1.5 aPSEPowerDetectionStatus ATTRIBUTE APPROPRIATE SYNTAX: An ENUMERATED VALUE that has one of the following entries: disabled PSE disabled searching PSE searching deliveringPower PSE delivering power test PSE test mode fault PSE fault detected otherFault PSE implementation specific fault detected BEHAVIOUR DEFINED AS: A read-only value that indicates the current status of the PD Detection function specified in 33.2.6. The enumeration disabled indicates that the PSE State diagram (Figure 336) is in the state DISABLED. The enumeration deliveringPower indicates that the PSE State diagram is in the state POWER_ON. The enumeration test indicates that the PSE State diagram is in the state TEST_MODE. The enumeration fault indicates that the PSE State diagram is in the state TEST_ERROR. The enumeration otherFault indicates that the PSE State diagram is in the state IDLE due to the variable error_condition = true. The enumeration searching indicates the PSE State diagram is in a state other than those listed above. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the PSE Status bits specified in 33.6.1.2.9.
NOTEA derivative attribute may wish to apply a delay to the use of the deliveringPower enumeration as the PSE state diagram will enter then quickly exit the POWER_ON state if a short-circuit or overcurrent condition is present when power is rst applied.;
30.9.1.1.6 aPSEPowerClassication ATTRIBUTE APPROPRIATE SYNTAX: An ENUMERATED VALUE that has one of the following entries: class0 Class 0 PD class1 Class 1 PD class2 Class 2 PD class3 Class 3 PD class4 Class 4 PD BEHAVIOUR DEFINED AS: A read-only value that indicates the PD Class of a detected PD as specied in 33.2.7.2.
12
CSMA/CD
This value is only valid while a PD is being powered, that is the attribute aPSEPowerDetectionStatus reporting the enumeration deliveringPower. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the PD Class bits specied in 33.6.1.2.8.; 30.9.1.1.7 aPSEInvalidSignatureCounter ATTRIBUTE APPROPRIATE SYNTAX: Generalized nonresettable counter. This counter has a maximum increment rate of 2 counts per second. BEHAVIOUR DEFINED AS: This counter is incremented when the PSE state diagram (Figure 336) enters the state SIGNATURE_INVALID. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Invalid Signature bit specied in 33.6.1.2.4.; 30.9.1.1.8 aPSEPowerDeniedCounter ATTRIBUTE APPROPRIATE SYNTAX: Generalized nonresettable counter. This counter has a maximum increment rate of 2 counts per second. BEHAVIOUR DEFINED AS: This counter is incremented when the PSE state diagram (Figure 336) enters the state POWER_DENIED. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Power Denied bit specied in 33.6.1.2.2.; 30.9.1.1.9 aPSEOverLoadCounter ATTRIBUTE APPROPRIATE SYNTAX: Generalized nonresettable counter. This counter has a maximum increment rate of 2 counts per second. BEHAVIOUR DEFINED AS: This counter is incremented when the PSE state diagram (Figure 336) enters the state ERROR_DELAY_OVER. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Overload bit specied in 33.6.1.2.6.; 30.9.1.1.10 aPSEShortCounter ATTRIBUTE APPROPRIATE SYNTAX: Generalized nonresettable counter. This counter has a maximum increment rate of 2 counts per second. BEHAVIOUR DEFINED AS: This counter is incremented when the PSE state diagram (Figure 336) enters the state ERROR_DELAY_SHORT. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the Short Circuit bit specied in 33.6.1.2.5.;
13
30.9.1.1.11 aPSEMPSAbsentCounter ATTRIBUTE APPROPRIATE SYNTAX: Generalized nonresettable counter. This counter has a maximum increment rate of 2 counts per second. BEHAVIOUR DEFINED AS: This counter is incremented when the PSE state diagram (Figure 336) transitions directly from the state POWER_ON to the state IDLE due to tmpdo_timer_done being asserted. If a Clause 22 MII or Clause 35 GMII is present, then this will map to the MPS Absent bit specied in 33.6.1.2.7.; 30.9.1.2 PSE actions 30.9.1.2.1 acPSEAdminControl ACTION APPROPRIATE SYNTAX: Same as aPSEAdminState BEHAVIOUR DEFINED AS: This action provides a means to alter aPSEAdminState.;
30.10 Layer management for Midspan

30.10.1 Midspan managed object class This subclause formally denes the behaviours for the oMidSpan managed object class, attributes, and notications. 30.10.1.1 Midspan attributes 30.10.1.1.1 aMidSpanID ATTRIBUTE APPROPRIATE SYNTAX: INTEGER BEHAVIOUR DEFINED AS: The value of aMidSpanID is assigned so as to uniquely identify a Midspan device among the subordinate managed objects of system (systemID and system are defined in ISO/IEC 10165-2: 1992 [SMI]).; 30.10.1.1.2 aMidSpanPSEGroupCapacity ATTRIBUTE APPROPRIATE SYNTAX: INTEGER BEHAVIOUR DEFINED AS: The aMidSpanPSEGroupCapacity is the number of PSE groups that can be contained within the Midspan device. Within each managed Midspan device, the PSE groups are uniquely numbered in the range from 1 to aMidSpanPSEGroupCapacity. Some PSE groups may not be present in a given Midspan instance, in which case the actual number
14
CSMA/CD
of PSE groups present is less than aMidSpanPSEGroupCapacity. The number of PSE groups present is never greater than aMidSpanPSEGroupCapacity.; 30.10.1.1.3 aMidSpanPSEGroupMap ATTRIBUTE APPROPRIATE SYNTAX: BITSTRING BEHAVIOUR DEFINED AS: A string of bits which reflects the current configuration of PSE groups that are viewed by PSE group managed objects. The length of the bitstring is aMidSpanPSEGroupCapacity bits. The first bit relates to PSE group 1. A 1 in the bitstring indicates presence of the PSE group, 0 represents absence of the PSE group.; 30.10.1.2 Midspan notications 30.10.1.2.1 nMidSpanPSEGroupMapChange NOTIFICATION APPROPRIATE SYNTAX: BITSTRING BEHAVIOUR DEFINED AS: This notification is sent when a change occurs in the PSE group structure of a Midspan device. This occurs only when a PSE group is logically removed from or added to a Midspan device. The nMidSpanPSEGroupMapChange notification is not sent when powering up a Midspan device. The value of the notification is the updated value of the aMidSpanPSEGroupMap attribute.; 30.10.2 PSE Group managed object class This subclause formally denes the behaviours for the oPSEGroup managed object class, attributes, actions, and notications. 30.10.2.1 PSE Group attributes 30.10.2.1.1 aPSEGroupID ATTRIBUTE APPROPRIATE SYNTAX: INTEGER BEHAVIOUR DEFINED AS: A value unique within the Midspan device. The value of aPSEGroupID is assigned so as to uniquely identify a PSE group among the subordinate managed objects of the containing object (oMidSpan). This value is never greater than aMidSpanPSEGroupCapacity.; 30.10.2.1.2 aPSECapacity ATTRIBUTE APPROPRIATE SYNTAX: INTEGER BEHAVIOUR DEFINED AS: The aPSECapacity is the number of PSEs contained within the PSE group. Valid range is 11024.
15
Within each PSE group, the PSEs are uniquely numbered in the range from 1 to aPSECapacity. Some PSEs may not be present in a given PSE group instance, in which case the actual number of PSEs present is less than aPSECapacity. The number of PSEs present is never greater than aPSECapacity.; 30.10.2.1.3 aPSEMap ATTRIBUTE APPROPRIATE SYNTAX: BitString BEHAVIOUR DEFINED AS: A string of bits that reflects the current configuration of PSE managed objects within this PSE group. The length of the bitstring is aPSECapacity bits. The first bit relates to PSE 1. A 1 in the bitstring indicates presence of the PSE, 0 represents absence of the PSE.; 30.10.2.2 PSE Group notications 30.10.2.2.1 nPSEMapChange NOTIFICATION APPROPRIATE SYNTAX: BitString BEHAVIOUR DEFINED AS: This notification is sent when a change occurs in the PSE structure of a PSE group. This occurs only when a PSE is logically removed from or added to a PSE group. The nPSEMapChange notification is not sent when powering up a Midspan device. The value of the notification is the updated value of the aPSEMap attribute.;
16
CSMA/CD
40. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 1000BASE-T
40.6.1.1 Isolation requirement
Change the rst paragraph of this subclause as follows:
A PHY that encompasses the PI of a PD within its MDI (see 33.1.3) shall provide isolation between all external conductors, including frame ground (if any), and all MDI leads. A PHY that does not encompass the PI of a PD within its MDIThe PHY shall provide electrical isolation between the port device circuits, including frame ground (if any) and all MDI leads. This electrical separation shall withstand at least one of the following electrical strength tests: 40.12.2 Major capabilities/options
Insert the following row at the bottom (following item AXO) of the table:
*PD
Powered Device
40.6.1.1
Yes [ ] No [ ]
PHY encompasses the PI of a PD within its MDI.
40.12.7 PMA Electrical Specications

Change the second row (item PME15) of the table in this subclause as follows:
PME15a
The PHY shall provide electrical isolation between
40.6.1.1
!PD:M
Yes [ ] N/A [ ]
The port device circuits including frame ground, and all MDI leads.
Insert a row between the second and third rows (between items PME15 and PME16) of the table in this subclause as follows:
PME15b
The PHY shall provide electrical isolation between
40.6.1.1
PD:M
Yes [ ] N/A [ ]
All external conductors, including frame ground, and all MDI leads.
17
Annex 30A
(normative)
GDMO specification for IEEE 802.3 managed object classes

Change the rst paragraph of this annex as follows: This annex formally denes the protocol encodings for CMIP and ISO/IEC 15802-2: 1995 [ANSI/IEEE Std 802.1B and 802.1k, 1995 Edition] for the IEEE 802.3 Managed Objects using the templates specied in ISO/IEC 10165-4: 1992. The application of a GDMO template compiler against 30A.1 to 30A.1530A.18 will produce the proper protocol encodings.
30A.10.1 ResourceTypeID, formal denition

Insert the following paragraph at the end of this subclauses: nbResourceTypeID-midSpan NAME BINDING
SUBORDINATE OBJECT CLASS IEEE802.1F:oResourceTypeID; NAMED BY SUPERIOR OBJECT CLASS oMidSpan AND SUBCLASSES; WITH ATTRIBUTE aMidSpanID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) resourceTypeID-midSpan(25)}; Insert the following subclauses after subclause 30A.15.2:
30A.16 PSE managed object class

30A.16.1 PSE, formal denition
oPSE DERIVED FROM CHARACTERIZED BY pPSEBasic ATTRIBUTES MANAGED OBJECT CLASS CCITT Rec. X.721 (1992) | ISO/IEC 10165-2 : 1992:top; PACKAGE aPSEID aPSEAdminState aPSEPowerPairsControlAbility aPSEPowerPairs aPSEPowerDetectionStatus acPSEAdminControl;
GET, GET, GET, GET-REPLACE, GET;
ACTIONS ; ; CONDITIONAL PACKAGES pPSERecommended ATTRIBUTES
PACKAGE aPSEPowerClassification aPSEInvalidSignatureCounter aPSEPowerDeniedCounter
GET, GET, GET,
18
CSMA/CD
aPSEOverLoadCounter GET, aPSEShortCounter GET, aPSEMPSAbsentCounter GET; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) package(4) pseRecommendedPkg(27)}; PRESENT IF The recommended package is implemented; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) managedObjectClass(3) pseObjectClass(15)}; nbPSE-repeaterPortName NAME BINDING
SUBORDINATE OBJECT CLASS oPSE; NAMED BY SUPERIOR OBJECT CLASS oRepeaterPorts AND SUBCLASSES; WITH ATTRIBUTE aPSEID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) pse-repeaterPortName(26)}; nbPSE-dteName NAME BINDING
SUBORDINATE OBJECT CLASS oPSE; NAMED BY SUPERIOR OBJECT CLASS oPHYEntity AND SUBCLASSES; WITH ATTRIBUTE aPSEID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) pse-dteName(27)}; nbPSE-pseGroupName NAME BINDING
SUBORDINATE OBJECT CLASS oPSE; NAMED BY SUPERIOR OBJECT CLASS oPSEGroup AND SUBCLASSES; WITH ATTRIBUTE aPSEID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) pse-pseGroupName(28)};
30A.16.2 PSE attributes

aPSEID ATTRIBUTE WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.OneOfName; MATCHES FOR EQUALITY; BEHAVIOUR bPSEID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseID(209)}; bPSEID DEFINED AS aPSEAdminState WITH ATTRIBUTE SYNTAX MATCHES FOR BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.1; ATTRIBUTE IEEE802Dot3MgmtAttributeModule.PortAdminState; EQUALITY;
19
BEHAVIOUR REGISTERED AS
bPSEAdminState; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseAdminState(210)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.2; ATTRIBUTE IEEE802Dot3MgmtAttributeModule.PairCtrlAbility; EQUALITY; bPSEPowerPairsControlAbility; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) psePowerPairsControlAbility(211)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.3; ATTRIBUTE IEEE802Dot3MgmtAttributeModule.PSEPowerPairs; EQUALITY; bPSEPowerPairs; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) psePowerPairs(212)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.4; ATTRIBUTE
bPSEAdminState DEFINED AS aPSEPowerPairsControlAbility WITH ATTRIBUTE SYNTAX MATCHES FOR BEHAVIOUR REGISTERED AS
bPSEPowerPairsControlAbility DEFINED AS aPSEPowerPairs WITH ATTRIBUTE SYNTAX MATCHES FOR BEHAVIOUR REGISTERED AS
bPSEPowerPairs DEFINED AS aPSEPowerDetectionStatus
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.DetectStatus; MATCHES FOR EQUALITY; BEHAVIOUR bPSEPowerDetectionStatus; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) psePowerDetectionStatus(214)}; bPSEPowerDetectionStatus DEFINED AS aPSEPowerClassication BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.5; ATTRIBUTE
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.PowerClass; MATCHES FOR EQUALITY; BEHAVIOUR bPSEPowerClassication; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) psePowerClassication(215)};
20
CSMA/CD
bPSEPowerClassication DEFINED AS aPSEInvalidSignatureCounter DERIVED FROM MATCHES FOR BEHAVIOUR REGISTERED AS
BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.6; ATTRIBUTE aCMCounter; EQUALITY; bPSEInvalidSignatureCounter; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7)pseInvalidSignatureCounter(227)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.7; ATTRIBUTE aCMCounter; EQUALITY; bPSEPowerDeniedCounter; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7)psePowerDeniedCounter(228)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.8; ATTRIBUTE aCMCounter; EQUALITY; bPSEOverLoadCounter; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7)pseOverLoadCounter(229)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.9; ATTRIBUTE aCMCounter; EQUALITY; bPSEShortCounter; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7)pseShortCounter(230)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.10;
bPSEInvalidSignatureCounter DEFINED AS aPSEPowerDeniedCounter DERIVED FROM MATCHES FOR BEHAVIOUR REGISTERED AS
bPSEPowerDeniedCounter DEFINED AS aPSEOverLoadCounter DERIVED FROM MATCHES FOR BEHAVIOUR REGISTERED AS
bPSEOverLoadCounter DEFINED AS aPSEShortCounter DERIVED FROM MATCHES FOR BEHAVIOUR REGISTERED AS
bPSEShortCounter DEFINED AS
21
aPSEMPSAbsentCounter DERIVED FROM MATCHES FOR BEHAVIOUR REGISTERED AS
ATTRIBUTE aCMCounter; EQUALITY; bPSEMPSAbsentCounter; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseMPSAbsentCounter(217)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.1.11;
bPSEMPSAbsentCounter DEFINED AS
30A.16.3 PSE actions

acPSEAdminControl BEHAVIOUR MODE WITH INFORMATION SYNTAX REGISTERED AS ACTION bPSEAdminControl; CONFIRMED; IEEE802Dot3MgmtAttributeModule.PortAdminState; {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) action(9) pseAdminControl(13)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.9.1.2.1;
bPSEAdminControl DEFINED AS
30A.17 Midspan managed object class

oMidSpan DERIVED FROM CHARACTERIZED BY pMidSpanBasic ATTRIBUTES MANAGED OBJECT CLASS CCITT Rec. X.721 (1992) | ISO/IEC 10165-2 : 1992:top; PACKAGE aMidSpanID GET, aMidSpanPSEGroupCapacity GET, aMidSpanPSEGroupMap GET; nMidSpanPSEGroupMapChange;
NOTIFICATIONS ; ; REGISTERED AS
{iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) managedObjectClass(3) midSpanObjectClass(17)}; NAME BINDING
nbMidSpanName
SUBORDINATE OBJECT CLASS oMidSpan; NAMED BY SUPERIOR OBJECT CLASS ISO/IEC 10165-2 :system AND SUBCLASSES; WITH ATTRIBUTE aMidSpanID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) midSpanName(31)};
22
CSMA/CD
nbMidSpanMonitor
NAME BINDING
SUBORDINATE OBJECT CLASS IEEE802.1F :oEWMAMetricMonitor; NAMED BY SUPERIOR OBJECT CLASS ISO/IEC 10165-2 :system AND SUBCLASSES; WITH ATTRIBUTE IEEE802.1F:aScannerId; CREATE WITH-AUTOMATIC-INSTANCE-NAMING; DELETE ONLY-IF-NO-CONTAINED-OBJECTS; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) midSpanMonitor(32)};
30A.17.1 Midspan attributes

aMidSpanID ATTRIBUTE
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.OneOfName; MATCHES FOR EQUALITY; BEHAVIOUR bMidSpanID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) midSpanID(221)}; bMidSpanID DEFINED AS aMidSpanPSEGroupCapacity BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.1.1.1; ATTRIBUTE
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.OneOfName; MATCHES FOR EQUALITY,ORDERING; BEHAVIOUR bMidSpanPSEGroupCapacity; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) midSpanPSEGroupCapacity(222)}; bMidSpanPSEGroupCapacity DEFINED AS aMidSpanPSEGroupMap BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.1.1.2; ATTRIBUTE
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.BitString; MATCHES FOR EQUALITY; BEHAVIOUR bMidSpanPSEGroupMap; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) midSpanPSEGroupMap(223)}; bMidSpanPSEGroupMap DEFINED AS BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.1.1.3;
30A.17.2 Midspan notications nMidSpanPSEGroupMapChange BEHAVIOUR NOTIFICATION bMidSpanPSEGroupMapChange;
23
WITH INFORMATION SYNTAX IEEE802Dot3-MgmtAttributeModule.BitString; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) notification(10)midSpanPSEGroupMapChange(8)}; bMidSpanPSEGroupMapChange DEFINED AS BEHAVIOUR
See BEHAVIOUR DEFINED AS in 30.10.1.2.1;
30A.18 PSE Group managed object class

oPSEGroup DERIVED FROM CHARACTERIZED BY pPSEGroupBasic ATTRIBUTES MANAGED OBJECT CLASS CCITT Rec. X.721 (1992) | ISO/IEC 10165-2 : 1992:top; PACKAGE aPSEGroupID aPSECapacity aPSEMap nPSEMapChange;
GET, GET, GET;
NOTIFICATIONS ; ; REGISTERED AS
{iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) managedObjectClass(3) midSpanGroupObjectClass(18)}; NAME BINDING
nbPSEGroupName
SUBORDINATE OBJECT CLASS oPSEGroup; NAMED BY SUPERIOR OBJECT CLASS oMidSpan AND SUBCLASSES; WITH ATTRIBUTE aPSEGroupID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) nameBinding(6) pseGroupName(33)};
30A.18.1 PSE Group attributes

aPSEGroupID ATTRIBUTE
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.OneOfName; MATCHES FOR EQUALITY; BEHAVIOUR bPSEGroupID; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseGroupID(224)}; bPSEGroupID DEFINED AS aPSECapacity WITH ATTRIBUTE SYNTAX MATCHES FOR BEHAVIOUR BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.2.1.1; ATTRIBUTE IEEE802Dot3-MgmtAttributeModule.OneOfName; EQUALITY,ORDERING; bPSECapacity;
24
CSMA/CD
REGISTERED AS
{iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseCapacity(225)}; BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.2.1.2; ATTRIBUTE
bPSECapacity DEFINED AS aPSEMap
WITH ATTRIBUTE SYNTAX IEEE802Dot3-MgmtAttributeModule.BitString; MATCHES FOR EQUALITY; BEHAVIOUR bPSEMap; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) attribute(7) pseMap(226)}; bPSEMap DEFINED AS BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.2.1.3;
30A.18.2 PSE Group notications

nPSEMapChange NOTIFICATION
BEHAVIOUR bPSEMapChange; WITH INFORMATION SYNTAX IEEE802Dot3-MgmtAttributeModule.BitString; REGISTERED AS {iso(1) member-body(2) us(840) ieee802dot3(10006) csmacdmgt(30) notification(10)pseMapChange(9)}; bPSEMapChange DEFINED AS BEHAVIOUR See BEHAVIOUR DEFINED AS in 30.10.2.2.1;
25
Annex 30B
(normative)
GDMO and ASN.1 definitions for management

30B.2 ASN.1 module for CSMA/CD managed objects
Insert the following ASN.1 denitions into the ASN.1 module, in appropriate alphabetic sequence:
CurrentStatus ::= ENUMERATED { MPSAbsent (0), ok (1) } DetectStatus ::= ENUMERATED { disabled (0), searching (1), deliveringPower (2), test (3), fault (4), otherFault (5) } PairCtrlAbility ::=BOOLEAN PowerClass ::= ENUMERATED { class0 (0), class1 (1), class2 (2), class3 (3), class4 (4) }
-- MPS absent -- MPS present and over current not detected
-- PSE disabled -- PSE searching -- PSE delivering power -- PSE test mode -- PSE fault detected -- PSE implementation specific fault detected
-- Class 0 PD -- Class 1 PD -- Class 2 PD -- Class 3 PD -- Class 4 PD
PSEPowerPairs ::= ENUMERATED { signal (0), -- PSE Pinout Alternative A spare (1) -- PSE Pinout Alternative B }
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CSMA/CD
33. Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
NOTEAlthough this clause existed in previous publications of IEEE Std 802.3, it was reserved for future use and therefore contained no information. All information in this clause is new material.
33.1 Overview
This clause denes the functional and electrical characteristics of two optional power (non-data) entities, a Powered Device (PD) and Power Sourcing Equipment (PSE), for use with the physical layers dened in Clauses 14, 25, and 40. These entities allow devices to supply/draw power using the same generic cabling as is used for data transmission. DTE powering is intended to provide a 10BASE-T, 100BASE-TX, or 1000BASE-T device with a single interface to both the data it requires and the power to process these data. This clause species the following: a) b) c) d) e) A power source to add power to the 100 balanced cabling system, The characteristics of a powered devices load on the power source and the structured cabling, A protocol allowing the detection of a device that requires power, Optionally, a method to classify devices based on their power needs, and A method for scaling supplied power back to the detect level when power is no longer requested or required.
The importance of item c) above should not be overlooked. Given the large number of legacy devices (both IEEE 802.3 and other types of devices) that could be connected to a 100 balanced cabling system, and the possible consequences of powering such devices, the protocol to distinguish compatible devices and noncompatible devices is important to prevent damage to non-compatible devices. The detection and powering algorithms are likely to be compromised by cabling that is multi-point as opposed to point-to-point, resulting in unpredictable performance and possibly damaged equipment. This clause differentiates between the two ends of the powered portion of the link, dening the PSE and the PD as separate but related devices. 33.1.1 Objectives The following are the objectives of Power via MDI: a) b) c) PowerA PD designed to the standard, and within its range of available power, can obtain both power and data for operation through the MDI and therefore need no additional connections. SafetyA PSE designed to the standard will not introduce non-SELV (Safety Extra Low Voltage) power into the wiring plant. CompatibilityClause 33 utilizes the existing MDIs of 10BASE-T, 100BASE-TX, and 1000BASE-T without modication and adds no signicant requirements to the cabling. The use of other IEEE 802.3 MDIs is beyond the scope of this clause. SimplicityThe powering system described here is no more burdensome on the end users than the requirements of 10BASE-T, 100BASE-TX, or 1000BASE-T.
d)
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33.1.2 Compatibility considerations All implementations of PD and PSE systems shall be compatible at their respective Power Interfaces (PIs) when used in accordance with the restrictions of Clause 33 where appropriate. Designers are free to implement circuitry within the PD and PSE in an application-dependent manner provided that the respective PI specications are satised. 33.1.3 Relationship of Power via MDI to the IEEE 802.3 Architecture Power via MDI comprises an optional non-data entity. As a non-data entity it does not appear in a depiction of the OSI Reference Model. Figure 331 depicts the positioning of Power via MDI in the case of the PD.
PHYSICAL INTERFACE CIRCUITRY PHY PD
MDI/PI MEDIUM MDI = MEDIUM DEPENDENT INTERFACE PD = POWERED DEVICE PHY = PHYSICAL LAYER DEVICE PI = POWER INTERFACE
Figure 331DTE Power via MDI powered device relationship to the physical interface circuitry and the IEEE 802.3 CSMA/CD LAN model Figure 332 and Figure 333 depict the positioning of Power via MDI in the cases of the Endpoint PSE and the Midspan PSE, respectively.
PHYSICAL INTERFACE CIRCUITRY PHY PSE
MDI/PI MEDIUM MDI = MEDIUM DEPENDENT INTERFACE PHY = PHYSICAL LAYER DEVICE PI = POWER INTERFACE PSE = POWER SOURCING EQUIPMENT
Figure 332DTE Power via MDI endpoint power sourcing equipment relationship to the physical interface circuitry and the IEEE 802.3 CSMA/CD LAN model
28
CSMA/CD
PHY MDI MEDIUM PI
PSE
4-PAIR SHEATH
MDI = MEDIUM DEPENDENT INTERFACE PHY = PHYSICAL LAYER DEVICE PI = POWER INTERFACE PSE = POWER SOURCING EQUIPMENT
Figure 333DTE Power via MDI midspan power sourcing equipment relationship to the physical interface circuitry and the IEEE 802.3 CSMA/CD LAN model Any device that contains an MDI compliant with Clause 14, Clause 25, and/or Clause 40, and sinks and/or sources power in accordance with the specications of this clause is permitted. The Power Interface (PI) is the generic term that refers to the mechanical and electrical interface between the PSE or PD and the transmission medium. In an Endpoint PSE and in a PD the PI is encompassed within the MDI. PSE power interface specications that are dened at the MDI apply to an Endpoint PSE. They may or may not apply to a Midspan PI.
33.2 Power sourcing equipment

PSE, as the name implies, is the equipment that provides the power to a single link section. The PSEs main functions are to search the link section for a PD, optionally classify the PD, supply power to the link section (only if a PD is detected), monitor the power on the link section, and scale power back to the detect level when power is no longer requested or required. An unplugged link section is one instance when power is no longer required. A PSE is electrically specied at the point of the physical connection to the cabling. Characteristics, such as the losses due to overvoltage protection circuits, or power supply inefciencies, after the PI connector are not accounted for in this specication. 33.2.1 PSE location PSEs may be placed in two locations with respect to the link segment, either coincident with the DTE/ Repeater or midspan. A PSE that is coincident with the DTE/Repeater is an Endpoint PSE. A PSE that is located within a link segment that is distinctly separate from and between the MDIs is a Midspan PSE. The requirements of this document shall apply equally to Endpoint and Midspan PSEs unless the requirement contains an explicit statement that it applies to only one implementation. See Figure 334. Endpoint PSEs may support either Alternative A or B, or both. Endpoint PSEs can be compatible with 10BASE-T, 100BASE-TX and/or 1000BASE-T. Midspan PSEs shall use Alternative B. Midspan PSEs are limited to operation with 10BASE-T and 100BASE-TX systems. Operation of Midspan PSEs on 1000BASE-T systems is beyond the scope of this standard.
29
Switch/Hub
Data pair
Powered End Station

Data pair
Power Sourcing Equipment (PSE)
Powered Device (PD)
Data pair
Data pair
Endpoint PSE, Alternative A
Switch/Hub
Data pair
Powered End Station

Data pair
Powered Device (PD)
Data pair
Data pair
Endpoint PSE, Alternative B

Non-PSE Switch/Hub
Data pair Midspan Power Insertion Equipment
Powered End Station

Data pair
Powered Device (PD)
Data pair
Data pair
Midspan PSE, Alternative B

Figure 334PSE location overview
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CSMA/CD
33.2.2 PI pin assignments A PSE device may provide power via one of two valid four-wire connections. In each four-wire connection, the two conductors associated with a pair each carry the same nominal current in both magnitude and polarity. Figure 335, in conjunction with Table 331, illustrates the valid alternatives. Table 331PSE pinout alternatives
Alternative A (MDI-X) Negative VPort Negative VPort Positive VPort Alternative A (MDI) Positive VPort Positive VPort Negative VPort Positive VPort Positive VPort Positive VPort Negative VPort Negative VPort Negative VPort Alternative B (All)
Conductor 1 2 3 4 5 6 7 8
12
34
56
78
Figure 335PD and PSE eight-pin modular jack
For the purposes of data transfer, the type of PSE data port is relevant to the far-end PD and in some cases to the cabling system between them. Therefore, Alternative A matches the positive voltage to the transmit pair of the PSE. PSEs that use automatically-conguring MDI/MDI-X (Auto MDI-X) ports may choose either polarity choice associated with Alternative A congurations. For further information on the placement of MDI vs. MDI-X, see 14.5.2. A PSE shall implement Alternative A or Alternative B, or both, provided the PSE meets the constraints of 33.2.3. Implementers are free to implement either alternative or both. While a PSE may be capable of both Alternative A and Alternative B, PSEs shall not operate both Alternative A and Alternative B on the same link segment simultaneously.
31
33.2.3 PSE state diagrams The PSE state diagrams specify the externally observable behavior of a PSE. Equivalent implementations that present the same external behavior are allowed. The PSE shall provide the behavior of the state diagrams shown in Figure 336 and Figure 337. 33.2.3.1 Overview Detection, classication, and power turn-on timing shall meet the specications in Table 335. The PSE shall turn on power after a valid detection in less than Tpon as specied in Table 335, if power is to be applied. If the PSE cannot supply power within Tpon, it shall initiate and successfully complete a new detection cycle before applying power. It is possible that two separate PSEs, one that implements Alternative A and one that implements Alternative B (see 33.2.1), may be attached to the same link segment. In such a conguration, and without the required backoff algorithm, the PSEs could prevent each other from ever detecting a PD by interfering with the detection process of the other. After a PSE that is performing detection using Alternative B fails to detect a valid PD detection signature, the PSE shall back off no less than Tdbo as specied in Table 335 before attempting another detection. During this backoff, the PSE shall not apply a voltage greater than 2.8Vdc to the PI. A PSE that is performing Alternative B detection shall not resume detection mode until at least one backoff cycle has elapsed. If a PSE that is performing detection using Alternative B detects an open circuit (see 33.2.6.3) on the link section, then that PSE may optionally omit the detection backoff. If a PSE performing detection using Alternative A detects an invalid signature, it should initiate a second detection attempt within 1 second after the beginning of the rst detection attempt. This ensures that a PSE performing detection using Alternative A will complete a second detection cycle prior to a PSE using Alternative B that might also be present on the same Link Section, and therefore causing the invalid signature, completing its second detection cycle due to the Alternative B detection backoff described above. 33.2.3.2 Conventions The notation used in the state diagrams follows the conventions of state diagrams as described in 21.5. 33.2.3.3 Constants The PSE state diagrams use the following constants: ICUT Overload current detection range (see Table 335) ILIM Output current at short circuit condition (see Table 335) IInrush Current during inrush period of startup (see Table 335) 33.2.3.4 Variables The PSE state diagrams use the following variables:
32
CSMA/CD
error_condition A variable indicating the status of implementation-specic fault conditions that require the PSE not to source power. These error conditions are not the same conditions monitored by the state diagrams in Figure 337. Values: FALSE: No fault indication. TRUE: A fault indication exists. mr_mps_valid The PSE monitors either the DC or AC Maintain Power Signature (MPS, see 33.2.10.1). This variable indicates the presence or absence of a valid MPS. Values: FALSE: If monitoring both components of the MPS, when the DC component of MPS is absent or the AC component of MPS is absent. If monitoring only one component of MPS, that component of MPS is absent. TRUE: If monitoring both components of the MPS, the DC component of MPS and the AC component of MPS are both present. If monitoring only one component of MPS, that component of MPS is present. mr_pse_alternative This variable indicates which pinout alternative the PSE will use to apply power to the link (see Table 331). This variable is provided by a management interface that may be mapped to the PSE Control register Pair Control bits (11.3:2) or other equivalent function. Values: A: The PSE uses PSE pinout Alternative A. B: The PSE uses PSE pinout Alternative B. mr_pse_enable A control variable that selects PSE operation and test functions. This variables is provided by a management interface that may be mapped to the PSE Control register PSE Enable bits (11.1:0), as described below, or other equivalent function. Values: disable: All PSE functions disabled (behavior is as if there was no PSE functionality). This value corresponds to MDIO register bits 11.1:0 = '00'. enable: Normal PSE operation. This value corresponds to MDIO register bits 11.1:0 = '01'. force_power:Test mode selected that causes the PSE to apply power to the PI when there are no detected error conditions. This value corresponds to MDIO register bits 11.1:0 = '10'. performs_classication The performance of optional classication by the PSE is indicated by performs_classication. Values: FALSE: The PSE does not perform classication. TRUE: The PSE does perform classication. pi_powered A variable that controls the circuitry that the PSE uses to power the PD. Values: FALSE: The PSE is not to apply power to the link (default). TRUE: The PSE has detected a PD, optionally classied it, and determined the PD will be powered. power_applied A variable indicating that the PSE has begun steady state operation by having asserted pi_powered, completed the ramp of power per TRise of Table 335 and is operating beyond the startup requirements of 33.2.8.5. Values: FALSE: The PSE is either not applying power or has begun applying power but is still in startup. TRUE: The PSE has begun steady state operation. pse_available_power This variable indicates the highest power PD Class that could be supported. The value is determined in an implementation-specic manner. Values: 0: Class 1 1: Class 2 2: Class 0, Class 3 and Class 4
33
power_not_available Variable that is asserted in an implementation-dependent manner when the PSE is no longer capable of sourcing sufcient power to support the PD Class of the attached PD. Values: FALSE: PSE is capable to continue to source power to a PD. TRUE: PSE is no longer capable of sourcing power to a PD. pse_ready Variable that is asserted in an implementation-dependent manner to probe the link segment. Values: FALSE: PSE is not ready to probe the link segment. TRUE: PSE is ready to probe the link segment.
NOTECare should be taken when negating this variable in a PSE performing detection using Alternative A after an invalid signature is detected due to the delay it will introduce between detection attempts (see 33.2.3.1).
pse_reset Controls the resetting of the PSE state diagram. Condition that is TRUE until such time as the power supply for the device that contains the PSE overall state diagrams has reached the operating region. It is also TRUE when implementation specic reasons require reset of PSE functionality. Values: FALSE: Do not reset the PSE state diagram. TRUE: Reset the PSE state diagram. 33.2.3.5 Timers All timers operate in the manner described in 14.2.3.2 with the following addition. A timer is reset and stops counting upon entering a state where stop x_timer is asserted. tdbo_timer A timer used to regulate backoff upon detection of an invalid signature, see Tdbo in Table 335. tdet_timer A timer used to limit an attempt to detect a PD, see Tdet in Table 335. ted_timer A timer used to regulate a subsequent attempt to detect a PD after an error condition causes power removal, see Ted in Table 335. tlim_timer A timer used to monitor the duration of a short-circuit condition, see TLIM in Table 335. tovld_timer A timer used to monitor the duration of an overcurrent condition, see Tovld in Table 335. tmpdo_timer A timer used to monitor the dropout of the MPS, see TMPDO in Table 335. tpon_timer A timer used to limit the time for power turn-on, see Tpon in Table 335. tpdc_timer A timer used to limit the classication time, see Tpdc in Table 335. 33.2.3.6 Functions do_detection This function returns multiple variables: The variable signature as dened in 33.2.6 and the variable mr_valid_siganture. signature: This variable indicates the presence or absence of a PD. Values: open_circuit: The PSE has detected an open circuit. This value is optionally returned by a PSE performing detection using Alternative B. valid: The PSE has detected a PD requesting power. invalid: Neither open_circuit, nor valid PD detection signature has been found.
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CSMA/CD
mr_valid_signature: This variable indicates that the PSE has detected a valid signature. Values: FALSE: No valid signature detected. TRUE: Valid signature detected. do_classication This function returns multiple variables: pd_requested_power: This variable indicates the power class requested by the PD. Values: 0: Class 1 1: Class 2 2: Class 0, Class 3 or Class 4 mr_pd_class_detected: The class of the PD associated with the PD detection signature, see Table 333, 33.2.7. Class 0 is returned if an invalid classication signature is detected. Values: Class_0 Class_1 Class_2 Class_3 Class_4
35
33.2.3.7 State diagrams

mr_pse_enable = disable pse_reset + error_condition * (mr_pse_enable = enable) (mr_pse_enable = force_power) * !error_condition
DISABLED pi_powered FALSE
IDLE pi_powered FALSE mr_valid_signature FALSE
disable
mr_pse_enable
pse_ready * !power_applied * (mr_pse_enable force_power) START_DETECTION start tdet_timer do_detection mr_pd_class_detected CLASS_0 pd_requested_power 2 do_detection_done * tdet_timer_not_done DETECT_EVAL (signature = valid) * !performs_classification* start tpon_timer (pse_available_power pd_requested_power)
TEST_MODE pi_powered TRUE mr_pse_enable force_power (tlim_timer_done + tovld_timer_done) * (mr_pse_enable = force_power) TEST_ERROR pi_powered FALSE mr_pse_enable force_power tdet_timer_done
(signature = invalid) + (signature = open_circuit) (signature = valid) * performs_classification SIGNATURE_INVALID (mr_pse_alternative = B) * (signature open_circuit) BACKOFF start tdbo_timer A tbdo_timer_done A tpdc_timer_done
START_CLASSIFICATION do_classification start tpdc_timer do_classification_done
(mr_pse_alternative = A) + ((mr_pse_alternative = B) * (signature = open_circuit))
CLASSIFICATION_EVAL
(pd_requested_power > pse_available_power) * !performs_classification * (signature = valid) pd_requested_power pse_available_power pd_requested_power > pse_available_power power_not_available * tlim_timer_not_done * tovld_timer_not_done * tmpdo_timer_not_done tpon_timer_done
POWER_DENIED UCT
POWER_UP pi_powered TRUE power_applied * tpon_timer_not_done POWER_ON tlim_timer_done tlim_timer_done ERROR_DELAY_SHORT start ted_timer pi_powered FALSE B
(tmpdo_timer_done + (pse_enable = force_power)) * tlim_timer_not_done * tovld_timer_not_done * !power_not_available B tlim_timer_not_done * tolvd_timer_done ERROR_DELAY_OVER start ted_timer pi_powered FALSE ted_timer_done
ted_timer_done
Figure 336PSE state diagram
36
CSMA/CD
!power_applied
!pi_powered
!power_applied
IDLE_OVLD stop tovld_timer power_applied
IDLE_SHORT stop tlim_timer pi_powered
IDLE_MPS stop tmpdo_timer power_applied
MONITOR_OVLD stop tovld_timer
MONITOR_SHORT stop tlim_timer (I > ILIM ) * power_applied + (I > IInrush) DETECT_SHORT start tlim_timer I < ILIM
MONITOR_MPS stop tmpdo_timer !mr_mps_valid
I > ICUT DETECT_OVLD start tovld_timer I < ICUT
DETECT_MPS start tmpdo_timer mr_mps_valid
Figure 337PSE monitor overload, monitor short, and monitor MPS state diagrams
33.2.4 PD detection In an operational mode, the PSE shall not apply operating power to the PI until the PSE has successfully detected a PD requesting power. The PSE is not required to continuously probe to detect a PD signature. The period of time when a PSE is not attempting to detect a PD signature is implementation dependent. Also, a PSE may successfully detect a PD, but may then opt not to power the detected PD. PSE operation is independent of data link status. The PSE shall turn on power only on the same pairs as those used for detection.
37
33.2.5 PSE validation circuit The PSE shall detect the PD by probing via the PSE PI. The Thevenin equivalent of the detection circuit is shown in Figure 338. PSE requirements are stated for a Thevenin circuit only; they may be transformed via circuit theory into other circuit parameters in specic implementations. Zsource Vdetect+ >45K Vdetect D1 Vvalid with Valid PD Detection Signature
VdetectFigure 338PSE detection source
A functional equivalent of the detection circuit that has no source impedance limitation, but restricts the PSE detection circuit to the rst quadrant, is shown in Figure 339. Zsource D2 Vdetect+ Vdetect Vvalid with Valid PD Detection Signature
D1
VdetectFigure 339Alternative PSE detection source In Figure 338 and Figure 339, the behavior of diode D1 ensures a non-valid PD detection signature for a reversed voltage PSE to PSE connection. The open circuit voltage and short circuit current shall meet the specications in Table 332. The PSE shall not be damaged by up to 5mA backdriven current over the range of VPort as specied in Table 335. Output capacitance shall be as specied in Table 335. The PSE shall exhibit Thevenin equivalence to one of the detection circuits shown in Figure 338 or Figure 339 in all detection states. Table 332PSE PI detection mode electrical requirements
Item 1 2 3 Parameter Open circuit voltage Short circuit current Valid test voltage Symbol Voc Isc Vvalid Unit V mA V 2.8 Min Max 30 5 10 Additional information In detection mode only In detection mode only
38
CSMA/CD
Table 332PSE PI detection mode electrical requirements (continued)

Item 4 5 6 7 8 9 10 11 12 13 Parameter Voltage difference between test points Time between any two test points Slew rate Accept signature resistance Reject signature resistance Open circuit resistance Accept signature capacitance Reject signature capacitance Signature offset voltage tolerance Signature offset current tolerance Symbol Vtest TBP Vslew Rgood Rbad Ropen Cgood Cbad Vos Ios Unit V ms V/s K K K nF F V A 10 0 0 2.0 12 See Annex 33A for examples of valid signatures. 19 15 500 150 1 2 0.1 26.5 33 This timing implies a 500Hz maximum probing frequency. Min Max Additional information
33.2.5.1 Detection probe requirements The detection voltage Vdetect shall be within the Vvalid voltage range at the PSE PI as specied in Table 332 with a valid PD detection signature connected. The PSE shall make at least two measurements with Vdetect values that create at least a Vtest difference as specied in Table 332 between the two measurements with a valid PD detection signature connected.
NOTESettling time before voltage or current measurement: the voltage or current measurement should be taken after Vdetect has settled to within 1% of its steady state condition.
The PSE shall control the slew rate of the probing detection voltage when switching between detection voltages to be less than Vslew as specied in Table 332. The polarity of Vdetect shall match the polarity of VPort as dened in 33.2.1. 33.2.6 PSE detection of PDs The PSE probes the link section in order to detect a valid PD detection signature. 33.2.6.1 Detection criteria A PSE shall accept as a valid signature a link section with both of the following characteristics between the powering pairs with an offset voltage up to Vos max and an offset current up to Ios max, as specied in Table 332: a) b) Signature resistance Rgood, and Parallel signature capacitance Cgood.
39
NOTECaution, in a multiport system, the implementer should maintain DC isolation through the termination circuitry to eliminate cross-port leakage currents.
33.2.6.2 Rejection criteria The PSE shall reject link sections as having an invalid signature, when those link sections exhibit any of the following characteristics between the powering pairs, as specied in Table 332: a) b) c) Resistance less than or equal to Rbad min, or Resistance greater than or equal to Rbad max, or Capacitance greater than or equal to Cbad min.
A PSE may accept or reject a signature resistance in the band between Rgood min and Rbad min, and in the band between Rgood max and Rbad max. In instances where the resistance and capacitance meet the detection criteria, but one or both of the offset tolerances are exceeded, the detection behavior of the PSE is undened. 33.2.6.3 Open circuit criteria If a PSE that is performing detection using Alternative B (see 33.2.2) determines that the impedance at the PI is greater than Ropen as dened in Table 33-2 item 9, then it may optionally consider the link to be open circuit and omit the tdbo_timer interval. 33.2.7 PSE classication of PDs The PSE may optionally classify a PD to allow features such as load management to be implemented. If a PSE successfully completes detection of a PD, and the PSE does not classify the PD in Class 1, 2, 3, or 4, then the PSE shall assign the PD to Class 0. A successful classication of a PD requires: a) b) Successful PD detection, and subsequently, Successful Class 04 classication.
A PSE may remove power to a PD that violates the maximum power required for its advertised class. A PSE performs optional classication of a PD by applying voltage and measuring current, as specied in 33.2.7.2. The PSE classication circuit should have adequate stability to prevent oscillation when connected to a PD. 33.2.7.1 Classication power levels PDs provide information that allow a PSE to classify their power requirements. The classications are listed in Table 333. Class 4 is reserved for future use. PDs classied as Class 4 shall be treated as Class 0 for powering purposes. 33.2.7.2 PSE classication The PSE shall provide VClass between 15.5 and 20.5 volts, limited to 100 mA or less to the PI. Polarity shall be the same as dened for VPort in 33.2.2 and timing specications shall be as dened by Tpdc in Table 335. The PSE shall measure IClass and classify the PD based on the observed current according to Table 334. If the measured IClass is equal to or greater than 51mA, the PSE shall classify the PD as Class 0.
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Table 333Power classications

Minimum power levels at output of PSE 15.4 Watts 4.0 Watts 7.0 Watts 15.4 Watts Treat as Class 0
Class 0 1 2 3 4 Default Optional Optional Optional
Usage
Reserved for future use
NOTE This is the minimum power at the PSE PI. For maximum power available to PDs, see Table 3310.
Table 334PD classication

Measured IClass 0mA to 5mA > 5mA and < 8mA 8mA to 13mA > 13mA and < 16mA 16mA to 21mA > 21mA and < 25mA 25mA to 31mA > 31mA and < 35mA 35mA to 45mA > 45mA and < 51mA Class 0 May be Class 0 or 1 Class 1 May be Class 0, 1, or 2 Class 2 May be Class 0, 2, or 3 Class 3 May be Class 0, 3, or 4 Class 4 May be Class 0 or 4 Classication
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33.2.8 Power supply output When the PSE provides power to the PI, it shall conform with Table 335, Figure 336, and Figure 337. Table 335PSE output PI electrical requirements for all PD classes, unless otherwise specied
Item 1 2 3 Parameter Output voltage Load regulation Power feeding ripple and noise: f < 500Hz 500Hz to 150kHz 150KHz to 500KHz 500KHz to 1MHz 4 Maximum output current in normal powering mode at PSE min output voltage Output current in startup mode a) IDLE state current 1 b) IDLE state current 2 IPort_max Vpp Vpp Vpp Vpp mAdc 350 0.5 0.2 0.15 0.1 See 33.2.8.4 See 33.2.8.3 Symbol VPort Unit Vdc V Min 44 44 Max 57 57 Additional information See 33.2.8.1 See 33.2.8.2
5 6
IInrush IMin1 IMin2
mA mA mA
400 0 5
450 5 10
See 33.2.8.5 Relevant for 33.2.10.1.2. PSE removes power for t > TMPDO Relevant for 33.2.10.1.2. PSE may or may not remove power for t > TMPDO See 33.2.10
7a
PD Maintain Power Signature dropout time limit PD Maintain Power Signature time for validity Overload current detection range Overload time limit Output current at short circuit condition Short circuit time limit Turn on rise time Turn off time Turn off voltage Continuous Output Power
TMPDO
ms
300
400
7b
TMPS
ms
60
See 33.2.10
8 9 10 11 12 13a 13b 14
ICUT Tovld ILIM TLIM TRise TOff VOff PPort
mA ms mA ms s ms Vdc W
15400/ VPort 50 400 50 15
400 75 450 75
See 33.2.8.6 See 33.2.8.7 See 33.2.8.8 See 33.2.8.9 From 10% to 90% of VPort
500 2.8 15.4
See 33.2.8.10 See 33.2.8.11 Over the range of output voltage. Averaged over 1 second.
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Table 335PSE output PI electrical requirements for all PD classes, unless otherwise specied (continued)
Item 15 16 17 18 19 20 21 Parameter Current unbalance Power turn on time Detection backoff time Output capacitance during detection mode Detection timing Classication timing Error delay timing Symbol Iunb Tpon Tdbo Cout Tdet Tpdc Ted Unit mA ms sec nF ms ms ms 10 750 2 520 500 75 Time to complete detection of a PD. Time to classify the PD. Delay before PSE may attempt subsequent detection after power removal because of error condition. Min Max 10.5 400 Additional information See 33.2.8.12 See 33.2.8.13 PSE detection backoff time limit.
33.2.8.1 Output voltage The specication for VPort in Table 335 shall include line and temperature variations. The voltage potential shall be measured between any conductor of one power pair and any conductor of the other power pair. 33.2.8.2 Load regulation The specication for load regulation in Table 335 shall be met from 0.44W to 15.4W load step at a rate of change of 35mA/s max. The voltage transients as a result of the load changes shall be limited to 3.5V/s max. 33.2.8.3 Power feeding ripple and noise The specication for power feeding ripple and noise in Table 335 shall be met for common-mode and/or pair-to-pair noise values for power outputs from 0.44W to 15.4W at operating VPort. The limits are meant to ensure data integrity. To meet EMI standards, lower values may be needed. For higher frequencies, see 33.4.4 and 33.4.5. 33.2.8.4 Maximum output current in normal powering mode at PSE min output voltage For VPort > 44V, the minimum value for IPort_max in Table 335 shall be 15.4W/VPort. The current IPort_max ensures 15.4W min output power. The PSE shall support the following AC current waveform parameters: a) b) Ipeak = 0.4A minimum for 50ms minimum and 5% duty cycle minimum. For VPort > 44V, Ipeak = 17.6W/VPort.
33.2.8.5 Output current in startup mode The specication for IInrush in Table 335 shall be met under the following conditions: a) b) For duration of 50ms min, duty cycle = 5% min. Measurement to be taken after 1ms to ignore startup transients.
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c) d) e)
During startup, the minimum IInrush requirement applies for duration TLIM. During startup, for PI voltages above 30V, the minimum IInrush requirement is as specied in Table 335, item 5. During startup, for PI voltages between 10V and 30V, the minimum IInrush requirement is 60mA. See Figure 33C.4 and Figure 33C.6.
33.2.8.6 Overload current detection range If IPort in Table 335 exceeds ICUT for longer than Tovld, the PSE shall remove power from the PI. See Figure 33C.6. In a PSE that supports the optional classication function (33.2.7), the minimum value of ICUT may optionally be ( P_class 1000 ) Vportmin , where P_class is the minimum power level at the output of the PSE (as specied by Table 333) and Vportmin is VPort min in Table 335. 33.2.8.7 Overload time limit After time duration of Tovld as specied in Table 335, the PSE shall remove power from the PI. See Figure 33C.6. 33.2.8.8 Output currentat short circuit condition The power shall be removed from the PI within TLIM, as specied in Table 335, under the following conditions: a) b) c) Max value of the PI current during short circuit condition. Max value applies for any DC input voltage up to the maximum voltage as specied in item 1 of Table 335. Measurement to be taken after 1ms to ignore initial transients.
See Figure 33C.4 and Figure 33C.6. 33.2.8.9 Short circuit time limit If a short circuit condition is detected, power removal from the PI shall begin within TLIM and be complete by TOff, as specied in Table 335. See Figure 33C.4 and Figure 33C.6. 33.2.8.10 Turn off time The specication for TOff in Table 335 shall apply to the discharge time from VPort to 2.8Vdc with a test resistor of 320K attached to the PI. In addition, it is recommended that the PI be discharged when turned off. The PSE enters the IDLE state when VPort drops 1V below the steady-state value after the pi_powered variable is cleared (see Figure 336). The PSE remains in the IDLE state as long as the average voltage across the PI is VOff. The IDLE State is the mode when the PSE is not in Detection, Classication, or normal powering mode.
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33.2.8.11 Turn off voltage The specication for VOff in Table 335 shall apply to the PI voltage in the IDLE State. 33.2.8.12 Current unbalance The specication for Iunb in Table 335 shall apply to the current unbalance between the two conductors of a power pair over the current load range. The 10.5mA value is based on a simulated output current unbalance of 3%. 33.2.8.13 Power turn on time The specication for Tpon in Table 335 shall apply to the PSE power up time for a PD after completion of detection. If power is not applied as specied, a new detection cycle is initiated (See 33.2.3.1). 33.2.8.14 PSE stability
NOTE Caution, when connected together as a system, the PSE and PD might exhibit instability at the PSE side or the PD side or both due to the presence of negative impedance at the PD input. See Annex 33D for PSE design guidelines to ensure stable operation.
33.2.9 Power supply allocation A PSE shall not initiate power provision to a link if the PSE is unable to provide the maximum power level requested by the PD based on the PDs class. Where a PSE does not provide the optional classication function specied in 33.2.7, all PDs are treated as Class 0. The PSE may manage the allocation of power based on additional information beyond the classication of the attached PD. Allocating power based on additional information about the attached PD, and the mechanism for obtaining that additional information, is beyond the scope of this standard with the exception that the allocation of power shall not be based solely on the historical data of the power consumption of the attached PD. If the system implements a power allocation algorithm, no additional behavioral requirement is placed on the system as it approaches or reaches its maximum power subscription. Specically, the interaction between one PSE PI and another PSE PI in the same system is beyond the scope of this standard. 33.2.10 PSE power removal Figure 337 shows the PSE monitor state diagrams. These state diagrams monitor for overload current, short circuit, inrush current, and the absence of the Maintain Power Signature (MPS). If any of these conditions exists for longer than its related time limit, the power will be removed from the PI. 33.2.10.1 PSE Maintain Power Signature (MPS) requirements The MPS consists of two components, an AC MPS component and a DC MPS component. The PSE may optionally monitor the AC MPS component only, the DC MPS component only or both the AC and the DC MPS components.
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33.2.10.1.1 PSE AC MPS component requirements A PSE that monitors the AC MPS component shall meet the AC Signal parameters and PSE PI voltage during AC disconnect detection parameters in Table 336. A PSE shall consider the AC MPS component to be present when it detects an AC impedance at the PI equal to or lower than |Zac1| as dened in Table 336. A PSE shall consider the AC MPS component to be absent when it detects an AC impedance at the PI equal to or greater than |Zac2| as dened in Table 336. Power shall be removed from the PI when AC MPS has been absent for a time duration greater than TPMDO. A PSE may consider the AC MPS component to be either present or absent when it detects a AC impedance between the values |Zac1| and |Zac2| as dened in Table 336. See Figure 33C.15 for timing relationships. 33.2.10.1.2 PSE DC MPS component requirements A PSE shall consider the DC MPS component to be present if the DC current is greater than or equal to IMin2 max for a minimum of TMPS. A PSE may consider the DC MPS component to be present or absent if the DC current is in the range IMin2. A PSE shall consider the DC MPS component to be absent when it detects a DC current in the range IMin1. Power shall be removed from the PI when DC MPS has been absent for a duration greater than TMPDO. The specication for TMPS in Table 335 applies only to the DC MPS component. The PSE shall not remove power from the port when the DC current is greater than or equal to IMin2 max for at least TMPS every TMPS + TMPDO, as dened in Table 335. This allows a PD to minimize its power consumption. See Figure 33C.9 for timing relationships. Table 336PSE PI parameters for AC disconnect-detection function
Item Parameter AC signal parameters 1a PI probing AC voltage V_open Vpp 1.9 10% of the average value of VPort, 44V<VPort <60V. Includes noise, ripple, etc. V_open is the AC voltage across the PI when the PD is not connected to the PI and before the detection of this condition by the PSE. V_open1 is the AC voltage across the PI when the PD is not connected to the PI and after the detection of this condition by the PSE and the removal of power from the PI. Symbol Unit Min Max Additional information
V_open1
Vp
30V, VPort 44V.
1b 1c
AC probing signal frequency AC probing signal slew rate
Fp SR
Hz V/ s
500 0.1 Positive or negative.
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Table 336PSE PI parameters for AC disconnect-detection function (continued)

Item Parameter Symbol Unit Min Max Additional information
AC source output impedance 2a Source output current during the operation of the AC disconnect detection function PSE PI impedance during PD detection when measured at the PI of the PSE PI I_sac mA 5 During operation of the AC disconnect detection function. Specied in 33.2.5 and Figure 338. Shown here to clarify the difference in PI impedance during the signature detection function.
2b
R_rev
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PSE PI voltage during AC disconnect detection 3a 3b 3c PI AC voltage when PD is connected PI voltage when PD is disconnected Disconnect detection time VCLOSE VPort TMPDO Vpp Vp ms 60 See Table 335, item 7a. See Table 335, item 3.
AC Maintain Power Signature 4a Shall not remove power from the PI | Zac1 | K 27 Fp = 5Hz, Testing voltage >2.5V. See Figure 3310. Impedance shall have nonnegative resistive component and a net capacitive reactive component. See Figure 3311.
4b
Shall remove power from the PI
| Zac2 |
1980
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1.9V offset
Rpd_d
Zac1
Cpd_d
Figure 3310Zac1 denition as indicated in Table 336 (Rpd_d, Cpd_d specied in Table 3313. Cpd_d may be located either before or after the diode bridge.)
Zac2
Rpd
2MEG+/-1%
Figure 3311Zac2 denition as indicated in Table 336
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33.3 Powered devices

A PD is a device that is either drawing power or requesting power by participating in the PD detection algorithm. A device that is capable of becoming a powered device may or may not have the ability to draw power from an alternate power source and, if doing so, may or may not require power from the PI. PD capable devices that are neither drawing nor requesting power are also covered in this clause. A PD is specied at the point of the physical connection to the cabling. Characteristics such as the losses due to voltage correction circuits, power supply inefciencies, separation of internal circuits from external ground or other characteristics induced by circuits after the PI connector are not specied. Limits dened for the PD are specied at the PI, not at any point internal to the PD, unless specically stated. 33.3.1 PD PI The PD shall be capable of accepting power on either of two sets of PI conductors. The two conductor sets are named Mode A and Mode B. In each four-wire connection, the two wires associated with a pair are at the same nominal average voltage. Figure 335 in conjunction with Table 337 illustrates the two power modes. Table 337PD pinout
Conductor 1 2 3 4 5 6 7 8 Negative VPort , Positive VPort Negative VPort , Positive VPort Negative VPort , Positive VPort Mode A Positive VPort , Negative VPort Positive VPort , Negative VPort Negative VPort , Positive VPort Positive VPort , Negative VPort Positive VPort , Negative VPort Mode B
The PD shall be implemented to be insensitive to the polarity of the power supply and shall be able to operate per the PD Mode-A column and the PD Mode-B column in Table 337.
NOTEPDs that implement only Mode A or Mode B are specically not allowed by this standard. PDs that simultaneously require power from both Mode A and Mode B are specically not allowed by this standard.
The PD shall not source power on its PI. The PD shall withstand any voltage from 0V to 57V at the PI indenitely without permanent damage. 33.3.2 PD state diagram The PD shall provide the behavior of the state diagram shown in Figure 3312. 33.3.2.1 Conventions The notation used in the state diagram follows the conventions of state diagrams as described in 21.5.
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33.3.2.2 Variables The PD state diagram uses the following variables: pd_reset An implementation specic control variable that unconditionally resets the PD state diagram to the NOT_MDI_POWERED state. Values: FALSE: The device has not been reset (default). TRUE: The device has been reset. present_pd_signature Controls presenting the detection (see 33.3.3) and classication (see 33.3.4) signatures by the PD. Values: FALSE: The PD detection and classication signatures are not to be applied to the link. TRUE: The PD detection and classication signatures are to be applied to the link. present_mps Controls applying MPS (see 33.3.6) to the link by the PD. Values: FALSE: The Maintain Power Signature (MPS) is not to be applied to the link. TRUE: The MPS is to be applied to the link. mdi_power_required A control variable indicating the PD is enabled and should request power from the PSE by applying a PD detection signature to the link, and when the PSE sources power to apply the MPS to keep the PSE sourcing power. Values: FALSE: PD functionality is disabled. TRUE: PD functionality is enabled. power_received An indication from the circuitry that power is present on the link. Values: FALSE: Power not being received. TRUE: Power being received.
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33.3.2.3 State diagram
pd_reset
NOT_MDI_POWERED present_pd_signature FALSE present_mps FALSE mdi_power_required REQUESTING_POWER present_pd_signature TRUE power_received !mdi_power_required
MDI_POWERED present_pd_signature FALSE present_mps TRUE !mdi_power_required + !power_received NOT_REQUESTING_POWER present_pd_signature FALSE present_mps FALSE !power_received
Figure 3312PD state diagram
33.3.3 PD valid and non-valid detection signatures A PD shall present a valid detection signature at the PI between Positive VPort and Negative VPort of PD Mode A and between Positive VPort and Negative VPort of PD Mode B as dened in 33.3.1 while it is in a state where it will accept power via the PI, but is not powered via the PI. A PD shall present a non-valid detection signature at the PI between Positive VPort and Negative VPort of PD Mode A and between Positive VPort and Negative VPort of PD Mode B as dened in 33.3.1 while it is in a state where it will not accept power via the PI. When a PD becomes powered via the PI, it shall present a non-valid detection signature on the set of pairs from which is it not drawing power. The valid and non-valid detection signature regions are separated by guardbands. The guardbands for the V-I slope are the ranges 12K to 23.75K and 26.25K to 45K. A PD that presents a signature in a guardband is non-compliant. V-I slope is the effective resistance calculated from the two voltage/current measurements made during the detection process. V-I slope = (V2 V1)/(I2 I1) where (V1, I1) and (V2, I2) are measurements made at the PD PI. (331)
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The valid PD detection signature shall have the characteristics of Table 338. Table 338Valid PD detection signature characteristics, measured at PD input connector
Parameter V-I Slope (at any 1V or greater chord within the voltage range conditions) V offset I offset Input capacitance Input inductance 2.7V to 10.1 V 2.7V to 10.1 V 0.05 Conditions 2.7V to 10.1V Minimum 23.75 Maximum 26.25 Unit K
1.9 10 0.12 100
V A F H
A non-valid detection signature shall have one or both of the characteristics in Table 339 Table 339Non-valid PD detection signature characteristics, measured at PD input connector
Parameter V-I Slope Conditions V < 10.1V Range of values Either greater than 45 or less than 12 Greater than 10 Unit K F
Input Capacitance
V < 10.1V
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33.3.4 PD classications A PD may be classied by the PSE based on the classication information provided by the PD. The intent of PD classication is to provide information about the maximum power required by the PD during operation. Class 0 is the default for PDs. However, to improve power management at the PSE, the PD may opt to provide a signature for Class 1 to 3. The PD is classied based on power. The classication of the PD is the maximum power that the PD will draw across all input voltages and operational modes. A PD shall return Class 0 to 3 in accordance with the maximum power draw as specied by Table 3310. Table 3310PD power classication
Range of maximum power used by the PD 0.44 to 12.95 Watts 0.44 to 3.84 Watts 3.84 to 6.49 Watts 6.49 to 12.95 Watts Reserved for Future Use
Class 0 1 2 3 4
Usage Default Optional Optional Optional Not Allowed
NOTEClass 4 is dened but is reserved for future use. A Class 4 signature cannot be provided by a compliant PD.
In addition to a valid detection signature, PDs shall provide the characteristics of a classication signature as specied in Table 3311. A PD shall present one, and only one, classication signature during classication. Table 3311Classication signature, measured at PD input connector
Parameter Current for Class 0 Current for Class 1 Current for Class 2 Current for Class 3 Current for Class 4 Conditions 14.5V to 20.5V 14.5V to 20.5V 14.5V to 20.5V 14.5V to 20.5V 14.5V to 20.5V Minimum 0 9 17 26 36 Maximum 4 12 20 30 44 Unit mA mA mA mA mA
33.3.5 PD power The power supply of the PD shall operate within the characteristics in Table 3312.
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The PD may be capable of drawing power from a local power source. When a local power source is provided, the PD may draw some, none, or all of its power from the PI. Table 3312PD power supply limits
Item 1 2 3 4 Parameter Input voltage Input average power Input inrush current Peak operating current, Class 0, 3 Peak operating current, Class 1 Peak operating current, Class 2 5 Input current (DC or RMS), VPort=37Vdc Input current (DC or RMS), VPort=57Vdc 6 PI capacitance during normal powering mode Ripple and noise, < 500Hz Ripple and noise, 500Hz to 150KHz Ripple and noise, 150KHz to 500KHz Ripple and noise, 500KHz to 1MHz 8 a) PD Power supply turn on voltage b) PD power supply turn off voltage 9 PD classication stability time Backfeed voltage VOn VOff Tclass Vbfd Symbol VPort PPort IInrush IPort IPort IPort IPort IPort CPort Unit Vdc W mA mA Min 36 Max 57 12.95 400 400 Additional information
See 33.3.5.1 See 33.3.5.2 Peak ValueSee 33.3.5.3 See 33.3.5.4
mA
120
mA
210
mA
350
See 33.3.5.3
mA F
230
See 33.3.5.5
0.5 0.2
VPP VPP VPP VPP V
See 33.3.5.6
0.15
0.1
42
See 33.3.5.7
30
ms
See 33.3.5.8 See 33.3.5.10
10
2.8
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33.3.5.1 Input voltage The specication for VPort in Table 3312 is for the input voltage range after startup, and it includes loss in the cabling plant. The PD shall turn on at a voltage less than VOn. After the PD turns on, the PD shall stay on over the entire VPort range. The PD shall turn off at a voltage less than VPort minimum and greater than VOff. 33.3.5.2 Input average power The specication for PPort in Table 3312 shall apply for the input power averaged over 1 second. PPort = VPort IPort, measured when the PD is fed by 44V to 57V with 20 in series. 33.3.5.3 Input inrush current Input inrush current at startup will be limited by the PSE if CPort < 180F, as specied in Table 335. If CPort 180F, input inrush current shall be limited by the PD so that IInrush max is satised. 33.3.5.4 Peak operating current At any operating condition the peak current shall not exceed PPort max/VPort for more than 50ms max and 5% duty cycle max. Peak current shall not exceed IPort max. Ripple current content (Iac) superimposed on the DC current level (Idc) is allowed if the total input power is less than or equal to PPort max. The RMS, DC and ripple current shall be bounded by the following equation:
Irms = ( Idc ) 2 + ( Iac ) 2
The maximum IPort_dc and IPort_rms values for all operating VPort range shall be dened by the following equation: IPort_max [mA] =12950/VPort. 33.3.5.5 PI capacitance during normal powering mode While there is no max capacitance, the PD max input capacitance (CPort in Table 3312) and the PD input circuitry shall be designed in such a way that when a PD is connected to a PSE through a series resistance of up to 20 and the PSE voltage is changed from 44V to 57V, the peak current IPort will be as specied in Table 3312, item 4, for a maximum duration of 50ms. Input capacitance of 180F or less requires no special input considerations. 33.3.5.6 Ripple and noise The specication for ripple and noise in Table 3312 shall be for the common-mode and/or differential pairto-pair noise at the PD PI generated by the PD circuitry. The ripple and noise specication shall be for all operating voltages in the range dened by Table 3312, item 1, and over the range of input power of the device. The PD shall operate correctly in the presence of ripple and noise generated by the PSE that appears at the PD PI. These levels are specied in Table 335, item 3. Limits are provided to ensure data integrity. To meet EMI standards, lower values may be needed. The system designer is advised to assume the worst case condition in which both PSE and PD generate the maximum noise allowed by Table 335 and Table 3312, which may cause a higher noise level to appear at
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the PI than the standalone case as specied by this clause.
33.3.5.7 PD power supply turn on / turn off voltages The PD shall turn on at VOn and turn off at VOff (as specied in Table 3312) when connected to a PSE through a 20 series resistor. The PD shall turn on or off without startup oscillation and within the rst trial at any load value. 33.3.5.8 PD classication stability time The PD classication signature shall be valid within Tclass as specied in Table 3312 and remain valid for the duration of the classication period. 33.3.5.9 PD stability
NOTECaution, when connected together as a system, the PSE and PD might exhibit instability at the PSE side or the PD side or both due to the presence of negative impedance at the PD input. See Annex 33D for PD design guidelines to ensure stable operation.
33.3.5.10 Backfeed Voltage When VPort max is applied across the PI at either polarity specied on the conductors for Mode A according to Table 337, the voltage measured across the PI for Mode B with a 100K load resistor connected shall not exceed Vbfd max as specied in Table 3312. When VPort max is applied across the PI at either polarity specied on the conductors for Mode B according to Table 337, the voltage measured across the PI for Mode A with a 100K load resistor connected shall not exceed Vbfd max. 33.3.6 PD Maintain Power Signature In order to maintain power, the PD shall provide a valid Maintain Power Signature (MPS) at the PI. The MPS shall be both: a) b) Current draw equal or above the minimum Input current (IPort min) as specied in Table 3313 for a minimum duration of 75ms followed by an optional MPS dropout for no longer than 250ms, and Input impedance with resistive and capacitive components as dened in Table 3313.
A PD that does not maintain any one of: c) d) The minimum input current as dened in Table 3313 for at least 75ms, and Input impedance with resistive and capacitive components as dened by Table 3313 (also, see Figure 3310 and Figure 3311),
may have its power removed within the limits of TMPDO as specied in Table 335. Powered PDs that no longer require power shall remove both components a) and b) of the MPS. To ensure power removal, the impedance of the PI must rise above Zac2 as specied in Table 336.
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Table 3313PD Maintain Power Signature

Item 1 2 3 Parameter Input current Input resistance Input capacitance Symbol Iport Rpd_d Cpd_d Unit mA K F 0.05 10 26.25 With 0V to 57V DC bias applied Min Max Additional information See 33.3.6.1
33.3.6.1 Input current The specication for IPort in Table 3313 includes the following additional information: a) b) IPort =10mA min for Cport 180F. IPort = 10mA Cport [F] /180 for Cport > 180F, or the PD will need to make special accommodation to ensure that the 10 mA minimum current be maintained within the limits of TMPDO when the PD input voltage is dropped from 57V to 44V at the maximum allowable slew rate. Minimum current requirement applies when the PD is fed by 44V to 57V with 20 in series.
c)
33.4 Additional Electrical specications

This clause denes additional electrical specications for both the PSE and PD. The specications apply for all PSE and PD operating conditions at the cabling side of the mated connection of the PI. The requirements apply during data transmission only when specied as an operating condition. The requirements of 33.4 are consistent with the requirements of the PHYs of 10BASE-T, 100BASE-TX, and 1000BASE-T. 33.4.1 Isolation The PSE shall provide electrical isolation between the PI device circuits, including frame ground (if any), and all PI leads. The PD shall provide electrical isolation between all external conductors, including frame ground (if any), and all PI leads. This electrical isolation shall be in accordance with the isolation requirements between SELV circuits and telecommunication network connections in subclause 6.2 of IEC 60950-1:2001. This electrical isolation shall withstand at least one of the following electrical strength tests: a) b) 1500 Vrms steady-state at 50-60 Hz for 60 seconds, applied as specied in subclause 6.2 of IEC 60950-1:2001. An impulse test consisting of a 1500 V, 10/700s waveform, applied 10 times, with a 60 second interval between pulses, applied as specied in subclause 6.2 of IEC 60950-1:2001.
There shall be no insulation breakdown, as dened in subclause 6.2.2.3 of IEC 60950-1:2001. Conductive link segments that have different isolation and grounding requirements shall have those requirements provided by the port-to-port isolation of network interface devices (NID).
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33.4.1.1 Electrical isolation environments There are two electrical power distribution environments to be considered that require different electrical isolation properties. They are as follows: Environment A: When a LAN or LAN segment, with all its associated interconnected equipment, is entirely contained within a single low-voltage power distribution system and within a single building. Environment B: When a LAN crosses the boundary between separate power distribution systems or the boundaries of a single building.
33.4.1.1.1 Environment A requirements Attachment of network segments via NIDs that have multiple instances of a twisted pair MDI requires electrical isolation between each segment and the protective ground of the NID. For NIDs, the requirement for isolation is encompassed within the isolation requirements of the basic MAU/ PHY/medium standard. (See 14.3.1.1, TP-PMD, and 40.6.1.1.) Equipment with multiple instances of PSE and/or PD shall meet or exceed the isolation requirement of the MAU/PHY with which they are associated. A multi-port NID complying with Environment A requirements does not require electrical power isolation between link segments. An Environment A PSE shall switch the more negative conductor. It is allowable to switch both conductors. 33.4.1.1.2 Environment B requirements The attachment of network segments that cross environment A boundaries requires electrical isolation between each segment and all other attached segments as well as to the protective ground of the NID. For NIDs, the requirement for isolation is encompassed within the isolation requirements of the basic MAU/ PHY/medium standard (See 14.3.1.1, TP-PMD, and 40.6.1.1.). Equipment with multiple instances of PSE and/or PD shall meet or exceed the isolation requirement of the MAU/PHY with which each is associated. The requirements for interconnected electrically conducting link segments that are partially or fully external to a single building environment may require additional protection against lightning strikes or other hazards. Protection requirements for such hazards are beyond the scope of this standard. Guidance on these requirements may be found in Section 6 of IEC 60950-1:2001, as well as any local and national codes related to safety. 33.4.2 Fault tolerance Each wire pair of the PSE or PD when it is encompassed within the MDI shall meet the fault tolerance requirements of the appropriate specifying clause, (See 14.3.1.2.7, Clause 25, and 40.8.3.4). When a PSE is not encompassed within an MDI, the PSE PI shall meet the fault tolerance requirements of this subclause. The PSE PI shall withstand without damage the application of short circuits of any wire to any other wire within the cable for an indenite period of time. The magnitude of the current through such a short circuit shall not exceed ILIM max as dened in Table 335, item 10. Each wire pair shall withstand, without damage, a 1000V common-mode impulse applied at Ecm of either polarity (as indicated in Figure 3313). The shape of the impulse shall be (0.3/50)s (300ns virtual front
58
CSMA/CD
time, 50s virtual time or half value), as dened in IEC 60060, where Ecm is an externally applied AC voltage as shown in Figure 3313. PI 402 110 402 Ecm PG *Resistor matching to 1 part in 100 Figure 3313PI fault tolerance test circuit
33.4.3 Impedance balance Impedance balance is a measurement of the common-mode-to-differential-mode offset of the PI. The common-mode-to-differential-mode impedance balance for the transmit and receive pairs shall exceed: 29 17log10(/10)dB from 1.0-20 MHz for a 10 Mb/s PHY, and 34 19.2log10(/50)dB from 1.0100 MHz for a 100 Mb/s or greater PHY, where is the frequency in MHz. The impedance balance is dened as 20log10(Ecm/Edif) (334) (333) (332)
where Ecm is an externally applied AC voltage as shown in Figure 3314 and Edif is the resulting waveform due only to the applied sine wave. PI
147 Edif 143 147 Ecm
*Resistor matching to 1 part in 100 Figure 3314PI impedance balance test circuit
59
33.4.4 Common-mode output voltage The magnitude of the common-mode AC output voltage measured according to Figure 3315 and Figure 3316 at the transmit PI while transmitting data and with power applied, Ecm_out, shall not exceed 50mV peak when operating at 10Mb/s, and 50mV peak-to-peak when operating at 100Mb/s or greater. The magnitude of the common-mode AC voltage shall not exceed 50mV peak-to-peak measured at all other PIs. The frequency of the measurement shall be from 1MHz to 100MHz. PI
47.5 47.5 C**
Ecm_out 49.9 *Resistor matching 1 part in 100 **Capacitor impedance less than 1 from 1MHz to 100MHz Figure 3315Common-mode output voltage test
The PIs shall be tested with the PHY transmitting data, an operating PSE or PD, and with the following PSE load or PD source requirements: 1) When testing a PSE, the PIs that supply power are terminated as illustrated in Figure 3316. The PSE load, R, in Figure 3316 is adjusted so that the PSE output current, Iout, is 10mA and then 350mA, while measuring Ecm_out on all PIs. While testing a PD, the PIs that require power shall be terminated as illustrated in Figure 33 16. A voltage source, Vsource in Figure 3316, supplies power to the PD and is adjusted to 36Vdc and 57Vdc, while measuring Ecm_out on all PIs.
2)
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CSMA/CD
PI
Center tapped Inductor
Ed_out
47.5 47.5 C
Ecm_out
49.9
For a PSE
For a PD
Iout
DUT
R PI
+
Vsource
Ed_out
Center tapped Inductor
47.5 47.5 C
Ecm_out
49.9
Figure 3316PSE and PD terminations for common-mode output voltage test
NOTEThe Implementer should consider any applicable local, national, or international regulations that may require more stringent specications. One such specication can be found in the European Standard EN 55022:1998.
33.4.5 Pair-to-pair output noise voltage The pair-to-pair output noise voltage (see Figure 3317) will be limited by the resulting electromagnetic interference due to this AC voltage. This AC voltage can be ripple from the power supply (Table 335, item
61
3) or from any other source. A system integrating a PSE shall comply with applicable local and national codes for the limitation of electromagnetic interference. PI A
47.5 47.5 C 49.9
Pair to pair output noise voltage PI B
47.5 47.5 C 49.9
*Resistor matching 1 part in 100 Figure 3317Pair to pair output noise voltage test
33.4.6 Differential noise voltage The coupled noise, Ed_out in Figure 3316, from a PSE or PD to the differential transmit and receive pairs shall not exceed 10mV peak-to-peak measured from 1MHz to 100MHz. The PSE and PD shall be terminated as illustrated in Figure 3316 and tested with the PSE and PD conditions as specied in 33.4.4, item 1) and item 2). 33.4.7 Return loss The differential impedance of the transmit and receive pairs at the PHYs MDI shall be such that any reection shall meet the return loss requirements as specied in 14.3.1.3.4 for a 10 Mb/s PHY, in ANSI X3.263:1995 for a 100 Mb/s PHY, and 40.8.3.1 for a 1000 Mb/s PHY. In addition, all pairs terminated at an MDI should maintain a nominal common-mode impedance of 75. The common-mode termination is affected by the presence of the power supply, and this should be considered to ensure proper termination.
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CSMA/CD
33.4.8 Midspan PSE device additional requirements The cabling specications for 100 balanced cabling are described in ISO/IEC 11801-2002. Some cable category specications that only appear in earlier editions are also supported. The conguration of channel and permanent link is dened in Figure 3318.
Channel
Permanent Link
CP Link
FD
C
TO
EQP C Equipment cord C C C C Work area cable
CP
Patch cord/ Jumper cable
C C CP cable
TE
FD = floor distributor; EQP = equipment; C = connection (mated pair); CP = consolidation point; TO = telecommunications outlet; TE = terminal equipment
Figure 3318Floor distributor channel conguration
The ISO/IEC 11801 denes in 5.6.1 two types of Equipment interface to the cabling system: Interconnect model and the cross-connect model. See Figure 3319.
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Equipment cord EQP C C
Cabling sub-system
Interconnect model
Equipment cord EQP C C
Patch cord or jumper C
Cabling sub-system
Cross-connect model
Equipment cord EQP C
Midspan
C
Patch cord or jumper C
Cabling sub-system
Midspan insertion configuration C = connection
Figure 3319Interconnect model, cross-connect model, and midspan insertion conguration
The insertion of a Midspan PSE at the Floor Distributor (FD) shall comply with the following guidelines: a) If the existing FD conguration is of the Interconnect model type, the Midspan PSE can be added, provided it does not increase the length of the resulting channel to more than specied 100 meters as dened in ISO/IEC 11801. If the existing FD conguration is of the Cross-connect model type, the Midspan PSE needs to be installed instead of one of the connection pairs in the FD. In addition, the installation of the Midspan PSE shall not increase the length of the resulting channel to more than specied 100 meters as dened in ISO/IEC 11801.
b)
Congurations with the Midspan PSE in the cabling channel shall not alter the transmission requirements of the permanent link. A Midspan PSE inserted into a channel shall provide continuity for the signal pairs. A
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CSMA/CD
Midspan PSE shall not provide DC continuity between the two sides of the segment for the pairs that inject power. The requirements for the two pair category 5 channel are found in 25.4.6.
NOTEAppropriate terminations may be applied to the interrupted pairs on both sides of the midspan device.
33.4.8.1 Connector or telecom outlet Midspan PSE device transmission requirements The Midspan PSE equipment to be inserted as Connector or Telecom outlet shall meet the following transmission parameters. These parameters should be measured using the test procedures of ISO 11801:2002 for connecting hardware. 33.4.8.1.1 NEXT (Near End Crosstalk) NEXT loss is a measure of the unwanted signal coupling from a transmitter at the near-end into neighboring pairs measured at the near-end. NEXT loss is expressed in dB relative to the received signal level. NEXT loss shall be measured for Midspan PSE devices for the transmit and receive pairs from 1MHz to 100MHz and shall meet the values determined by Equation (335). However, for frequencies that correspond to calculated values greater than 65dB, the requirement reverts to the minimum requirement of 65dB. NEXTconn 40 20log(/100)dB 33.4.8.1.2 Insertion loss Insertion loss is a measure of the signal loss between the transmitter and receiver, expressed in dB relative to the received signal level. Insertion loss shall be measured for Midspan PSE devices for the transmit and receive pairs from 1MHz to 100MHz, and shall meet the values determined by Equation (336). However, for frequencies that correspond to calculated values less than 0.1dB, the requirement reverts to the maximum requirement of 0.1dB. Insertion_lossconn 0.04 SQRT() dB 33.4.8.1.3 Return loss Return loss is a measure of the reected energy caused by impedance mismatches in the cabling system and is expressed in dB relative to the reected signal level. Return loss shall be measured for Midspan PSE devices for the transmit and receive pairs from 1MHz to 100Mhz and shall meet or exceed the values specied in Table 3314. Table 3314Connector return loss
Frequency 1MHz<20MHz 20MHz100 MHz 23 dB 14 dB Return loss
(335)
(336)
33.4.8.1.4 Work area or equipment cable Midspan PSE Replacing the work area or equipment cable with a cable that includes a Midspan PSE should not alter the requirements of the cable. This cable shall meet the requirements of this clause and the specications for a
65
Category 5 (jumper) cord as specied in ISO/IEC 11801:2002 for insertion loss, NEXT, and return loss for the transmit and receive pairs.
33.5 Environmental
33.5.1 General safety All equipment meeting this standard shall conform to IEC 60950-1:2001. In particular, the PSE shall be classied as a Limited Power Source in accordance with IEC 60950-1:2001. Equipment shall comply with all applicable local and national codes related to safety. 33.5.2 Network safety This subclause sets forth a number of recommendations and guidelines related to safety concerns. The list is neither complete nor does it address all possible safety issues. The designer is urged to consult the relevant local, national, and international safety regulations to ensure compliance with the appropriate requirements. LAN cabling systems described in this clause are subject to at least four direct electrical safety hazards during their installation and use. These hazards are as follows: a) b) c) d) Direct contact between LAN components and power, lighting, or communications circuits. Static charge buildup on LAN cabling and components. High-energy transients coupled onto the LAN cabling system. Voltage potential differences between safety grounds to which various LAN components are connected.
Such electrical safety hazards must be avoided or appropriately protected against for proper network installation and performance. In addition to provisions for proper handling of these conditions in an operational system, special measures must be taken to ensure that the intended safety features are not negated during installation of a new network or during modication of an existing network. 33.5.3 Installation and maintenance guidelines It is a mandatory requirement that sound installation practice, as dened by applicable local codes and regulations, be followed in every instance in which such practice is applicable. It is a mandatory requirement that, during installation of the cabling plant, care be taken to ensure that noninsulated network cabling conductors do not make electrical contact with unintended conductors or ground. 33.5.4 Patch panel considerations It is possible that the current carrying capability of a cabling cross-connect may be exceeded by a PSE. The designer should consult the manufacturers specications to ensure compliance with the appropriate requirements. 33.5.5 Cabling resistance unbalance Resistance unbalance is a measure of the difference in resistance between the two conductors in the 100 balanced cabling system. The resistance unbalance shall be as specied in IEC 11801 Edition 2, Clause 6.4.8 (reference: 3 percent). The resistance unbalance as dened in IEC 61156-1 is
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CSMA/CD
((Rmax Rmin)/(Rmax + Rmin)) 100 percent,
(337)
where Rmax is the resistance of the conductor with the highest resistance, and Rmin is the resistance of the conductor with the lowest resistance. 33.5.6 Telephony voltages The use of building wiring brings with it the possibility of wiring errors that may connect telephony voltages to a PSE or PD. Other than voice signals, the primary voltages that may be encountered are the battery and ringing voltages. Although there is no universal standard, the following maximums generally apply: Battery voltage to a telephone line is generally 56Vdc, applied to the line through a balanced 400 source impedance. Ringing voltage is a composite signal consisting of an AC component and a DC component. The AC component is up to 175Vp at 20Hz to 60Hz with a 100 source resistance. The DC component is 56Vdc with 300 to 600 source resistance. Large reactive transients can occur at the start and end of each ring interval. Application of any of the above voltages to the PI of a PSE or a PD shall not result in any safety hazard. 33.5.7 Electromagnetic emissions The PD and PSE powered cabling link shall comply with applicable local and national codes for the limitation of electromagnetic interference. 33.5.8 Temperature and humidity The PD and PSE powered cabling link segment is expected to operate over a reasonable range of environmental conditions related to temperature, humidity, and physical handling. Specic requirements and values for these parameters are beyond the scope of this standard. 33.5.9 Labeling It is recommended that the PSE or PD (and supporting documentation) be labeled in a manner visible to the user with at least the following parameters: a) b) c) d) Power classication and power level in terms of maximum current drain over the operating voltage range, 44V to 57V, applies for PD only, Port type (e.g., 100BASE-TX, TIA Category or ISO Class), Any applicable safety warnings, and PSE or PD as appropriate.
33.6 Management function requirements

Management of the PSE is optional. If the PSE is instantiated in the same physical package as a PHY and a Clause 22 MII or a Clause 35 GMII is physically implemented, then management access shall be via the MII Management interface. Where no physical embodiment of the MII or GMII exists and management is supported, equivalent management capability shall be provided. 33.6.1 PSE registers A PSE shall use register address 11 for its control and register address 12 for its status functions.
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Some of the bits within registers are dened as latching high (LH). When a bit is dened as latching high and the condition for the bit to be high has occurred, the bit shall remain high until after it has been read via the management interface. Once such a read has occurred, the bit shall assume a value based on the current state of the condition it monitors. 33.6.1.1 PSE Control register (Register 11) (R/W) The assignment of bits in the PSE Control register is shown in Table 3315. The default value for each bit of the PSE Control register should be chosen so that the initial state of the PSE upon power up or reset is a normal operational state without management intervention. Table 3315PSE Control register bit denitions
Bit(s) 11.15:4 11.3:2 Reserved Pair Control Name Description Ignore when read (11.3) (11.2) 1 1 1 0 0 1 0 0 (11.1) (11.0) 1 1 1 0 0 1 0 0 = Reserved = PSE pinout Alternative B = PSE pinout Alternative A = Reserved = Reserved = Force Power Test Mode = PSE Enabled = PSE Disabled R/Wa RO R/W
11.1:0
PSE Enable
R/W
aR/W
= Read/Write, RO = Read Only
33.6.1.1.1 Reserved bits (11.15:4) Bits 11.15:4 are reserved for future standardization. They shall not be affected by writes and shall return a value of 0 when read. To ensure compatibility with future use of reserved bits and registers, the Management Entity should write to reserved bits with a value of 0 and ignore reserved bits on read. 33.6.1.1.2 Pair Control (11.3:2) Bits 11.3:2 report the supported PSE Pinout Alternative specified in 33.2.1. A PSE may also provide the option of controlling the PSE Pinout Alternative through these bits. Provision of this option is indicated through the Pair Control Ability (12.0) bit. A PSE that does not support this option shall ignore writes to these bits and shall return the value that reports the supported PSE Pinout Alternative. When read as 01, bits 11.3:2 indicate that only PSE Pinout Alternative A is supported by the PSE. When read as 10, bits 11.3:2 indicate that only PSE Pinout Alternative B is supported by the PSE. Where the option of controlling the PSE Pinout Alternative through these bits is provided, setting bits 11.3:2 to 01 shall force the PSE to use only PSE Pinout Alternative A and setting bits 11.3:2 to 10 shall force the PSE to use only PSE Pinout Alternative B. If bit 12.0 is 1, writing to these register bits shall set mr_pse_alternative to the corresponding value: 01 = A and 10 = B. The combinations 00 and 11 for bits 11.3:2 are reserved and will never be assigned. Reading bits 11.3:2 will return an unambiguous result of 01 or 10 that may be used to determine the presence of the PSE Control register.
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CSMA/CD
33.6.1.1.3 PSE Enable (11.1:0) The PSE function shall be disabled by setting bits 11.1 to logic zero and 11.0 to logic zero. When the PSE function is disabled, the MDI shall function as it would if it had no PSE function. The PSE function shall be enabled by setting bits 11.1 to a logic zero and 11.0 to a logic one. When bit 11.1 is a logic one, and bit 11.0 is a logic zero, a test mode is enabled. This test mode supplies power without regard to PD detection. Writing to these register bits shall set mr_pse_enable to the corresponding value: 00 = disable, 01 = enable and 10 = force power. The combination 11 for bits 11.1:0 has been reserved for future use.
NOTECaution, test mode may damage connected non-PD, legacy, twisted pair Ethernet devices or other non-Ethernet devices, especially in split application wiring schemes.
33.6.1.2 PSE Status register (Register 12) (R/W) The assignment of bits in the PSE Status register is shown in Table 3316. 33.6.1.2.1 Reserved bits (12.15:13) Bits 12.15:13 are reserved for future standardization. They shall not be affected by writes and shall return a value of 0 when read. To ensure compatibility with future use of reserved bits and registers, the Management Entity should write to reserved bits with a value of 0 and ignore reserved bits on read. 33.6.1.2.2 Power Denied (12.12) When read as a logic one, bit 12.12 indicates that power has been denied. This bit shall be set to 1 when the PSE state diagram (Figure 336) enters the state POWER_DENIED. The Power Denied bit shall be implemented with latching high behavior as dened in 33.6.1. 33.6.1.2.3 Valid Signature (12.11) When read as a logic one, bit 12.11 indicates that a valid signature has been detected. This bit shall be set to 1 when mr_valid_signature transitions from FALSE to TRUE. The Valid Signature bit shall be implemented with latching high behavior as dened in 33.6.1. 33.6.1.2.4 Invalid Signature (12.10) When read as a logic one, bit 12.10 indicates that an invalid signature has been detected. This bit shall be set to 1 when the PSE state diagram (Figure 336) enters the state SIGNATURE_INVALID. The Invalid Signature bit shall be implemented with latching high behavior as dened in 33.6.1. 33.6.1.2.5 Short Circuit (12.9) When read as a logic one, bit 12.9 indicates that a short circuit condition has been detected. This bit shall be set to 1 when the PSE state diagram (Figure 336) enters the state ERROR_DELAY_SHORT. The Short Circuit bit shall be implemented with latching high behavior as dened in 33.6.1. 33.6.1.2.6 Overload (12.8) When read as a logic one, bit 12.8 indicates that an overload condition has been detected. This bit shall be set to 1 when the PSE state diagram (Figure 336) enters the state ERROR_DELAY_OVER. The Overload bit shall be implemented with latching high behavior as dened in 33.6.1.
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Table 3316PSE Status register bit denitions

Bit(s) 12.15:13 12.12 Reserved Power Denied Name Ignore when read 1 = Power has been denied 0 = Power has not been denied 1 = Valid PD signature detected 0 = No valid PD signature detected 1 = Invalid PD signature detected 0 = No invalid PD signature detected 1 = Short circuit condition detected 0 = No short circuit condition detected 1 = Overload condition detected 0 = No overload condition detected 1 = MPS absent condition detected 0 = No MPS absent condition detected (12.6) (12.5) (12.4) 1 1 1 = Reserved 1 1 0 = Reserved 1 0 1 = Reserved 1 0 0 = Class 4 0 1 1 = Class 3 0 1 0 = Class 2 0 0 1 = Class 1 0 0 0 = Class 0 (12.3) (12.2) (12.1) 1 1 1 = Reserved 1 1 0 = Reserved 1 0 1 = Implementation specic fault 1 0 0 = Test error 0 1 1 = Test mode 0 1 0 = Delivering power 0 0 1 = Searching 0 0 0 = Disabled 1 = PSE pinout controllable by Pair Control bits 0 = PSE pinout Alternative xed Description R/Wa RO RO/ LH RO/ LH RO/ LH RO/ LH RO/ LH RO/ LH RO
12.11
Valid Signature
12.10
Invalid Signature
12.9
Short Circuit
12.8
Overload
12.7
MPS Absent
12.6:4
PD Class
12.3:1
PSE Status
RO
12.0
aRO
Pair Control Ability
RO
= Read Only, LH = Latched High
33.6.1.2.7 MPS Absent (12.7) When read as a logic one, bit 12.7 indicates that an MPS Absent condition has been detected. The MPS Absent bit shall be set to 1 when the PSE state diagram (Figure 336) transitions directly from the state POWER_ON to IDLE due to tpmdo_timer_done being asserted. The MPS Absent bit shall be implemented with latching high behavior as dened in 33.6.1.
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CSMA/CD
33.6.1.2.8 PD Class (12.6:4) Bits 12.6:4 report the PD Class of a detected PD as specified in 33.2.6 and 33.2.7. The value in this register is valid while a PD is connected, i.e., while the PSE Status (12.3:1) bits are reporting Delivering Power. The combinations 101, 110 and 111 for bits 12.6:4 have been reserved for future use. 33.6.1.2.9 PSE Status (12.3:1) Bits 12.3:1 report the current status of the PSE. When read as 000, bits 12.3:1 indicate that the PSE state diagram (Figure 336) is in the state DISABLED. When read as 010, bits 12.3:1 indicate that the PSE state diagram is in the state POWER_ON. When read as 011, bits 12.3:1 indicate that the PSE state diagram is in the state TEST_MODE. When read as 100, bits 12.3:1 indicate that the PSE state diagram is in the state TEST_ERROR. When read as 101, bits 12.3:1 indicate that the PSE state diagram is in the state IDLE due to the variable error_condition = true. When read as 001, bits 12.3:1 indicate that the PSE state diagram is in a state other than those listed above. The combinations 111 and 110 for bits 12.3:1 have been reserved for future use. 33.6.1.2.10 Pair Control Ability (12.0) When read as a logic one, bit 12.0 indicates that the PSE supports the option to control which PSE Pinout Alternative (see 33.2.1) is used for PD detection and power through the Pair Control (11.3:2) bits. When read as a logic zero, bit 12.0 indicates that the PSE lacks support of the option to control which PSE Pinout Alternative is used for PD detection and power through the Pair Control (11.3:2) bits.
33.7 Protocol Implementation Conformance Statement (PICS) proforma for Clause 33, DTE Power via MDI
33.7.1 Introduction The supplier of a protocol implementation that is claimed to conform to IEEE Std 802.3af-2003, DTE Power via MDI, shall complete the following Protocol Implementation Conformance Statement (PICS) proforma. A detailed description of the symbols used in the PICS proforma, along with instructions for completing the PICS proforma, can be found in Clause 21.
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33.7.2 Identication 33.7.2.1 Implementation identication
Supplier1 Contact point for enquiries about the PICS1 Implementation Name(s) and Version(s)1,3 Other information necessary for full identicatione.g., name(s) and version(s) for machines and/or operating systems; System Name(s)2
1Required for all implementations 2May be completed as appropriate in meeting the requirements for the identification. 3The terms Name and Version should be interpreted appropriately to correspond with a suppliers terminology (e.g., Type, Series, Model).
33.7.2.2 Protocol summary
Identication of protocol standard Identication of amendments and corrigenda to this PICS proforma that have been completed as part of this PICS
IEEE Std 802.3af-2003, Clause 33, DTE Power via MDI
Have any Exception items been required? No [ ] Yes [ ] (See Clause 21; the answer Yes means that the implementation does not conform to the standard.) Date of Statement
33.7.2.3 PD Major capabilities/options
Item *PDCL
Feature PD Classication
Subclause 33.3.4
Value/Comment PD supports classication
Status O
Support Yes [ ] No [ ]
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33.7.2.4 PSE Major capabilities/options
Item *CL *END *ENDA *ENDB
Feature Implementation supports classication Endpoint PSE Alternative A Endpoint PSE Alternative B Endpoint PSE PSE supports management registers accessed through MII Management Interface Midspan PSE Power Allocation Pair control ability - PSE supports the option to control which PSE Pinout is used Monitor AC MPS Monitor DC MPS
Subclause 33.2.7 33.2.1 33.2.1 33.2.1
Value/Comment Optional PSE implemented as an endpoint device PSE implements Alternative A PSE implements Alternative B
Status O O/1 END:O.2 END:O.2
Support Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ] Yes [ ] No [ ]
*MAN
33.6
Optional PSE implemented as a midspan device PSE implements power supply allocation
*MID *PA
33.2.1 33.2.9
O/1 O
*PCA
33.6.1.1.3
Optional
*AC *DC
33.2.10.1.1 33.2.10.1.2
PSE monitors for AC MPS PSE monitors for DC MPS
O.3 O.3
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33.7.3 PICS proforma tables for DTE Power via MDI 33.7.3.1 Common device features
Item COM1
Feature Compatibility Considerations.
Subclause 33.1.2
Value/Comment PDs and PSEs compatible at their PIs.
Status M
Support Yes [ ]
33.7.3.2 Power sourcing equipment
Item PSE1
Feature PSE location.
Subclause 33.2.1
Value/Comment Requirements apply equally to Endpoint and Midspan PSE unless otherwise stated. Only implementation allowed for Midspan. Not operate on same link segment simultaneously. In accordance with state diagrams shown in Figure 336 and Figure 337. In accordance with Table 335. After valid detection in less than Tpon. Must initiate and successfully complete a new detection cycle before applying power. Must wait no less than Tdbo as specied in Table 335 before attempting another detection. Not greater than 2.8Vdc. Not until a PD requesting power has been successfully detected. Power must be supplied on the same pairs as those used for detection. Performed via the PSE PI. Item 1 in Table 332. Item 2 in Table 332. Not be damaged by up to 5mA over the range of Vport. Item 18 in Table 335.
Status M
Support Yes [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ]
PSE2 PSE3
Alternative B. Alternative A and Alternative B.
33.2.1 33.2.2
MID:M END:M
PSE4
PSE behavior.
Detection, classication and turn on timing. Turn on power.
33.2.3
PSE5 PSE6
33.2.3.1 33.2.3.1
M M
Yes [ ] Yes [ ]
PSE7
Not apply power within Tpon.
33.2.3.1
Yes [ ]
PSE8 PSE9 PSE10
Alternative B backoff cycle. Backoff voltage. Applying power.
33.2.3.1 33.2.3.1 33.2.4
M M M
Yes [ ] Yes [ ] Yes [ ]
PSE11 PSE12 PSE13 PSE14 PSE15 PSE16
Power pairs. Detecting PDs. Open circuit voltage. Short circuit current. Backdriven current. Output capacitance.
33.2.4 33.2.5 33.2.5 33.2.5 33.2.5 33.2.5
M M M M M M
Yes [ ] Yes [ ] Yes [ ] Yes [ ] Yes [ ] Yes [ ]
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CSMA/CD
Item PSE17
Feature Exhibit Thevenin equivalence to one of the detection circuits in all detection states. Vdetect with a valid PD signature connected. Two measurements with Vdetect. Control slew rate when switching detection voltages. Polarity of Vdetect.
Subclause 33.2.5
Value/Comment Figure 338 or Figure 339.
Status M
Support Yes [ ]
PSE18 PSE19 PSE20 PSE21
33.2.5.1 33.2.5.1 33.2.5.1 33.2.5.1
Item 3 in Table 332. At least 1 V difference between consecutive measurements. Item 6 in Table 332. Match polarity of VPort dened in 33.2.1. (19K to 26.5K DC resistance) and (120nF capacitance or less) and (Voltage offset of up to 2.0 volts DC) and (Current offset of up to 12A). (Less than 15 K DC resistance) or (More than 33 K DC resistance) or (More than 10F capacitive load). Assign to Class 0 if PD cannot be classied as Class 1, 2, 3, or 4. PDs classied as Class 4 will be treated as Class 0. Between 15.5 and 20.5 volts, limited to 100 mA or less at the PI. Same as VPort. Item 20 in Table 335. Classify PD according to Table 334. Assign PD to Class 0 if Iclass is greater than or equal to 51mA. Provide power to the PI according to Table 335, Figure 336, and Figure 337. The specication for VPort includes line and temperature variations. Measured between any conductor of one power pair and any conductor of the other power pair.
M M M M
Yes [ ] Yes [ ] Yes [ ] Yes [ ]
PSE22
Probe link to detect all PDs which present a valid signature.
33.2.6.1
Yes [ ]
PSE23
Reject PDs that present an invalid signature.
33.2.6.2
Yes [ ]
PSE24 PSE25
Default classication. Classication power levels
33.2.7 33.2.7.1
M M
Yes [ ] Yes [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ]
PSE26
Provide VClass.
33.2.7.2
CL:M
Classication polarity Classication timing Measure IClass. Classication default.
33.2.7.2 33.2.7.2 33.2.7.2 33.2.7.2
CL:M CL:M CL:M CL:M
PSE31
Power supply output.
33.2.8
PSE32
Output Voltage
33.2.8.1
Yes [ ]
PSE33
VPort measurement.
33.2.8.1
Yes [ ]
75
Item PSE34 PSE35
Feature Load regulation. Voltage transients
Subclause 33.2.8.2 33.2.8.2 33.2.8.3
Value/Comment Specied as 0.44W to 15.4W load step at a rate of change of 35mA/s max. Limited to 3.5V/s max. Met for common-mode and/or pair-to-pair noise values for power outputs from 0.44W to 15.4W at operating VPort. For VPort > 44V, the minimum value for IPort_max in Table 335 shall be 15.4W/VPort IPeak = 0.4A minimum for 50ms minimum and 5% duty cycle minimum. For VPort > 44V, IPeak = 17.6W/ VPort.
Status M M
Support Yes [ ] Yes [ ]
PSE36
Power feeding ripple and noise
Yes [ ]
PSE37
Maximum current at minimum voltage
33.2.8.4
Yes [ ]
PSE38
AC current waveform parameters
33.2.8.4
Yes [ ]
PSE39
Specications for IInrush current Overload current detection range Overload time limit. Short circuit current Short circuit time limit
33.2.8.5
Meet conditions specied in 33.2.8.5 items a) through e). If Iport > ICUT for T > Tovld the PSE shall remove power. Item 8 in Table 335 Item 9 in Table 335 Item 10 in Table 335. Item 11 in Table 335. Applies to the discharge time from VPort to 2.8Vdc with a test resistor of 320K attached to the PI. Applies to the PI voltage in the IDLE State. Item 15 in Table 335. Item 16 in Table 335.
Yes [ ]
33.2.8.6 33.2.8.7 33.2.8.8 33.2.8.9
M M M M
Yes [ ] Yes [ ] Yes [ ] Yes [ ]
PSE44
Turn off time
33.2.8.10
Yes [ ]
PSE45 PSE46 PSE47
Turn off voltage Current unbalance Power turn on time
33.2.8.11 33.2.8.12 33.2.8.13
M M M
Yes [ ] Yes [ ] Yes [ ]
76
CSMA/CD
Item
Feature
Subclause
Value/Comment Do not initiate if PSE is unable to provide maximum power level requested by PD based on PDs classication. Not be based solely on historical data of power consumption of the attached PD. Meet requirements specied in item 1 and item 3 in Table 336 Meets requirements specied in item 4a in Table 336. Meets requirements specied in item 4b in Table 336. When AC MPS has been absent for a time duration greater than TPMDO. Meet requirements specied in item 6 and item 7b in Table 335. Meet requirements specied in item 6 in Table 335. When DC MPS has been absent for a time duration greater than TPMDO. When the DC current is greater than or equal to IMin2 max for at least TMPS every TMPS + TMPDO, as dened in Table 335
Status
Support Yes [ ] N/A [ ]
PSE48
Power provision.
33.2.9
PA:M
PSE49
Power allocation. PSE AC MPS component requirements. PSE AC MPS component present. PSE AC MPS component absent. Power removal. PSE DC MPS component present. PSE DC MPS component absent. Power removal.
33.2.9
PA:M
Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ]
PSE50 PSE51 PSE52
33.2.10.1.1 33.2.10.1.1 33.2.10.1.1
AC:M AC:M AC:M
PSE53
33.2.10.1.1
AC:M
PSE54 PSE55
33.2.10.1.2 33.2.10.1.2
DC:M DC:M
PSE56
33.2.10.1.2
DC:M
PSE57
Not remove power.
33.2.10.1.2
DC:M
Yes [ ] N/A [ ]
77
33.7.3.3 Powered devices
Item PD1 PD2 PD3
Feature Accept power. Polarity insensitive Source power.
Subclause 33.3.1 33.3.1 33.3.1
Value/Comment On either set of PI conductors. Both Mode A and Mode B per Table 337. The PD will not source power on its PI. Withstand 0V to 57V at the PI indenitely without permanent damage. According to state diagram shown in Figure 3313. Presented on each set of pairs dened in 33.3.1 if not powered via the PI. Presented on each set of pairs dened in 33.3.1 if not powered via the PI and will not accept power via the PI. When powered, present an invalid signature on the set of pairs not drawing power. Characteristics dened in Table 338. Exhibit one or both of the characteristics described in Table 339. Implement classication selection according to maximum power draw specied in Table 3310. As dened in Table 3311. One classication signature during classication. Operate within the characteristics in Table 3312. PD will turn on at a voltage less than VOn. Must stay on for all voltages in the range of VPort. Must turn off at a voltage less than VPort minimum and greater than VOff.
Status M M M
Support Yes [ ] Yes [ ] Yes [ ]
PD4
Voltage tolerance.
33.3.1
Yes [ ]
PD5
PD behavior.
33.3.2
Yes [ ]
PD6
Valid detection signature.
33.3.3
Yes [ ]
PD7
Non-valid detection signature.
33.3.3
Yes [ ]
PD8
33.3.3
Yes [ ]
PD9
Valid detection signature.
33.3.3
Yes [ ]
PD10
33.3.3
Yes [ ]
PD11
Return Class 0 to 3 classication.
33.3.4
PDCL:M
Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] Yes [ ] Yes [ ]
PD12 PD13 PD14 PD15 PD16
Classication signature. Classication signature. PD power supply. PD turn on voltage. PD stay on voltage.
33.3.4 33.3.4 33.3.5 33.3.5.1 33.3.5.1
PDCL:M PDCL:M M M M
PD17
PD turn off voltage.
33.3.5.1
Yes [ ]
78
CSMA/CD
Item PD18
Feature Input average power.
Subclause 33.3.5.2
Value/Comment Applies for input power as specied in Table 3312 averaged over one second. Limited by the PD if Cport is greater than or equal to 180F so that IInrush max is satised. Not to exceed PPort max/VPort for more than 50ms max and 5% duty cycle max. Not to exceed IPort max. Bounded by Irms = [(Idc)2 + (Iac)2]1/2. Dened by the following equation: IPort_max [mA] =12950/ VPort. As specied in subclause 33.3.5.5. As specied in Table 3312 for the common-mode and/or differential pair-to-pair noise at the PD PI. For all operating voltages in the range dened by Table 3312 item 1. Must operate correctly when connected to a PSE generating ripple and noise levels specied in Table 335 item 3. As specied in Table 3312 when connected to a PSE through a 20 series resistor. Shall turn on or off without startup oscillations and within the rst trial at any load value. Classication signature will remain valid within Tclass and remain valid for the duration of the classication period. Mode A and Mode B per 33.3.5.10. (current draw) and (AC impedance) dened in Table 3313. Remove both components of the Maintain Power Signature.
Status M
Support Yes [ ]
PD19
Input inrush current.
33.3.5.3
Yes [ ]
PD20 PD21 PD22
Peak operating current. Peak current. RMS, DC, and ripple current. Maximum operating DC and RMS current. PI capacitance during normal powering mode.
33.3.5.4 33.3.5.4 33.3.5.4
M M M
Yes [ ] Yes [ ] Yes [ ]
PD23
33.3.5.4
Yes [ ]
PD24
33.3.5.5
Yes [ ]
PD25
Ripple and noise.
33.3.5.6
Yes [ ]
PD26
Ripple and noise specication.
33.3.5.6
Yes [ ]
PD27
Ripple and noise presence.
33.3.5.6
Yes [ ]
PD28
Power supply turn on/turn off voltages.
33.3.5.7
Yes [ ]
PD29
Startup oscillations
33.3.5.7
Yes [ ]
PD30
Classication stability.
33.3.5.8
Yes [ ]
PD31
Backfeed voltage
33.3.5.10
Yes [ ]
PD32
Maintain power signature.
33.3.6
Yes [ ]
PD33
No longer require power.
33.3.6
Yes [ ]
79
33.7.3.4 Electrical specications applicable to the PSE and PD
Item EL1
Feature Electrical isolation
Subclause 33.4.1
Value/Comment Electrical isolation will be in accordance with subclause 6.2 of IEC 60950-1:2001 Withstand at least one of the electrical strength tests specied in 33.4.1. Conductive link segments that have different requirements must have those requirements provided by the port-to-port isolation of the NID. Meet or exceed the isolation requirement of the MAU/PHY with which they are associated. Switch more negative conductor. Meet or exceed the isolation requirement of the MAU/PHY with which they are associated. Meet requirements of the appropriate specifying clause. Meet the requirements of 33.4.2.
Status M
Support Yes [ ]
EL2
Strength tests for electrical isolation.
33.4.1
Yes [ ]
EL3
Isolation and grounding requirements.
33.4.1
Yes [ ]
EL4
Environment A requirements for multiple instances of PSE and/or PD. Environment A requirement. Environment B requirements for multiple instances of PSE and/or PD. Fault tolerance for PSEs and PDs encompassed within the MDI. Fault tolerance for PSEs and PDs not encompassed within an MDI.
33.4.1.1.1
!MID:M
Yes [ ] N/A [ ] Yes [ ]
EL5
33.4.1.1.1
EL6
33.4.1.1.2
Yes [ ]
EL7
33.4.2
!MID:M
Yes [ ] N/A [ ]
EL8
33.4.2
Yes [ ]
80
CSMA/CD
Item
Feature
Subclause
Value/Comment Each wire pair will withstand a 1000V common-mode impulse applied at Ecm of either polarity without damage. 0.3/50 s (300 ns virtual front time, 50 s virtual time of the half value). Exceed: - 29-17 log 10 (/10)dB from 1.0 to 20MHz for 10Mb/s PHYs - 34-19.2 log 10 (/50)dB from 1.0 to 100MHz for 100Mbits/s or greater PHYs. Magnitude while transmitting data and with power applied will not exceed 50mV peak when operating at 10Mbits/s and 50mV peak-to-peak when operating at 100Mbits/s or greater. Magnitude at all other ports will not exceed 50mV peak-topeak. At all other ports will be from 1MHz to 100MHz. Must be performed with the PHY transmitting data and an operating PSE or PD and with the PSE load or PD source requirements specied in 33.4.4 items 1) or 2). Will not exceed 10mV peakto-peak measured from 1MHz to 100MHz. The PSE and PD shall be terminated as illustrated in Figure 3316 and tested with the PSE and PD conditions as specified in 33.4.4. Specied in 14.3.1.3.4 for a 10Mb/s PHY, in ANSI X3.263:1995 for a 100Mb/s PHY, and 40.8.3.1 for a 1000 Mb/s PHY.
Status
Support
EL9
Common-mode fault tolerance.
33.4.2
Yes [ ]
EL10
The shape of the impulse for item common-mode fault tolerance.
33.4.2
Yes [ ]
EL11
Impedance balance for transmit and receive pairs.
33.4.3
Yes [ ]
EL12
Common-mode output voltage.
33.4.4
Yes [ ]
EL13
Common-mode AC voltage. Frequency range for commonmode AC voltage measurement.
33.4.4
Yes [ ]
EL14
33.4.4
Yes [ ]
EL15
Common-mode output voltage test conguration.
33.4.4
Yes [ ]
EL16
Noise from an operating PSE or PD to the differential transmit and receive pairs.
33.4.6
Yes [ ]
EL17
Differential noise voltage test setup.
33.4.6
Yes [ ]
EL18
Return loss requirements.
33.4.7
Yes [ ]
81
33.7.3.5 Electrical specications applicable to the PSE

Item PSEEL1 Feature PSE electrical isolation. Subclause 33.4.1 Value/Comment Provided between port device circuits, frame ground and PI leads. Any wire pair will withstand any short circuit to any other pair for an indenite amount of time. Not to exceed maximum value of ILIM. PSE will comply with applicable local and national codes. Comply with the guidelines specied in 33.4.8 items a) and b). Installation of a Midspan PSE will not increase the length to more than 100 meters as dened in ISO/IEC 11801. Must not alter transmission requirements of the permanent link. Must provide continuity for signal pairs. Will not provide DC continuity between the two sides of the segment for the pairs that inject power. Meet transmission parameters NEXT, insertion loss and return loss. NEXTconn 40 - 20log(/ 100)dB (equation 335) but not greater than 65dB from from 1MHz to 100MHz. Insertion_lossconn 0.04 SQRT() dB [Equation (336)] but not less than 0.1dB from from 1MHz to 100MHz. 1MHz<20MHz: 23dB 20MHz100MHz: 14 dB (Table 3314) for transmit and receive pairs. Meet the requirements of this clause and the specications for a Category 5 (jumper) cord as specied in ISO/IEC 118012002 for insertion loss, NEXT, and return loss for all transmit and receive pairs. Status M Support Yes [ ]
PSEEL2
Short circuit fault tolerance.
33.4.2
Yes [ ]
PSEEL3 PSEEL4
Magnitude of short circuit current. Limitation of electromagnetic interference. Insertion of Midspan at FD.
33.4.2 33.4.5
M M
Yes [ ] Yes [ ] Yes [ ] N/A [ ]
PSEEL5
33.4.8
MID:M
PSEEL6
Resulting channel.
33.4.8
MID:M
Yes [ ] N/A [ ]
PSEEL7
Congurations with Midspan PSE. Midspan PSE insertion in the channel. Midspan continuity in nondata pairs. Midspan PSE inserted as a Connector or Telecom outlet.
33.4.8
MID:M
Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ]
PSEEL8
33.4.8
MID:M
PSEEL9
33.4.8
MID:M
PSEEL10
33.4.8.1
MID:M
Yes [ ] N/A [ ]
PSEEL11
Midspan PSE NEXT.
33.4.8.1.1
MID:M
Yes [ ] N/A [ ]
PSEEL12
Midspan PSE Insertion Loss.
33.4.8.1.2
MID:M
Yes [ ] N/A [ ]
PSEEL13
Midspan PSE Return Loss.
33.4.8.1.3
MID:M
Yes [ ] N/A [ ]
PSEEL14
Work area or equipment cable Midspan PSE.
33.4.8.1.4
MID:M
Yes [ ] N/A [ ]
82
CSMA/CD
33.7.3.6 Electrical specications applicable to the PD
Item PDEL1
Feature PD electrical isolation.
Subclause 33.4.1
Value/Comment Provided between all external conductors, including frame ground, and all PI leads. The PIs that require power shall be terminated as illustrated in Figure 3316.
Status M
Support Yes [ ]
PDEL2
PD common-mode test requirement.
33.4.4
Yes [ ]
33.7.3.7 Environmental specications applicable to PSEs and PDs
Item ES1 ES2 Safety. Safety.
Feature
Subclause 33.5.1 33.5.1
Value/Comment Conform to IEC publication 60950-1:2001. Comply with all applicable local and national codes. Application thereof described in 33.5.6 not result in any safety hazard. Comply with applicable local and national codes.
Status M M
Support Yes [ ] Yes [ ]
ES3
Telephony voltages. Limitation of electromagnetic interference.
33.5.6
Yes [ ]
ES4
33.5.7
Yes [ ]
33.7.3.8 Environmental specications applicable to the PSE
Item PSEES1 Safety.
Feature
Subclause 33.5.1
Value/Comment Limited Power Source in accordance with IEC publication 60950-1:2001. As specied in IEC 11801 Edition 2 Clause 6.4.8 (reference: 3 percent).
Status M
Support Yes [ ]
PSEES2
Resistance unbalance.
33.5.5
Yes [ ]
83
33.7.3.9 Management function requirements

Item MF1 Feature Management capability. Subclause 33.6 Value/Comment Access via MII, GMII, or equivalent. Register address 11 for control functions and register address 12 for status functions. Remain high until read via the management interface. Bit assumes a value based on the current state of the condition it monitors. Not affected by writes and return a value of zero when read. Ignore writes to bits 11.3:2. Return the value that reports the supported PSE Pinout Alternative. Forces the PSE to use Alternative A. Forces the PSE to use Alternative B. A value of 1 sets the mr_pse_alternative variable. Setting PSE Enable bits 11.1:0 to a logic 00, also the MDI shall function as it would if it had no PSE function. Setting PSE Enable bits 11.1:0 to a logic 01. Writing to these register bits shall set mr_pse_enable to the corresponding value: 00 = disable, 01 = enable and 10 = force power. Not affected by writes and shall return a value of zero when read. A value of 1 indicates power has been denied. Will be implemented with a latching high behavior as dened in 33.6.1. Status MAN:M Support Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ]
MF2
PSE registers. Register bits latching high (LH). Register bits read.
33.6.1
MAN:M
MF3
33.6.1
MAN:M
MF4
33.6.1
MAN:M
MF5
PSE Control register reserved bits (11.15:4). Pair Control Ability not supported. Writes to 11.3:2 when Pair Control Ability not supported. Bits 11.3:2 set to '01'. Bits 11.3:2 set to '10'. Pair control ability bit, (12.0).
33.6.1.1.1
MAN:M MAN !PCA:M MAN !PCA:M MAN PCA:M MAN PCA:M MAN PCA:M
MF6
33.6.1.1.2
MF7
33.6.1.1.2
MF8 MF9 MF10
33.6.1.1.2 33.6.1.1.2 33.6.1.1.2
MF11
PSE function disabled
33.6.1.1.3
MAN:M
MF12
PSE function enabled.
33.6.1.1.3
MAN:M
MF13
PSE enable bits (11.1:0).
33.6.1.1.3
MAN:M
Yes [ ] N/A [ ]
MF14
Reserved bits (12.15:13).
33.6.1.2.1
MAN:M
Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ]
MF15
Power denied bit (12.12). Power denied bit implementation.
33.6.1.2.2
MAN:M
MF16
33.6.1.2.2
MAN:M
84
CSMA/CD
Item MF17
Feature Valid signature bit (12.11). Valid signature bit implementation. Invalid signature bit (12.10). Invalid signature bit implementation.
Subclause 33.6.1.2.3
Value/Comment Logic 1 indicates a valid signature has been detected. Will be implemented with a latching high behavior as dened in 33.6.1. Logic 1 indicates an invalid signature has been detected. Will be implemented with a latching high behavior as dened in 33.6.1. Logic 1 indicates a short circuit condition has been detected. Will be implemented with a latching high behavior as dened in 33.6.1. Set to 1 when PSE state diagram enters the state ERROR_DELAY_OVER. Will be implemented with a latching high behavior as dened in 33.6.1. Read as logic 1 indicates either or both elements of the MPS is absent for a duration greater than TMPDO as specied in 33.2.10. Will be implemented with a latching high behavior as dened in 33.6.1.
Status MAN:M
Support Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ] Yes [ ] N/A [ ]
MF18
33.6.1.2.3
MAN:M
MF19
33.6.1.2.4
MAN:M
MF20
33.6.1.2.4
MAN:M
MF21
Short circuit bit (12.9).
33.6.1.2.5
MAN:M
MF22
Short circuit bit implementation.
33.6.1.2.5
MAN:M
MF23
Overload bit (12.8).
33.6.1.2.6
MAN:M
MF24
Overload bit implementation.
33.6.1.2.6
MAN:M
MF25
MPS absent bit (12.7).
33.6.1.2.7
MAN:M
Yes [ ] N/A [ ]
MF26
MPS Absent bit implementation.
33.6.1.2.7
MAN:M
Yes [ ] N/A [ ]
85
Annex 33A
(informative)
PSE Detection of PDs

The capacitance of the maximum cabling plant and maximum PD signature is included in the PSE detection requirement.
VdetectFigure 33A.1PD detection signature
PDs contain an autopolarity circuit that may result in a DC offset in the signature, as illustrated in Figure 33A.2.
<150nF
Vdetect+
VdetectFigure 33A.2PD detection signature with polarity guard
86
<150nF
Vdetect+
19K - 26.5K
19K - 26.5K
CSMA/CD
The circuits in Figure 33A.3, Figure 33A.4, and Figure 33A.5 are recommended as test benchmarks for rejection by a compliant PSE.
Vdetect+ <15K VdetectFigure 33A.3Invalid detection signature, impedance low
Vdetect+ >33K VdetectFigure 33A.4Invalid detection signature, impedance high
87
Vdetect+ 25K 10F IClass

10.1V<Vz<14.5
VdetectFigure 33A.5Invalid detection signature, capacitance high
The circuit in Figure 33A.6 is an example of the presentation of a classication signature by a PD.
VClass+
VClass-
Note: Zener threshold (Vz) enables current source between the detection and classification voltage ranges.
Figure 33A.6PD classication signature
88
CSMA/CD
Annex 33B
(informative)
Cabling guidelines
DTE power via MDI is intended to operate over a 100 balanced cabling infrastructure as described in ISO/ IEC 11801-2000. Although initial implementations are expected to make use of Clause 33 to provide powered IP telephones and wireless access points, Clause 33 is intended to address a much larger family of low power devices whose applications require connection to local area networks. It is expected that in the future as building cabling infrastructures begin to support more building automation systems (BAS), additional cabling guidelines will be implemented. BAS systems are used for controlling building systems such as re alarm, security, and access control (e.g., closed circuit television), and energy management systems (e.g., heating, ventilation, and air conditioning, and lighting control). One such standard that is to be published to support these systems with a cabling infrastructure in EIA/TIA is the Building Automation Cabling Standard for Commercial Buildings. This standard will specify a generic cabling system for building automation systems used in commercial buildings for a multi-product, multi-vendor environment. The purpose of the standard is to enable the planning and installation of a structured cabling system for building automation system applications that are required for use in new or renovated construction of commercial buildings. It is signicantly less expensive to integrate all of the major voice, data, and BAS applications by utilizing a fully-integrated structured cabling infrastructure. For planning purposes, a sufcient number of horizontal cabling links should be provided for voice, data, and building automation services over the average oor space. It is recommended that a minimum of two outlets be provided per work area as specied in the current standards in ISO/IEC.
Figure 33B.1Figure
89
Annex 33C
(informative)
Recommended test congurations and procedures

The test gures in this annex are intended to illustrate recommended testing procedures for verifying compliance with Clause 33. In each case, a behavioral circuit is shown along with one possible schematic to implement a test circuit. Other test circuits are possible, as long as compliance with the Clause 33 requirements are adequately demonstrated. In each PSE Test Conguration of this annex, the terminals a, b, c, and d correspond to PI pin assignments according to Table 33C.1. Table 33C.1PSE PI pin assignments for PSE Test Congurations
Alternative A (MDI-X) 3 6 1 2 Alternative A (MDI) 1 2 3 6 Alternative B (All) 4 5 7 8
Terminal a b c d
In each PD Test Conguration of this annex, the terminals a, b, c, and d correspond to PI pin assignments according to Table 33C.2. Table 33C.2PD PI pin assignments for PD Test Congurations
Mode A (MDI) 3 6 1 2 Mode A (MDI-X) 1,3 2,6 3,1 6,2 Mode B (All) 4 5 7 8
Terminal a b c d
90
CSMA/CD
33C.1 Recommended PSE output test procedures

33C.1.1 Test Procedure PSE-1 (output polarity, output voltage, and continuous output power)
Test Procedure PSE-1 is used for testing the following: a) b) c) d) Output voltage polarity (Table 331) VPort (Table 335, item 1) IPort_max (Table 335, item 4, 33.2.8.4) PPort (Table 335, item 14)
Test Procedure PSE-1 uses Test Conguration PSE-A as shown in Figure 33C.1. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a
AA + IPort
CC
Test Load
PSE in normal powering mode
PSE
VPort BB Vcm
Control
d CC + Csig 0.1F +/- 10% Rsig 24.9K +/- 1% Rmax Rmin 510 Vz = 33V +/- 5%
A possible example of the test load above
PD
S1
BB
Rsig, Csig, Vz, Rmin and Rmax are used to set the PSE into normal powering mode
Figure 33C.1Test conguration PSE-A
Test Procedure PSE-1 is as follows: 1) 2) Wait 1 second minimum and measure VPort at Rmax (S1 open). Rmax is adjusted to generate IPort min = 10mA. Wait 1 second minimum and measure VPort at Rmin (S1 closed). Rmin is adjusted to have a total load of 15.4W min.
91
33C.1.2 Test Procedure PSE-2 (load regulation)

Test Procedure PSE-2 is used for testing load regulation, i.e., voltage transients during load changes (Table 335, item 2). Test Procedure PSE-2 uses Test Conguration PSE-B as shown in Figure 33C.2. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a
AA + IPort
CC
Test Load
f = 1/T T
PSE
VPort BB Vcm
Control ton
I High I Low
d CC + Csig 0.1F +/- 10% Rsig 24.9K +/- 1% Rmax Rmin 510 Vz = 33V +/- 5%
Current probe reading: dI/dt<35mA/ s
PD
f = 1/T
I High
BB S1
ton
I Low
Rsig, Csig, Vz, Rmin and Rmax are used to set the PSE into normal powering mode
Figure 33C.2Test conguration PSE-B
Test Procedure PSE-2 is as follows: 1) 2) 3) Wait 1 second minimum and measure VPort at Rmax (S1 open). Rmax is adjusted to generate IPort min = 10mA. Wait 1 second minimum and measure VPort at Rmin (S1 closed). Rmin is adjusted to have a total load of 15.4W min. Change load from Rmax to Rmin and from Rmin to Rmax at f = 10Hz, for a 30% to 70% duty cycle, while monitoring VPort.
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33C.1.3 Test Procedure PSE-3 (ripple and noise)

Test Procedure PSE-3 is used for testing ripple and noise (Table 335, item 3), 33.4.5 and 33.4.6. Test Procedure PSE-3 uses Test Conguration PSE-A as shown in Figure 33C.1. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1. Test Procedure PSE-3 is as follows: 1) 2) 3) Wait 1 second minimum and measure VPort at Rmax (S1 open). Rmax is adjusted to generate IPort min = 10mA. Wait 1 second minimum and measure VPort at Rmin (S1 closed). Rmin is adjusted to have a total load of 15.4W min. Measure VPort ac noise and ripple at Rmax (S1 open) and at Rmin (S1 closed) by using spectrum analyzer or equivalent equipment.
33C.1.4 Test Procedure PSE-4 (output current in startup mode)

Test Procedure PSE-4 is used for testing the following: a) b) IInrush (Table 335, item 5) and TLIM (Table 335, item 11).
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Test Procedure PSE-4 uses Test Conguration PSE-C as shown in Figure 33C.3. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a AA +
PSE at startup mode Low Z current meter 1 or less
IPort
CC
Test Load
PSE
VPort BB -
10V or 30V
d CC S2 + Csig 0.1F +/- 10% Rsig 24.9K +/- 1%

R1 Vcc Reset
41.2K +/- 1% Cpd 1000F +/- 20%
PD
R2
+ -
Set FF Q
BB
Vref
S3 Vz
S1
Example test setup principles: 1. The function of S1 is to connect a large capacitive load when the port voltage is either 0V or 42V. 2. S1 is to allow the transition from OFF to ON in less than 50s. 3. The capacitive load value is chosen to emulate a short-circuit condition for more than 75ms. 4. The test can be repeated only if the capacitive load is discharged and S1 is reset.
Figure 33C.3Test conguration PSE-C
Test Procedure PSE-4 is as follows: 1) 2) 3) 4) 5) 6) Wait 1 second minimum and measure VPort. Set Vz to 30V. Verify that IPort is within limits shown in Figure 33C.4. Discharge capacitive load and reset S1. Set Vz to 10V. Verify that IPort > 60mA.
NOTETest setup (as for any other test setup in Annex 33) may be modied in order to reect different PSE implementations in order to be able to test according to the results expected per Figure 33C.4.
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TLIM IPort[A]
Iport ( 0 < t < 1ms ) = 0.025 -----------t
Overshoot peak current <=5A max at t=1ms
0.45A IINRUSH/ILIMIT
(VPort > 30V
0.4A 0A
1ms max
t 50ms 75ms
S1 was closed
2ms max
Figure 33C.4IPort current and timing limits in startup and short-circuit conditions
33C.1.5 Test Procedure PSE-5 (IDLE state current)

Test Procedure PSE-5 is used for testing the following: a) b) IMin1 (Table 335, item 6a) and TPMDO (Table 335, item 7a),
when monitoring the DC MPS component (33.2.10.1.2).
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Test Procedure PSE-5 uses Test Conguration PSE-D as shown in Figure 33C.5. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a
Test Load
AA + IPort
CC
f = 1/T Valid PD T
PSE
VPort BB toff ton=1s+/-10%
CC
+ Rmax
Csig 0.1F +/- 10%
Rsig 24.9K +/- 1%
PD
510
T f = 1/T
Vz = 33V +/- 5%
toff
BB
S1 -
ton=1s+/-10%
Figure 33C.5Test conguration PSE-D
Test Procedure PSE-5 is as follows: 1) Wait 1 second minimum and measure VPort at Rmax (S1 closed). Verify that 44V <= VPort <= 57V. Rmax is adjusted to generate IPort min = 10mA. Increase Rmax and verify that the power is removed from the port. Repeat step 1. Increase toff from 0 to 400ms and verify that VPort is stable and within its initial value for toff <= 300ms. Verify that VPort was removed for toff = 400ms from the time that S1 was opened.
2) 3) 4) 5)
33C.1.6 Test Procedure PSE-6 (overload current detection range and overload timings)
Test Procedure PSE-6 is used for testing the following: a) b) ICUT (Table 335, item 8) and Tovld (Table 335, item 9).
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Test Procedure PSE-6 uses Test Conguration PSE-B as shown in Figure 33C.2. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1. Test Procedure PSE-6 is as follows: 1) Set Rmax (S1 open) and Rmin (S1 closed). (Rmax is adjusted to generate IPort min = 10mA.) Verify that 44V <= VPort <= 57V. Close S1. Decrease Rmin slowly until power is removed from the port and note the actual value of ICUT. Verify that (15.4/VPort ) < ICUT < 400mA. Repeat step 1. Adjust S1 control to: IPort > ICUT. S1 on time: 50.0 ms. Verify that power is not removed from the port. Adjust S1 control to: IPort > ICUT. S1 on time: 75.0 ms. Verify that power is removed from the port.
2) 3) 4)
The relationships between overload detections and timings are shown in Figure 33C.6.
IPort 0.45A
Short Circuit Range
TOVLD or TLIM threshold
30V <VPort<=Vnominal VPort=Vnominal VPort=Vnominal VPort=Vnominal VPort=Vnominal (Vnominal is VPort during normal powering mode)
30V <VPort<=Vnominal VPort=Vnominal VPort=Vnominal VPort=Vnominal VPort=Vnominal
Voltage is removed from the port Voltage is removed from the port Voltage is removed from the port VPort=Vnominal
ILIM or IINRUSH threshold ICUT threshold

VPort=Vnominal VPort=Vnominal
0.4A
Overload Range
15.4/VPort
Normal Operating Range
VPort=Vnominal
50ms
75ms
Figure 33C.6Port voltage requirements during normal powering mode, overload and short-circuit conditions, as functions of IPort current and time duration
33C.1.7 Test Procedure PSE-7 (short circuit current and timing)

Test Procedure PSE-7 is used for testing the following: a) b) ILIM (Table 335, item 10) and TLIM (Table 335, item 11).
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Test Procedure PSE-7 uses Test Conguration PSE-E as shown in Figure 33C.7. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a
AA + IPort
CC
Test Load
PSE
VPort BB -
S1
CC
+ 0.1F +/- 10% Rsig 24.9K +/- 1% Rmax 1 +/- 5%
Vz = 33V +/- 5% BB S1
PD
Figure 33C.7Test conguration PSE-E
Test Procedure PSE-7 is as follows: 1) Wait 1 second minimum and measure VPort at Rmax (S1 open). Rmax is adjusted to generate IPort min = 10mA. Verify that 44V < VPort < 57V. Close S1 and observe IPort . Verify that IPort is within limits shown in Figure 33C.4.
2) 3)
33C.1.8 Test Procedure PSE-8 (turn on rise time)

Test Procedure PSE-8 is used for testing TRise (Table 335, item 12). Test Procedure PSE-8 uses Test Conguration PSE-A as shown in Figure 33C.1. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1. Test Procedure PSE-8 is as follows:
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1)
2)
Measure VPort at Rmax (S1 open). Rmax is adjusted to generate IPort min = 10mA. Measure rise time from 10% of VPort to 90% of VPort. See Figure 33C.11. Measure VPort at Rmin (S1 closed). Rmin is adjusted to have a total load of 15.4W min. Measure rise time from 10% of VPort to 90% of VPort. See Figure 33C.11.
33C.1.9 Test Procedure PSE-9 (turn off time)

Test Procedure PSE-9 is used for testing TOff (Table 335, item 13a). Test Procedure PSE-9 uses Test Conguration PSE-F as shown in Figure 33C.8. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a AA IPort + Bleeder R
CC
Test Load 10mA
PSE
VPort BB -
0mA
Control
d CC
DD + 320K+/- 1% S1 Rsig 24.9K +/- 1% Rmax
PD
CH-2
510 0.1F +/- 10% Vz = 33V +/- 5%
+
Oscilloscope CH-1
VPort
+ BB -
Figure 33C.8Test conguration PSE-F
Test Procedure PSE-9 is as follows: 1) 2) Measure VPort at Rmax (S1 closed). Rmax is adjusted to generate IPort min = 10mA. Monitor VPort at PSE side (CC) and at PD side (DD). Disconnect PD load by turning off S1 at T0.
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Use CH-1 as the trigger signal for measuring the timings. Verify that VPort has not changed during the rst 300 ms (T1) from T0. Verify that power is removed from the port within 400 ms (T2) from T0. Verify that VPort is less than 2.8Vdc within 500 ms max from tx. The turn off timing relationships are illustrated in Figure 33C.9.
Disconnect Detection time = TMPDO

Voltage
tx=TMPDO threshold Turn off time
tx
VPort (cc)
VPort (dd)
2.8Vdc time To S1=Open T2=400ms max T3=tx+500ms max T1<tx<T2
T1=300ms min
Figure 33C.9Turn off timing relationships
33C.1.10 Test Procedure PSE-10 (turn on, detection and classication time)
Test Procedure PSE-10 is used for testing the following: a) b) c) Tpon (Table 335, item 16), Tdet (Table 335, item 19), and Tpdc (Table 335, item 20).
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Test Procedure PSE-10 uses Test Conguration PSE-F1 as shown in Figure 33C.10. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a DD S1
Valid PD
AA +
CC IPort
Test Load
PSE in discovery mode
PSE
VPort BB -
d CC
DD + S1 Rsig 24.9K +/- 1% Rmax
PD
CH-2
510 0.1F +/- 10% Vz = 33V +/- 5%
+
Oscilloscope CH-1
+ BB -
Figure 33C.10Test conguration PSE-F1
Test Procedure PSE-10 is as follows: 1) 2) Wait 1 second minimum and measure VPort at Rmax (S1 closed). Rmax is adjusted to generate IPort min = 10mA. Open S1. Repeat step 1 and monitor the events vs. timings as illustrated in Figure 33C.11.
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Voltage Classification time
57V 44V Detection time 90%

Disconnect detection function starts here. After this point, detection results must be reset and a new detection cycle must be generated.
VPort (cc)
10% 2.8Vdc min 500ms 75ms

Turn ON rise time
time
400ms tpon=Turn ON time T1 IPort 10mA time T0 S1= Close T3 Timing values shown are maximums from Table 33-5
Figure 33C.11Detection, classication, turn on, and total cycle timing relationships
33C.1.11 Test Procedure PSE-11 (detection backoff time)

Test Procedure PSE-11 is used for testing Tdbo (Table 335, item 17) for a PSE that performs Alternative B as specied in 33.2.3.1 and Ropen (Table 332, item 9).
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Test Procedure PSE-11 uses Test Conguration PSE-G as shown in Figure 33C.12. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
AA +
CC IPort
Test Load
PSE
VPort BB -
33K<Invalid Sig<=500K Open circuit>500K
d CC S1
DD + Rmax Rsig
PD
510 0.1F +/- 10% BB Vz = 33V +/- 5%
Figure 33C.12Test conguration PSE-G
Test Procedure PSE-11 is as follows: 1) Set Rsig to 24.9K+/-1%. Close S1. Measure VPort at Rmax. Rmax is adjusted to generate IPort min = 10mA at VPort . Open S1. Adjust Rsig=34K+/-1%. Close S1. Verify that VPort is less than 2.8V for 2 second minimum after the detection sequence has been completed. Open S1. Adjust Rsig=510K+/-1%. Close S1. Verify that VPort voltages and timings are as dened in Figure 33C.11.
2)
3)
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33C.1.12 Test Procedure PSE-12 (port capacitance during detection)

Test Procedure PSE-12 is used for testing Cout (Table 335, item 18). Test Procedure PSE-12 uses Test Conguration PSE-H as shown in Figure 33C.13. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
a
AA +
PSE
Cpse
+ VPort 10.0V VPort
BB
I=1.00mA
V2 V1
Cpse=f(Rpse, Cpse, I, VPort, t)
Possible Voltage offset
t1
t2
Figure 33C.13Test conguration PSE-H
Test Procedure PSE-12 is as follows: 1) Set PSE port to IDLE state. Connect switched current source, I, to the PSE port. The current source voltage is clamped to 10V. Calculate port capacitance (Cpse) by measuring Rpse (port resistance) and using it in a typical differential equation solution.
33C.2 Recommended PSE AC disconnect-detection test procedures

33C.2.1 Test Procedure PSE-13 (ac disconnect pulse parameters)
Test Procedure PSE-13 is used for testing the following: a) b) c) d) e) f) g) V_close (Table 336, item 3a), V_open (Table 336, item 1a), Fp (Table 336, item 1b), SR (Table 336, item 1c), TPMDO (Table 336, item 3c) when monitoring the AC MPS component (33.2.10.1), VPort (Table 336, item 3b), and Zac1 and Zac2 (Table 336, item 4a and item 4b).
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Test Procedure PSE-13 uses Test Conguration PSE-I as shown in Figure 33C.14. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
AA +
CC IPort
Test Load
Valid MPS
PSE
VPort BB S1
d
Test Zac A
CC
S1 switches test loads from Zac1=27K to Zac2=2M
S1
DD Rsig1 +/- 1%
Zac
PD
Cpd1 100nF +/- 10%
2M +/- 1% BB
Cpd1 may be on either side of the diode bridge
Figure 33C.14Test conguration PSE-I
Test Procedure PSE-13 is as follows: 1) Set Rsig1 value to have total of Zac = 27K. Measure VPort and verify that VPort is within the normal operating voltage range. Verify that the ac ripple voltage is less than 0.5Vpp. This requirement should be veried with test Zac A. Monitor VPort at the PSE side (CC) and at the PD side (DD). Disconnect PD by turning off S1 at To. Use S1 opening as the trigger signal for measuring the timings. Verify that power is not removed during the rst 300ms (T1) from To. Verify that power is removed from the port within 400ms (T2) max from To. Measure V_open, Fp and SR. Refer to Figure 33C.15. Steps 1 through 6 should be conducted for both test Zac congurations as indicated in Figure 33C.14.
2) 3) 4) 5) 6) 7)
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Disconnect Detection time = TMPDO

Voltage V_close
Vp=60Vp max
tx
Turn off time
VPort (cc)
VPort (dd)
2.8Vdc time To S1=Open T2=400ms max T1=300ms min T1<tx<T2 T3=tx+500ms max
tr
V_open SR=V_open/tr
T=1/f
Figure 33C.15AC disconnect timing relationships
33C.2.2 Test Procedure PSE-14 (port impedance)

Test Procedure PSE-14 is used for testing the following: a) b) c) d) I_sac (Table 336, item 2a) when monitoring the AC MPS component (33.2.10.1.1), R_rev (Table 336, item 2b) when monitoring the AC MPS component (33.2.10.1.1) (If 33.2.10.1.2 is used, this test may be used when testing 33.2.5 according to Figure 338), Zsource (Figure 338 and Figure 339), and Detection short circuit (33.2.5).
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Test Procedure PSE-14 uses Test Conguration PSE-J as shown in Figure 33C.16. In this test conguration terminals a, b, c, and d correspond to pin assignments according to Table 33C.1.
AA +
CC IPort S1 VPort
Test Load
PSE
30V
BB
d CC +
S1 VPort 10K +/- 1% -
V=30Vdc=Vdetect max
+ Vsense -
BB
Figure 33C.16Test conguration PSE-J
Test Procedure PSE-14 is as follows: 1) 2) 3) 4) Set S1 = close. Monitor IPort and verify that IPort is less than 5mA over a 2 second period. (Ignore results of rst 1ms). Verify that IPort at frequency Fp is less than 5mA over a 2 second period. (Ignore results of rst 1ms). Set S1 = open. Verify that Vsense<5.27Vp (i.e., (30V Vd) 10K/(10K + 45K)) over a 2 second period. Vd is the forward diode voltage drop assumed to be 1V in this example.
33C.3 Recommended PSE detection signature test procedures

33C.3.1 Test Procedure PSE-15 (signature detection parameters)
Test Procedure PSE-15 is used for testing the following: a) b) PSE port impedance during detection (see 33C.2.2), Parallel diode across the port (33.2.5, Figure 33-8 and Figure 33-9),
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c) d) e) f) g) h) i) j) k) l)
Voc (Table 332, item 1), Isc (Table 332, item 2), Vvalid (Table 332, item 3), Vtest (Table 332, item 4), Rgood, (Table 332, item 7) Rbad (Table 332, item 8), Cbad (Table 332, item 11), Vslew (Table 332, item 6), Detection and power on the same leads (33.2.4), and VOS (Table 332, item 12).
Test Procedure PSE-15 uses Test Conguration PSE-K. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.1. The behavioral description is shown in Figure 33C.17.
a AA +
IPort S1
CC
PSE
VPort BB -
d CC ++
CH-1
1K +/- 1%
0-12A
Voffset=0V to 2.00V
PD
+ Rsig
Oscilloscope
Rsig = Valid signature: 19K,26.5K Non-valid signature:15K,33K
V1 +
Rsig
PD signature elements
S2 BB Csig -
Figure 33C.17Test conguration PSE-K
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An example of a possible test circuit is shown in Figure 33C.18.

a AA +
IPort S1
CC
Test Load
PSE
VPort BB -
d
CC Rsig
Rsig is the total signature value including permitted error. Rsig for valid signature is 19K to 26.5K. Rsig for non-valid signature is <15K and >33K. The additional error compared to PD input signature is represented by Rs and Rp.
Rs 1K +/- 1% Rp V1 +
PD input signature is defined by setting Rs=0 and Rp=open. Min value is 23.75K and max value is 26.25K.
PD
Voffset=2.0V
Oscilloscope
Csig=100nF +/- 10%
Rsig1 +/- 1%
S2 BB
Figure 33C.18Example of circuit for PSE-K
Test Procedure PSE-15 is as follows: 1) Parallel diode across the port (33.2.5, Figure 33-8 and Figure 33-9). a) Set S1 and S2 to OFF. b) Turn system OFF (No voltages across PSE port). Set V1 to 10.0V. Set S1 and S2 to ON. c) Measure IPort. Verify that IPort > 3mA. d) Reverse V1 polarity. Verify that IPort < 40 A. e) Set S2 to OFF. Detection open circuit voltage (33.2.5). a) Set S1 and S2 to OFF. b) Verify that VPort < 30Vp during the detection phase for 500ms max out of Ttot period as specied in Figure 33C.11. Verify that VPort average is <=2.8Vdc when the PSE is not in detection phase. c) Verify that the voltage slew rate is less than 0.1V/s. d) It is allowed to have no detection signals or to have single-point detection if the PSE identies that the port is open. Detection short circuit current (33.2.5). See Test Procedure PSE-14. Detection minimum/maximum voltages (33.2.5.1), Two-point detection voltage difference (33.2.5.1), Detection criteria (33.2.6.1), Rejection criteria (33.2.6.2),
2)
3) 4)
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Detection voltage slew rate (33.2.5.1), and Detection and power on the same leads (33.2.5.1). a) Part 1. i) Set Rs=0. Adjust VOFFSET to 0V. ii) Set Rsig1 to 23.75K. Adjust Rsig to 19.0K by adjusting Rp. iii) Adjust VOFFSET to 2.0V. b) Part 2. i) Set S1 to ON. Set S2 to OFF. ii) Monitor VPort and measure detection voltages Vdet1 and Vdet2. Verify that Vdet1 and Vdet2 are between 2.8V and 10V and |Vdet2 - Vdet1|>=1V. iii) Verify that 44V min is present across the port for 299ms min. iv) Verify that the slew rates of all the switched voltages are less than 0.1V/ s. c) Part 3. i) Adjust VOFFSET to 0V. ii) Set Rsig1 to 26.25K. Set Rp=Open. Adjust Rsig to 26.5K. by adjusting Rs. iii) Adjust VOFFSET to 2.0V. iv) Repeat step 4ii. d) Part 4. i) Adjust VOFFSET to 0V. ii) Set Rs=0. Set Rp=open. Set Rsig1 to 14.7K+/-1%. iii) Set S1 to ON. Set S2 to OFF. iv) Verify that power is not applied to the port. e) Part 5. i) Adjust VOFFSET to 0V. ii) Set Rs=0. Set Rp=Open. Set Rsig1 to 34K+/-1%. iii) Set S1 to ON. Set S2 to OFF. iv) Verify that power is not applied to the port. f) Part 6. i) Set Rsig1 to 24.9K. Set Rp=Open. Set Rsig=0. Set Csig=10.0F. ii) Adjust VOFFSET to 2.0V. iii) Set S1 to ON. Set S2 to OFF. iv) Verify that power is not applied to the port. v) Repeat steps ii to v with Rsig1=open.
33C.4 Recommended PD detection signature test procedures

33C.4.1 Test Procedure SIG-1 (PD signature characteristics)
Test Procedure SIG-1 is used for testing the following: a) b) c) d) V-I slope (Table 338), V offset (Table 338), Input capacitance (Table 338), and PD classication current (Table 3311).
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Test Procedure SIG-1 uses Test Conguration SIG-A as shown in Figure 33C.19. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.2
a IN DD + VPort d b
PD under Test
S2 + VN I=100A S1
Figure 33C.19Test conguration SIG-A
Test Procedure SIG-1 is as follows: 1) 2) 3) 4) Set S1 to ON. Set S2 to OFF. Limit the current of VN to between 4 and 5 mA. Change VN from 2.70V to 10.1V in steps of 1.00V and measure IN for each VN value. Calculate RsigN = (VN+1 VN)/(IN+1 IN). Verify that 23.75K<=RsigN <= 26.25K. Find the current/voltage offset by calculating the intersection of the line between the (VN, IN) and (VN+1, IN+1) data points and the V/I axis. Verify that the current offset is less than 10 A and the voltage offset is less than 1.9V.
NOTE The concept of this setup is to measure the equivalent Rsig as seen at the PD port and includes all possible errors caused by series diode drops (V offset) and component accuracy. Rsig is calculated with a minimum of two measurements to simulate PSE operation.
5) 6) 7) 8)
Change VN from 0.00V to 2.70V in steps of 0.20V and measure IN. Plot the results of IN vs. VN from steps 1 and 5 and nd V offset. See Figure 33C.20. Set S1 to OFF. Set S2 to ON. Ignore any data points above 10V. Activate the switched current source.
NOTEThe concept of this setup is to calculate the capacitance value by ramping the capacitance voltage with a constant current source and using the equation I t = V C. This method is useful when series diodes are present.
9)
Calculate the port capacitance (Cpd) by measuring Rpd (port resistance) and using it in the typical differential equation solution. 10) Verify that the PD port capacitance is between 50nF and 120nF. 11) Set the voltage source to sweep from 14.5V to 20.5V. 12) Observe the current at IN and verify that it falls in the valid range per Table 3311.
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IN
Voffset V-I slope= 23.75K to 26.25K
0V 2.7V
VN
10.1V
Figure 33C.20Signature voltage offset
VPort V2 V1
Allowable Voltage offset
t2
t2
Cpd=f(Rpd, Cpd, I, VPort, t)
Figure 33C.21Signature input capacitance
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33C.5 Recommended PD power supply test procedures

33C.5.1 Test Procedure PD-1 (all parameters)
Test Procedure PD-1 is used for testing the following: a) b) c) d) e) f) g) h) i) j) k) l) m) n) VOff (Table 3312, item 8b), VOn (Table 3312, item 8a), IPort (max input current during startup) at Vpse=44Vdc (Table 3312, item 5), IPort (max input current during startup) at Vpse=57Vdc (Table 3312, item 5), IPort (max average input current during normal powering mode at VPort=37Vdc) (Table 3312, item 3), PPort (max input power at 37Vdc) (Table 3312, item 2), Max input peak current at VPort=37Vdc and max load (Table 3312, item 2), IPort (max average input current during normal powering mode at VPort=57Vdc) (Table 3312, item 3), PPort (max input power at 57Vdc) (Table 3312, item 2), Max input peak current at VPort=57Vdc and max load (Table 3312, item 2), IPort (min input current at VPort=37Vdc) (Table 3313, item 1), IPort (min input current at VPort=57Vdc) (Table 3313, item 1), Polarity insensitivity when PD implements Auto-MDI-X (33.3.1), and PD false underload timing limitations (33.3.6.1).
Test Procedure PD-1 uses Test Conguration PD-A as shown in Figure 33C.22. In this test conguration, terminals a, b, c, and d correspond to pin assignments according to Table 33C.2. CL is a controlled current limit device with two threshold settings, CL1 and CL2. CL1 and CL2 are time-limited to TCL1 and TCL2. If IPort > = CL1 for t > TCL1, then S1 is opened and test is failed.
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.
PSE test circuit
S2 IPort + 20(*)
(*) Models the max cable resistance
a + VPort d
b
PD under Test
Vsource Control
Vpse
S2 S3
Current Limit V1
AA IPort S1
CC 20+/-1% DD + VPort -
+ -
b
PD under Test
V2
+ -
Vpse 0.47F BB
d Vcm
An example of the test circuit above
Figure 33C.22Test conguration PD-A
Test Procedure PD-1 is as follows: 1) 2) 3) Set S1 to OFF. Set S2 to ON. Set V1 to 30.0V. Set CL1=CL2=1.0A. Set S1 to ON. Wait 1sec and verify that IPort< 1.14mA(=30V/26.25K) Set S1 to OFF. Set S2 to OFF. Set V1 to 44.0V. Set V2=0.0V. Set CL1=CL2=0.4A,TCL1=50ms, CL2=350.0mA and TCL2=5sec. Set PD for max load mode. 4) Set S1 to ON. 5) Record the following parameters: IInrush, TInrush, Von. See Figure 33C.23. 6) Set S1 to OFF. 7) Set V1 to 57.0V. Set S1 to ON and record the following parameters: IInrush, TInrush, Von. See Figure 33C.23. 8) Set S2 to ON. Set V1 = 37.0V, V2 = 0.0V, CL1 = 0.4A, TCL1 = 50ms, CL2 = 350.0mA and TCL2=5sec. Set PD for max load mode. 9) Wait 1sec and record Iport_dc and Iport_ac parameters. See Figure 33C.23. 10) Set V1=57V and repeat steps 8,9. 11) Set S2 to ON. Set V1 = 30.0V, V2 = 0.0V, CL1 = 0.4A, TCL1=50ms, CL2=350.0mA and TCL2=5sec. Set PD for max load mode. 12) Increase V1 until PD power supply turns ON. Verify that V1<=Von.
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13) Set S1 to OFF. Set S2 to ON. Set V1 = 37.0V, V2 = 0.0V, CL1 = 0.4A, TCL1=50ms, CL2=350.0mA and TCL2=5sec. Set PD to min load if applicable. 14) Set V1=57.0V. Verify that IPort>= 10mA. 15) If the PD implements Auto-MDI-X, repeat steps 3, 4, and 5, and verify PD operation with reverse polarity connection. 16) Set V1=44V and V2=13V. Set PD to its minimum operating load. 17) Wait 1sec until IPort is stable. 18) Set S3 to OFF and monitor IPort. Verify that IPort is less than 10mA for only TUNLD<290ms. If IPort is not less than 10mA for any time duration, then timing requirement is ignored. See Figure 33C.24. 19) To verify PD input capacitance during normal operating mode: Set S1 to OFF. Set S2 to ON. Set V1=57.0V, V2=0.0V, CL1=CL2=1.0A,TCL1=TCL2=10sec. Set PD for constant load. 20) Set S1 to ON. 21) Wait 1sec and measure IPort. 22) Set S1 to OFF while monitoring VPort. Measure the time duration, Tdrop for VPort to drop from 57.0V to 56.0V. Calculate C=IPort Tdrop/1V. Verify that 5F<C<180F. 23) If C>180F, set CL1=CL2=1.0A, TCL1=TCL2=5sec. Repeat all tests regarding inrush current limitation and verify that inrush current is limited by the PD to 0.4A max. 24) Set V1 to 44V, V2=0V. Set S1 to ON. Measure VPort and Vcm noise level at VPort between 37V and 57V and at all known PD operating conditions.
IPort
Iport ( 0 < t < 1ms ) =
IINRUSH=5Ap max
Peak current limited by PD load design to 0.4A max
0.025 -----------t
T>ton/0.05
IPort(max)=0.4A max Current limit level IPort dc max= 12.95/VPort 10mA min ton= 50ms max
1ms 2ms
TINRUSH=50ms max
S1 set to ON
Figure 33C.23PD inrush current timing and max peak ripple current and time duration at normal powering mode
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VPort
57.0V 44.0V
S3 set to OFF
tf<1ms
t
TUNLD<290ms
IPort
10mA min
Figure 33C.24PD underload timing
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Annex 33D
(informative)
PSE-PD stability
33D.1 Recommended PSE design guidelines and test setup
In order to prevent potential oscillations between the PSE and PD, the sum of the PSE port output impedance (Zo_port), the cable impedance (Zc), the PD input port circuitry impedance (Zpd_cir) and the PD EMI output lter impedance (Z_emi) should be lower than the PD power supply input impedance (Zin_ps_pd). This subclause focuses on the PSE part. Port output impedance consists of two parts: a) b) PSE power supply output impedance (Zo_ps), which is function of the load (PPort), and Series elements (Z_ser) which connect the PSE power supply output to the port.
Therefore, the total Port output impedance during normal powering mode is Zo_port=Zo_ps+Z_ser. In order to maintain PSE-PD stability, the following guidelines apply: a) Zo_ps max =0.3. at frequencies up to 100KHz at Pport=15.4W. Zo_ps can be extracted from Zport by measuring VPort/IPort (with an external power dynamic analyzer system) as a function of frequency and subtracting from Zport the value of Zser (f=DC) which is limited by the value of Zser at DC (low frequency). If Zo_ps<Zo_ser and VPort is kept to 44V min and 57Vmax during dynamic load changes from 10Hz to 100KHz, then the value of Zo_ps is not limited.
b)
Compliance to the above requirements should be made by measuring the port output impedance from 10Hz to 100KHz at 15.4W load at short cable length or by presenting simulation results.
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See Figure 33D.1 for the PSE-PD system impedance allocation.
PSE Zo_ps PSE power supply Zo_ser PSE Output Port Circuitry Zc Cable Zout3 PD Input Port Circuitry
PD Zout4
PD DC/DC converter
EMI Filter
Zin
Zo_ps
Zo_port
Zo_emi(s) Zin_ps_pd(s)
Figure 33D.1PSE - PD system impedance allocation
See Figure 33D.2 for the test setup and Figure 33D.3 for the test requirements.
a Iac(f) + b VPort R_loa c Vac(f)
PSE
Vac source(f)
Figure 33D.2Test setup for measuring Zo_port
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Zo_port=Vac(f)/Iac(f)
15.4W Zo_ps = 0.3 --------------- max Pport
Z_ser @ frequency=0
F[KHz]
Figure 33D.3Test requirements for measuring Zo_port
33D.2 Recommended PD design guidelines

PD port input impedance consists of two parts: a) b) PD port input circuits including the EMI lter (Zin_ser), and PD power supply input impedance (Zin_ps_pd), which is fed by the output of the EMI lter (Zo_emi).
In order to maintain stability with the PSE, the PD power supply input impedance (Zin_ps_pd) should be higher than the output impedance of the total network including the PD EMI output lter impedance fed by the cable (MDI) output impedance which is fed by the PSE port output impedance. The worst case scenario is when the cable (MDI) length is zero (in terms of lower damping factor). The access to the PD input power supply is not possible through the PD port for evaluating the various impedances and derivation of the above parameters. Because of this, measuring the PD input impedance is a complicated task, the following guidelines should be followed by the PD vendor: c) The PD power supply input impedance (Zin_ps_pd) at max load of Pport=12.95W should be higher than 30 at any frequency up to the PD power supply crossover frequency. If the PD power supply is consuming less than Pport=12.95W, then Zin_ps_pd min=3012.95/Pport. The PD power supply EMI lter output impedance should be Zo_emi=2.7 max. If the PD power supply is consuming less than Pport=12.95W, then Zo_emi=2.712.95/Pport.
d)
See Figure 33D.1 for the PSE-PD system impedance allocation.
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Annex 33E
(informative)
Cabling resistance unbalance

This standard sets the maximum current that can be continuously drawn by the PD at 350mA total or 175mA per individual conductor of the differential pair. One drawback to implementing this scheme that should always be considered is the resistance unbalance associated with the cabling. The cabling resistance unbalance parameter is specied in this standard in reference to IEC 11801 Edition 2, Clause 6.4.8, (reference: 3 percent). The 3% cabling resistance unbalance is specied for the ISO/IEC cabling channel illustrated in Figure 3318. At the maximum current allowed, this resistance unbalance equates to a 10.5mA difference between the two paths. Signicant work on current imbalance in transformers has shown that certain data patterns induced a large baseline wander. Baseline wander induced a DC offset comparable to 6mA. The transformer specication that resulted is 350H under all conditions of tolerance, temperature, and with 8mA of DC bias. Using a transformer that can only tolerate this amount of DC bias reduces the maximum current the PSE can deliver without saturating the transformer to: 350mA (8mA/10.5mA) = 267mA (33E1)
In order to restore the current capability to 350mA, some form of ballast circuitry must be employed. Figure 33E.1 details a method for resolving cable and connector unbalances by using two resistors. Note that these ballast resistors are required at each end of both the transmit and receive channels. The addition of the capacitor in parallel with the resistors helps to minimize the signal loss induced by the balancing resistors and should be selected to present a low impedance at the lowest possible signal frequency.
R = 3.3 C = 0.22F
(Implementation specific)
Figure 33E.1Transformer detail
Table 33E.1 details the resistance of different cable sizes over minimum and maximum temperature ranges. These resistance values are used in calculations to resolve connector unbalance and voltage drops.
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Table 33E.1PSE PI pin assignments for test procedure terminals

AWG 26 24 22 Min at 0 C 12.18 7.65 4.81 Max at 0 C 12.79 8.03 5.05 Nominal 13.47 8.42 5.31 Min at 50 C 14.70 9.14 5.79 Max at 50 C 15.43 9.60 6.08
For purposes of calculating the ballast resistors, a typical maximum conguration of ve connectors is used. Each connection point has one contact measuring 0 with the other contact measuring 0.02, which is the maximum allowed resistance per IEC 60512-2. Furthermore, a ve meter length of 22 AWG cable is used because longer lengths reduce the unbalance. The equations describing this interaction are: Rc Rb Iout + Iimbal --------- + --------- = Iout Iimbal ( Rc 1.03 + Rb 1.01 + Rconn ) ---------------------------------------------------------------- 1.03 1.01 2 2 where: Iout = 350mA (maximum current from the PSE), Iimbal = 8mA (current difference between the two paths), Rc = 0.24 (5m of 22 AWG cable), Rb = 6.6 (ballast resistance), and. Rconn = 0.1 (total contact resistance for 5 connectors). Under these conditions the worst case current unbalance is 6.2mA. Using 3.3 ballast resistors increases the total voltage drop associated with the cabling by: (175+(6.2/2))mA (4 3.3W) = 2.35V (33E3) (33E2)
According to this standard, the minimum voltage sourced by the PSE must be greater than 44V, and the maximum voltage presented by the PD must be less than 36V. This 8V margin permits up to 45.7 of resistance per conductor path to exist between the PSE and PD under maximum current conditions. Even under worst case conditions of temperature and tolerance, using 3.3 ballast resistors in series with 100m of 26AWG cable (see Table 33E.1) still provides a margin of: 8V (175mA (30.86W 1.03 + 0.1 + 4 3.3W 1.01)) = 0.28V (33E4)
The ballast resistors will dissipate worst case power during an overcurrent condition, which this standard has set at 450mA. In this case the wattage rating of the ballast resistors would be: (450mA/2)exp2 3.3W = 0.17W Using standard sizes, this becomes 0.25W. (33E5)
121

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IEEE Std 802.

IEEE Computer Society

Print: SH95132 PDF: SS95132

IEEE Std 802.3af-2003

LAN/MAN Standards Committee of the IEEE Computer Society

IEEE-SA Standards Board

ISBN 0-7381-3696-4 ISBN 0-7381-3697-2

Introduction to IEEE Std 802.3af-2003

802 OVERVIEW & ARCHITECTURE*

802.2 LOGICAL LINK

DATA LINK LAYER

802.3 MEDIUM ACCESS 802.3 PHYSICAL

802.5 MEDIUM ACCESS 802.5 PHYSICAL

802.11 MEDIUM ACCESS 802.11 PHYSICAL

802.15 MEDIUM ACCESS 802.15 PHYSICAL

802.16 MEDIUM ACCESS 802.16 PHYSICAL PHYSICAL LAYER

* Formerly IEEE Std 802.1A.

Copyright 2003 IEEE. All rights reserved.

Conformance test methodology

IEEE Std 802.3af-2003

Copyright 2003 IEEE. All rights reserved.

Copyright 2003 IEEE. All rights reserved.

Copyright 2003 IEEE. All rights reserved.

Catherine Berger IEEE Standards Project Editor

Copyright 2003 IEEE. All rights reserved.

Copyright 2003 IEEE. All rights reserved.

Copyright 2003 IEEE. All rights reserved.

List of special symbols

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

AMENDMENT TO IEEE Std 802.3

MPS PD PI PSE SELV

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

14.10.4.5.11 Isolation requirements

Isolation, MDI leads to DTE Physical Layer circuits

Isolation, MDI leads to all external conductors

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

AMENDMENT TO IEEE Std 802.3

22. Reconciliation Sublayer (RS) and Media Independent Interface (MII)

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

AMENDMENT TO IEEE Std 802.3

30. 10 Mb/s, 100 Mb/s, 1000 Mb/s and 10 Gb/s Management

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

AMENDMENT TO IEEE Std 802.3

oResourceTypeID Present if MII Repeater System

oResourceTypeID Present if MII DTE System

Denotes one-to-many relationship Denotes one-to-one relationship

Figure 303Repeater and DTE System Eentity relationship diagram

Copyright 2003 IEEE. All rights reserved.

IEEE Std 802.3af-2003

Insert new Figure 304 as follows:

oPSE 30.9.1 Midspan system