design

Edited by Bill Travis

ideas
R4 + IC2 _ SCHMITT TRIGGER VOUT

DPP adds versatility to VFC

Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA
he basic VFC (voltage-to-frequenR2 cy converter) in Figure 1 Figure 1 comprises an integrator (IC1) and a Schmitt-trigger circuit (IC2). VIN R3 C1 R1 The integrator converts the dc input voltage, VIN, to a linear voltage ramp, and the _ Schmitt trigger sets the limits of the inIC1 tegrators output voltage. Feedback + around both circuits provides the condiINTEGRATOR tion for oscillation. The DPP (digitally programmable potentiometer) in Figure 2 adds programmable limits to the Schmitt trigger and adds two powerful This schematic depicts a basic voltage-to-frequency converter. features to the VFC. First, the scale or conversion factor is programmaFigure 2 R2<<R1 D1 ble, and, second, for a fixed dc-in1k, 1% put voltage, the converter is a programmable oscillator. The frequency, f0, of the pR3 (1 p)R3 VIN single-supply converter in Figure 2 is: 6 3

5V 8 1 2 7 CAT5113 DIGITAL CONTROLS

f o f BASE

(1

p ) (VIN 2.5V ) ; p 5V

R1 20k, 1%

C1 0.01 F 5V

10k

5 5V 2 + V1 8 510 7 4 1 2.5V 4

0 p 0.5, and 2.5V VIN 5V ,

2 _ 3

7 6

where fBASE 1/2 R1C1, and p is the relative position of the wiper from one end (0) of the DPP to the other end (1). For the100-tap Catalyst (www.catsemi.com)
DPP adds versatility to VFC................................................................99 Power circuit terminates DDR DRAMs..................................................100 Circuit protects bus from 5V swings ............................................102 Use a 555 timer as a switch-mode power supply........................104 VCO uses programmable logic................106 Controlling slew times tames EMI in offline supplies ................................108
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IC1 LT1097 + 4

IC2 LM211 3 _

V0UT

edn021031dix30741 Using a digitally programmable potentiometer, you can vary the scale factor of this voltage-to-freHeather
quency converter.

5113 potentiometer, the range of the rate resistors and capacitors. The scale scale-factor term (1-p)/p is 1 to 99 with factor relates to the ratiometric tempera resolution and accuracy of approxi- ature coefficient of the DPP and hence is mately 1%. For the values shown in Fig- minimally temperature-dependent. You ure 2, the practical range of frequencies can use the circuit as a programmable osis 500 Hz to 25 kHz. Higher bandwidth, cillator when VIN is fixed and the potenrail-to-rail CMOS versions of IC1 and tiometers wiper setting changes the limIC2, and a greater R1/R2 ratio can extend its of the Schmitt trigger. the accuracy and range of the circuit. The automated, accurate setting of the scale edn021031dix30742 factor saves manufacturing test time and Is this the best Design Idea in this Heather eliminates the need for expensive, accu- issue? Select at www.edn.com.
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Power circuit terminates DDR DRAMs

Ron Young, Maxim Integrated Products, Sunnyvale, CA
DR (double-data-rate) SDRAMs find use in high-speed memory systems in workstations and servers. The memory ICs operate with 1.8 or 2.5V supply voltages and require a reference voltage equal to half the supply voltage (VREF VDD/2). In addition, the logic outputs terminate with a resistor to the termination voltage, VTT, which equals and tracks VREF. VTT must source or sink current while maintaining VTT VREF 0.04V. The circuit of Figure 1 provides the termination voltage for both 1.8 and 2.5V memory systems and delivers out-

put current as high as 6A. IC1 includes a step-down controller and two linear-regulator controllers and operates with input voltages of 4.5 to 28V. IC1s fixed-frequency, 200-kHz PWM controller maintains the output voltage by sourcing and sinking current. Maximum sink current equals the maximum source current, though the sink current has no current limiting. When sinking current, the device returns some current to the input supply. To implement the tracking function, one of IC1s extra linear-regulator controllers is configured as

an inverting amplifier. This amplifier compares VDD/2 (created by R1 and R2) with VREF from IC1 and generates an error signal that connects via R3 to IC1s FB pin, thereby forcing VOUT to track VDD/2. A 10-mA load, R4, is necessary to bias the inverting amplifier for accurate tracking. VOUT can track VDD/2 for VDD in the range 1 to 4V.

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Figure 1

5V INPUT 4.7 F 10V CMPSH-3

1200 F 10V MV-AX 22 F 10V (4

16 VP 9 15k 22 nF 2 ILIM

15 VL BST 14 0.1 F

COMP

DH LX DL GND OUT

13 4.7 12 11 10 3 4 R5 10k 4.7

FDS6690A

EC31 QS03L

1000 pF

1.5 H DO5022P

FDS6690A

IC1 MAX1864T 5V

EC31 QS03L

1.25V 6A + 1200 F 2.5V OS-CON

1OOk POK 1 POK FB B2

R3 10k R7 220 330 pF CMPT 3906

5V

+ 1.24V

FB2

1 F 10V

B3

7 8

22.1k 22 F 10V R1 1k 2.5V 0.1 F R2 1k R4 100

FB3

22.1k

This circuit generates the termination voltage for DDR synchronous DRAMs.

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C

Circuit protects bus from 5V swings

Said Jackson, Equator Technologies Inc, Campbell, CA
1 he circuit in Figure 1 auto0.01 F 5V matically detects voltage 5 3 Figure 1 VCC GND and protects a bus, such 4 2 IC as a 3.3V-limited PCI bus, from 5V 1 + PCI_SERR# NC7SZ125 signal-level swings.You can also use 1 5V the circuit to determine bus-voltage 4 swings within one bus-cycle for set10 PR 2 D PR Q 5 12 9 ting appropriate termination voltD Q IC2A IC2B 3 ages of protection diodes or termi5V 11 CLK 6 8 PCI_CLK CLK Q Q CL CL nation resistors. Todays deepR1 13 1 74LVC74A 3.3 74LVC74A PLACE CLOSE submicron VLSI-manufacturing 0603 PCI_RST# TO PCI BUS 5 1 R4 techniques sometimes require cirPCI Q VCC 1.5k C2 R3 0603 2 LS1 12V AD10 R2 0603 + C3 cuits to limit I/O voltages to 3.3V GND IC3 0603 0.1 F P9948-ND 1 10 F 4 2k 2k 3 0805 PANSONIC IN IN+ 0805 signal swings. Connecting such cirPCI_AD[31..0] 1% 1% 2 EFB-CB37C11 METAL METAL C cuits to a bus with 5V level-swing MAX999 5V BUS B TOP VIEW Q1 cards could damage the circuitry. WARNING 1.88V 5% 5V BUZZER E The circuit in Figure 1 can accuR6 FMMT4123CT-ND C4 R5 9k SOT-23 0.1 F 15k rately andwithin one bus cycle 1% METAL JP1 0805 1% METAL 0603 detect a level swing larger than 3.3V 0603 1 ENABLE PROTECTION 2 on any bus and, upon a fault situaHEADER2 tion, generate a reset signal and an alarm output to notify the user and This circuit provides both an audible alarm and an error flag when an overvoltage condition exists. the system of this fault. Some of the The circuit generates a signal that can PCI_AD10. Every PCI device asserts this novel circuit features include a highly accurate synchronous-detection capability reset the system, or it can generate a sys- signal at least once during PCI enumerto avoid false alarms arising from large tem-error signal. Because the alarm-reg- ation, but you can monitor other signals signal overshoots, high impedance and ister memory, IC2B, serves as an asyn- if necessary. This method guarantees low capacitive loading of the bus, auto- chronous register, you can switch the recognition of a 5V PCI device shortly afmatic system shutdown during fault con- alarm off only by removing power from ter the BIOS starts enumerating the PCI ditions, and a single-cycle response time. the system or by asserting the reset signal. bus during system boot. IC2A then latchThis circuit successfully operates in To avoid false triggering by signal over- es the comparators, IC3, Q-output Pin 1 products using the high-performance shoot and undershoot, a flip-flop-based during the rising edge of the PCI clock. 3.3V MAP-CA processor family from register, IC2A, samples the comparator This action asserts flip-flop IC2B, which Equator Technologies (www.equator. output only during the rising edges of the in turn enables buzzer LS1 and generates com), but you can use it in other high- bus clock. This method allows for a gen- an open-collector, low-active, system-erspeed 3.3V or even lower voltage systems. erous 33-nsec period at 33 MHz for the ror signal through IC1. You could use this Equators latest generation chips are 5V- bus signal to settle down before being error signal to automatically remedy the tolerant, but you can adjust the circuit to sampled. Lowpass filtering by sensor re- fault condition by disabling the offendprotect other 1.8 and 2.5V chips. The cir- sistors R2, R3 and the 3- to 5-pF parasitic ing circuit on the bus. The sense and refcuit uses IC3, an ultrahigh-speed Maxim capacitance on Pin 3 of IC3 limit the max- erence resistors R2, R3, R5, and R6 should (www.maxim-ic.com) MAX999 com- imum clock speed of this circuit. The be metal-film 1% types. The 5V reference parator with 4.5-nsec propagation delay, traces connecting to Pin 3 of IC3, R2, and voltage connected to R5 determines the TPD, to constantly compare a signal line, R3 thus must be as short as possible and accuracy of the trip voltage, and todays PCI_AD10 in case of a PCI bus, to a ref- may limit the bus speed to approximate- power regulators have sufficient accuraerence level of 3.8V. This reference volt- ly 40 to 50 MHz. Symmetrically lower- cy so that you can use a 5V system-powage is an optimal compromise between ing the resistance of R2 and R3 increases er line as the reference voltage, obviating 5V signals clamped by 3.3V protection the maximum bus speed to a theoretical the need for a special 5V-reference gendiodes and the normal-operation 3.3V 7-nsec cycle time (greater than 140 MHz) erator. Removing jumper JP1 disables the signals. Once the voltage exceeds this ref- at the expense of a higher signal-loading circuit. erence level for an entire bus clock peri- current on the bus. In the case of monitoring a PCI bus, Is this the best Design Idea in this od, the system turns on an alarm buzzer Pin 3 of comparator IC3 monitors signal issue? Select at www.edn.com. connected to Q1.

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Use a 555 timer as a switch-mode power supply

Aaron Lager, Masterwork Electronics, Rohnert Park, CA
ost switch-mode power supplies rely on a PWM (pulse-widthmodulated) output that is controlled via voltage feedback. A 555-timer IC can inexpensively perform PWM. The circuit in Figure 1 shows how to turn a 555 PWM circuit into an switch-mode power supply with only one simple equation. The design uses two 555s. IC1, in astable mode, triggers IC2 in PWM mode. IC1 is set to oscillate at approximately 60 kHz at a high duty cycle. The output is low for only approximately 2.5 sec to trigger the PWM circuit and then goes high for the rest of the period. The PWM circuit has a maximum pulse width of approximately 85 sec, and it becomes shorter, depending on the control voltage from the feedback circuit. You can reduce the chip count by using a 556 or another

continuous-trigger source. The input must be (1.5VOUT Margin), so for 5V output you need 9V minimum input. If you use CMOS chips and small timing capacitors C1 and C2, you can keep the operating current low. Thus, you can use a simple zener-diode regulator for the 555 and increase the input voltage to more than 30V. The input-voltage limit is a function of how much power the zener supply can handle while delivering 5 to 10 mA to the 555s. Q1 has low RDS(ON) and low VGS and can handle more than 40V. D1 clamps any voltage spikes, such as those that occur when a large current flow ceases, causing a large magnetic field to be left in the inductor. You should select D1 according to the output voltage you need. For 5V output, use a 5.6V zener diode, for example.

IC3, R1, R2, and V1 form the feedback circuit to set the output voltage. The outputvoltage equation is VOUT V1(R1/R2 1). The TL431 is a popular part for setting a voltage reference and can easily create the 1.25V shown for V1. You can supply 5V at 1.5A with an input of 9 to 40V. At voltages higher than 12V, you can add a 10V zener-diode supply for the chips. The zener supply only slightly reduces the efficiency. With 12V input, 5V, 1.5A output efficiency is approximately 70%, and it drops to 65% with a 40V input and a zener circuit. The zener diodes influence is more noticeable at lower current levels; at a 50-mA load the efficiency drops to approximately 50%. Is this the best Design Idea in this issue? Select at www.edn.com.

POWER ASTABLE TRIGGER PWM

10k 2 TRIGGER UNREGULATED SUPPLY + 4 RESET 5 CONTROL 83

8 VCC 3 100

0.1 F

4 RESET 2

8 VCC DISCHARGE 7 6

4.7k

IC1 OUTPUT 555

TRIGGER

6 THRESHOLD 7 DISCHARGE 3 GND 1 OUTPUT

THRESHOLD IC2 5 555 CONTROL GND 1

C1 0.01 F

Figure 1
C2 0.001 F

0.01 F

0 3 Q1 ZVN4210G/ZTX 1 L1 68 H 1N5817 + 100 F D1 1N4734 1 RLOAD 2 VOUT REGULATED SUPPLY R1 10k R2 3.33k 1.25 _

POWER

7 3 + V+ IC3 LF411/NS V

OUT

2 + V1 4

FEEDBACK VOUT 1.25(1 R1/R2). 0 0

Heres one more use for the ubiquitous 555 timer: a switch-mode power supply.

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VCO uses programmable logic

Susanne Nell, Breitenfurt, Austria
VCO (voltage-controlled oscillator) is an analog circuit, so 5V 5V Figure 1 you cannot find it in the liR2 R4 R1 braries for the design of digital proR3 27k 6.8k 6.8k 27k J2 STEERING grammable chips. When you need such OUTPUT VOLTAGE a circuit for synchronization or clock 1 1 multiplication, you need to find a circuit 2 ICST D1 Q 2 1N4148 3 that works with the standard digital funcQ D2 1N4148 tions, such as AND and NAND. Several F possibilities exist for building variableF 4 1 frequency oscillators. For example, you IC1A IC1B can change the frequency using a varac74HC02 74HC02 tor diode. Unfortunately, these diodes 2 3 5 6 have a small change of frequency per volt. C1 C2 So, the standard Pierce oscillator with 1 nF 1 nF one inverter and capacitors is not useful for these applications. Another idea is to use a Schmitt-trigger inverter and to vary This unique VCO, implemented with discrete logic, has a wide tuning range. the charging resistor. This method can work, but the hysteresis of the IC usualNOT NOT 2 1 1 2 ly has a wide tolerance, so the selected inverter chip has a large influence Figure 2 on the frequency. 1 1 For these reasons, this design modifies 4 1 NOR2 a two-NOR-gate RC oscillator (Figure 1) TRISTATE TRISTATE NOR2 to function as a VCO. For almost all pureBUFFER BUFFER CMOS circuits, the switching point be2 2 2 3 5 6 tween high and low states is approximately VCC/2. This point does not depend PAD5 PAD2 PAD6 on the device. Using this circuit, you can BIDIRECTIONAL BIDIRECTIONAL OUTPUT obtain a wide frequency-tuning range. 1 Q The output is a square wave with a 50% 1 2 Q R4 duty cycle. At power-on, both capacitors ICST 2 R4 1k C1 C2 OUTPUT C1 and C2 are uncharged, and IC1A has a 1k 1 nF 1 nF STEERING low output. Thus, the output of IC1B is VOLTAGE VST high, and C2 charges with the time constant R2C2. The additional charging current from ICST and R4 also influences this This VCO uses an EPLD and has high gain, expressed in kilohertz per volt. charging time. When the voltage on C2 reaches VCC/2, IC1B switches to a low state. VCOs gain. The circuit uses an Altera grammable-logic devices with CMOS inNow, the output of IC1A switches high, (www.altera.com) EPLD (erasable pro- puts. You can also use steering voltages and C1 charges with time constant R1C1, grammable-logic device), the EPM3032. much higher then the supply voltage of influenced by ICST and R3. The low sig- Tristate buffers replace the diodes in Fig- the programmable chip, because the voltnal at the output of IC1B forward-biases ure 1, and the charging resistors connect age on the input of the chip never goes D2 and quickly discharges C2. directly to the steering voltage. This con- higher then VCC/2. This fact makes the This circuit produces a 50% duty cy- figuration produces the highest possible circuit suitable as a voltage-to-frequency cle if C1 C2, R1 R2, and R3 R4. The val- VCO gain: approximately 700 kHz/V for converter with a high input-voltage ues of R4 and R3 and the steering voltage, the component values shown. You can range. VST, determine the VCOs gain in kilo- switch off the VCO by using a steering hertz per volt. The circuit in Figure 2 voltage lower then VCC/2. You can imple- Is this the best Design Idea in this yields the highest possible value for the ment this circuit using almost all pro- issue? Select at www.edn.com.

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Controlling slew times tames EMI in offline supplies

David Canny, Linear Technology Corp, Milpitas, CA

MI from offline switching power supplies typically causes all sorts of problems for power-supply designers. You may need a large EMI filter to meet FCC emission requirements. Switchers for high efficiency produce high-frequency switching noise that can propagate through the rest of the system and cause problems. Board layout is critical, requiring considerable experimentation, even for experienced designers. The low-noise circuit in Figure 1 significantly reduces the complexity of these issues by continuous, closed-loop control of the voltage and current slew rates. High-frequency noise suppression is particularly important for medical devices because they dont require the ac-line-toearth ground capacitors (Y capacitors)

that typically suppress this noise. The absence of these capacitors allows medical devices to easily comply with the more stringent low-leakage-current healthcare specifications of UL544, UL2601, and CSA22.2. Figure 1 shows a 30W (12V output at 2.5A) offline power supply. IC1, an LT1738 low-noise switching regulator in a flyback topology, drives Q1 and continuously controls the current slew using the resistor at the RCSL pin. The IC controls the voltage slew using the resistor at the RVSL pin and the capacitance at the CAP pin. IC2, an LT1431 programmable reference, and the optocoupler close the isolated loop back to the LT1738. The circuit achieves current limit by sensing the current through a 68-m resistor at the CS

pin. Q2, Q3 and their associated circuitry provide undervoltage lockout with hysteresis. During start-up, the SHDN pin stays low until C5 charges to 12V via R1. The LT1738 then turns on and subsequently obtains most of its operating power from T1s auxiliary winding. The feedback goes directly to the LT1738s VC pin rather than to the FB pin because the optocoupler provides the feedback gain that the LT1738s internal feedback amplifier typically provides. C6 and L1 attenuate the low-frequency harmonics of the LT1738 switching frequency. You can see the benefits of the circuit by measuring its ac-line-conducted EMI and then comparing these measured results with those for basically the same circuit with the LT1738 replaced with a

X1 1M 90 TO 264V AC 1M X3

DANGER: HIGH VOLTAGE L1 C6 0.1 F 250V AC "X2" BR1

C1 + 100 F 400V

P6KE200A 510 2W 220 pF K A 3 6 BA521 5 8 7 12 A1 A2 C2 + 330 F 25V C3 + 330 F 25V C4 + 330 F 25V 200 pF 200V D1

T1 11

10 VOUT 12V 2.5A

Figure 1
+

R1

100k 2W

10

MUR160

VOUT

510k 7.5V IN755A

C5 56 F 35V

17 VIN 14 5 6 SHDN V5

19 NC

10 NFB

470 pF 15 pF 600V

15 pF CAP GATE CS NC PGND VC GND 11 GCL 3 0.1 F 4 13 10 nF 18 20 12 0.068 0.5W 6 5 2 ISO1 CNY17-3 3 1 3 V+ 2 COMP 8 REF IC2 COLL LT1431 RTOP 4 7 RMIO G-F G-S 6 5 38.3k 1% 1k 0.22 F 2 1 4 Q1 MTP2N60E 1k 0.1 F 1k VOUT

IC1 SYNC LT1738 CT RT RVSL RCSL FB SS

510k 51k 165k Q2 2N2222 1.5 nF

7 8 19.6k 16 3.9k 15 3.9k 9

2N2222 Q3 51k

10k 1%

NOTES: D1: MBR20300CT. UNLESS OTHERWISE NOTED, L1: HM18-10001. ALL RESISTORS: 1206,5%. BR1: GENERAL INSTRUMENTS WO6G. T1: PREMIER MAGNETICS POL-15033. C2, C3, AND C4: SANYO MV-GX.

A 30W offline power supply passes FCC Class B emission requirements without line-to-earth-ground capacitors.

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generic switcher. The only circuit-parameter difference is that, unlike the LT1738, the generic switcher doesnt actively control the switching current and voltage slew rates. Figure 2 shows the frequency spectra for both circuits. You can see by the respective frequency spectra that the LT1738-based circuit generates emissions well within FCC Class B requirements, whereas the circuit with the (b) (a) generic part results in emissions that exceeds FCC Class B allowable emissions by a significant margin. In these 50-MHz-wide spectral plots, areas under horizontal lines indicate acceptable Figure 2 Another benefit of the circuit FCC Class B emission requirements. The spectral plot for the LT1738-based circuit (a) in Figure 1 is that the output voltage shows emissions well within FCC Class B requirements, unlike the plot for the generic switcher (b). noise comprises the fundamental ripple with practically no high-frequency com- the output with little attenuation through in medical devices because the absence of ponents. You can attenuate this ripple the parasitic capacitance of the output fil- Y capacitors results in low leakage current voltage if desired to less than 300 V us- ters inductor. The circuit in Figure 1 to earth ground in compliance with ing a 100- H, 100- F LC filter on the minimizes noise and EMI by controlling health-care specifications. output. The generic switcher, on the oth- the voltage and current slew rates of the er hand, produces more output noise be- external n-channel MOSFET. This circuit Is this the best Design Idea in this cause the high-frequency noise passes to is well-suited for offline power supplies issue? Select at www.edn.com.

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