quartus-prime

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Here are 117 public repositories matching this topic...

CTSRD-CHERI / quartus-install

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Install Intel FPGA 'Quartus Prime' software on remote servers

fpga quartus-prime quartus

Updated Mar 22, 2024
Python

RomeoMe5 / DDLM

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Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

arthurmteodoro / install-quartus-linux

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Tutorial de instalação do Quartus Prime no Linux

fpga install-script modelsim quartus-prime quartus-linux fpga-linux

Updated Oct 16, 2019
Shell

robseb / HPS2FPGAmapping

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SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated Jun 9, 2021
Verilog

w3arycod3r / fpga-defender

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A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.

fpga vhdl defender quartus-prime de10-lite

Updated Oct 13, 2022
VHDL

Jefferson-Lopes / quartus-installation

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Full tutorial about how to install Quartus Prime software in different systems

ubuntu installation quartus-prime quartus-linux

Updated Nov 8, 2024

MinatsuT / CYC1000_SDRAM

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A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

Updated Jul 8, 2021
Verilog

egk696 / EDAC_SDRAM_Controller

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Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

fpga vhdl embedded-systems vivado fault-tolerant quartus-prime sdram sdram-controller cots-sdram

Updated Oct 30, 2017
Verilog

Nathen-Smith / FPGA-super-mario-bros

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FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

systemverilog fpga-soc quartus-prime nios2

Updated Dec 16, 2021
Verilog

Paebbels / pyIPCMI

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A Python-based IP Core Management Infrastructure.

infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro

Updated Apr 29, 2021
Python

tharinduSamare / Multicore_processor_verilog_design

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This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

fpga simulation verilog modelsim quartus-prime

Updated Jan 8, 2022
Verilog

jagumiel / irReceiver

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Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.

vhdl ir-receiver quartus-prime ir-decoder vhdl-code infrared-decoder

Updated Mar 29, 2022
VHDL

pa-tiq / vending_machine

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fpga verilog quartus-prime quartus de10nano de10-lite de10-nano verilog-project quartus-18-1

Updated Jul 14, 2019
Verilog

robseb / socfpgaPlatformGenerator

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Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

build-automation linux-distribution u-boot quartus-prime cyclone-v sd-card-image intel-fpga arria10 soc-fpgas soc-eds

Updated Jun 4, 2024
Python

addisonElliott / LogiFindFPGATest

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This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.