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<< /S /GoTo /D (section.1) >>
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(1 Introduction)
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<< /S /GoTo /D (section.2) >>
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(2 Module Motherboard architecture)
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<< /S /GoTo /D (subsection.2.1) >>
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(2.1 Design goals)
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<< /S /GoTo /D (subsection.2.2) >>
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(2.2 Architecture)
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<< /S /GoTo /D (section.3) >>
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(3 Link configuration)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Pipeline)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 IMS C004 link configuration)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 T212 pipeline and C004 control)
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Software link configuration)
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<< /S /GoTo /D (section.4) >>
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(4 System control)
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<< /S /GoTo /D (subsection.4.1) >>
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(4.1 Reset, Analyse and Error)
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<< /S /GoTo /D (subsection.4.2) >>
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(4.2 Up, Down and SubSystem)
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<< /S /GoTo /D (subsection.4.3) >>
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(4.3 Source of control)
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<< /S /GoTo /D (subsection.4.4) >>
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(4.4 Clock)
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<< /S /GoTo /D (section.5) >>
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(5 Interface to a separate host)
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<< /S /GoTo /D (subsection.5.1) >>
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(5.1 Link interface)
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<< /S /GoTo /D (subsection.5.2) >>
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(5.2 System control interface)
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<< /S /GoTo /D (subsection.5.3) >>
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(5.3 Interrupts)
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<< /S /GoTo /D (section.6) >>
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(6 Mechanical considerations)
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<< /S /GoTo /D (subsection.6.1) >>
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(6.1 Dimensions)
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<< /S /GoTo /D (subsubsection.6.1.1) >>
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(6.1.1 Width and length)
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<< /S /GoTo /D (subsubsection.6.1.2) >>
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(6.1.2 Vertical dimensions)
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<< /S /GoTo /D (subsection.6.2) >>
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(6.2 Motherboard sockets)
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<< /S /GoTo /D (subsection.6.3) >>
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(6.3 Mechanical retention of TRAMs)
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<< /S /GoTo /D (subsection.6.4) >>
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(6.4 Module orientation)
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<< /S /GoTo /D (section.7) >>
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(7 Edge Connectors)
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<< /S /GoTo /D (section*.2) >>
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(References)
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