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<< /S /GoTo /D (section.1) >>
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(1 Introduction)
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<< /S /GoTo /D (section.2) >>
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(2 A brief history)
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<< /S /GoTo /D (subsection.2.1) >>
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(2.1 Introduction)
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<< /S /GoTo /D (subsection.2.2) >>
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(2.2 Displays)
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<< /S /GoTo /D (subsection.2.3) >>
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(2.3 The frame store)
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<< /S /GoTo /D (subsection.2.4) >>
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(2.4 Colour)
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<< /S /GoTo /D (subsection.2.5) >>
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(2.5 System performance)
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<< /S /GoTo /D (subsection.2.6) >>
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(2.6 Graphics display system)
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<< /S /GoTo /D (section.3) >>
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(3 Overview of a parallel graphics system)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Introduction)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 Transputers and occam)
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<< /S /GoTo /D (subsubsection.3.2.1) >>
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(3.2.1 The IMS T800 transputer)
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<< /S /GoTo /D (subsubsection.3.2.2) >>
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(3.2.2 Serial links)
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<< /S /GoTo /D (subsubsection.3.2.3) >>
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(3.2.3 On-chip floating point unit)
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<< /S /GoTo /D (subsubsection.3.2.4) >>
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(3.2.4 2-D Block move instructions)
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<< /S /GoTo /D (subsubsection.3.2.5) >>
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(3.2.5 The occam programming language)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 Transputer modules \(TRAMs\))
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Introduction to graphics TRAMs)
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<< /S /GoTo /D (subsection.3.5) >>
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(3.5 Introduction to the serial port TRAM)
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<< /S /GoTo /D (subsection.3.6) >>
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(3.6 Introduction to the display backend TRAM)
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<< /S /GoTo /D (section.4) >>
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(4 Serial port TRAM)
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<< /S /GoTo /D (subsection.4.1) >>
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(4.1 Introduction)
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<< /S /GoTo /D (subsubsection.4.1.1) >>
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(4.1.1 Memory map)
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<< /S /GoTo /D (subsubsection.4.1.2) >>
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(4.1.2 Frame store addressing and the video RAM)
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<< /S /GoTo /D (subsubsection.4.1.3) >>
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(4.1.3 Pixel mappings)
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<< /S /GoTo /D (subsubsection.4.1.4) >>
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(4.1.4 Double buffered frame store addressing)
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<< /S /GoTo /D (subsubsection.4.1.5) >>
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(4.1.5 Frame store distribution)
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<< /S /GoTo /D (subsection.4.2) >>
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(4.2 Random access port)
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<< /S /GoTo /D (subsubsection.4.2.1) >>
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(4.2.1 Memory upgrades)
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<< /S /GoTo /D (subsubsection.4.2.2) >>
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(4.2.2 Memory cycles)
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<< /S /GoTo /D (subsubsection.4.2.3) >>
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(4.2.3 Address latches and multiplexing)
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<< /S /GoTo /D (subsubsection.4.2.4) >>
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(4.2.4 Decoding)
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<< /S /GoTo /D (subsection.4.3) >>
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(4.3 Serial access port)
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<< /S /GoTo /D (subsubsection.4.3.1) >>
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(4.3.1 Introduction)
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<< /S /GoTo /D (subsubsection.4.3.2) >>
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(4.3.2 Address generator)
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<< /S /GoTo /D (subsubsection.4.3.3) >>
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(4.3.3 Address sequencer)
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<< /S /GoTo /D (subsubsection.4.3.4) >>
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(4.3.4 Pixel counter)
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<< /S /GoTo /D (subsubsection.4.3.5) >>
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(4.3.5 Distributed control)
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<< /S /GoTo /D (section.5) >>
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(5 Display TRAMs)
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<< /S /GoTo /D (subsection.5.1) >>
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(5.1 Introduction)
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<< /S /GoTo /D (subsection.5.2) >>
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(5.2 An example display TRAM)
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<< /S /GoTo /D (subsubsection.5.2.1) >>
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(5.2.1 Pixel channels)
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<< /S /GoTo /D (subsubsection.5.2.2) >>
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(5.2.2 Display modes)
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<< /S /GoTo /D (section.6) >>
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(6 System configurations)
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<< /S /GoTo /D (subsection.6.1) >>
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(6.1 Driving the frame store)
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<< /S /GoTo /D (subsection.6.2) >>
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(6.2 Frame store configurations)
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<< /S /GoTo /D (section.7) >>
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(7 Conclusion)
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<< /S /GoTo /D (section.8) >>
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(8 Transputer memory interface)
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<< /S /GoTo /D (subsection.8.1) >>
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(8.1 Memory interface timing)
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<< /S /GoTo /D (subsection.8.2) >>
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(8.2 Configurable strobes)
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<< /S /GoTo /D (subsection.8.3) >>
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(8.3 Multiplexed address-data bus)
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<< /S /GoTo /D (subsection.8.4) >>
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(8.4 Byte selection)
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<< /S /GoTo /D (subsection.8.5) >>
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(8.5 Refresh)
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<< /S /GoTo /D (subsection.8.6) >>
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(8.6 Wait states)
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<< /S /GoTo /D (subsection.8.7) >>
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(8.7 MemReq, MemGranted and direct memory access)
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<< /S /GoTo /D (subsection.8.8) >>
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(8.8 Termination)
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<< /S /GoTo /D (subsection.8.9) >>
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(8.9 Configuration of the memory interface)
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<< /S /GoTo /D (subsection.8.10) >>
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236 0 obj
(8.10 The memory interface program)
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<< /S /GoTo /D (section.9) >>
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(9 Video RAMs)
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<< /S /GoTo /D (subsection.9.1) >>
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(9.1 What is a video RAM)
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<< /S /GoTo /D (subsection.9.2) >>
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(9.2 Video RAM logic operations)
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<< /S /GoTo /D (section*.2) >>
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(References)
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