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<< /S /GoTo /D (section.1) >>
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(1 Introduction)
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<< /S /GoTo /D (section.2) >>
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(2 Multi transputer evaluation)
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<< /S /GoTo /D (section.3) >>
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(3 Module)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Module)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 Module Links)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 Module Error)
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Module Decoupling)
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<< /S /GoTo /D (section.4) >>
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(4 Master Transputer)
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<< /S /GoTo /D (subsection.4.1) >>
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(4.1 Master Transputer)
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<< /S /GoTo /D (subsection.4.2) >>
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(4.2 Memory)
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<< /S /GoTo /D (subsection.4.3) >>
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(4.3 Address decode for ROM and peripherals)
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<< /S /GoTo /D (subsection.4.4) >>
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(4.4 Wait state generator)
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<< /S /GoTo /D (subsection.4.5) >>
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(4.5 EPROM)
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<< /S /GoTo /D (subsection.4.6) >>
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(4.6 DUART)
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<< /S /GoTo /D (section.5) >>
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(5 Conclusion)
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<< /S /GoTo /D (appendix.A) >>
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(A Supplement)
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<< /S /GoTo /D (subsection.A.1) >>
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(A.1 16L8 PAL logic equations and pin assignment)
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<< /S /GoTo /D (subsection.A.2) >>
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(A.2 Component side foil of IMS B006)
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<< /S /GoTo /D (subsection.A.3) >>
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(A.3 Solder side foil of IMS B006)
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<< /S /GoTo /D (subsection.A.4) >>
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(A.4 Component and solder side foil of module)
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