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<< /S /GoTo /D (section.1) >>
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(1 Overview of the Memory Interface)
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<< /S /GoTo /D (subsection.1.1) >>
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(1.1 Memory Interface timing)
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<< /S /GoTo /D (subsection.1.2) >>
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(1.2 Early and Late Write)
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<< /S /GoTo /D (subsection.1.3) >>
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(1.3 Refresh)
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<< /S /GoTo /D (subsection.1.4) >>
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(1.4 Wait states and Extra cycles)
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<< /S /GoTo /D (subsection.1.5) >>
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(1.5 Setting the Memory Interface Configuration)
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<< /S /GoTo /D (subsection.1.6) >>
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(1.6 The Memory Interface Program)
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<< /S /GoTo /D (section.2) >>
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(2 Basic Considerations in Memory Design)
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<< /S /GoTo /D (subsection.2.1) >>
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(2.1 Minimum memory interface cycle time)
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<< /S /GoTo /D (subsection.2.2) >>
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(2.2 Delay and Skew)
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<< /S /GoTo /D (subsection.2.3) >>
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(2.3 Ringing)
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<< /S /GoTo /D (section.3) >>
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(3 Worked Example)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Choose memory device size)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 Choose RAS duty cycle)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 Allocate Strobes)
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Address decoding)
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<< /S /GoTo /D (subsection.3.5) >>
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(3.5 Loading considerations)
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<< /S /GoTo /D (subsection.3.6) >>
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(3.6 Address Latching and Multiplexing)
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<< /S /GoTo /D (subsection.3.7) >>
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(3.7 Evaluate DRAM Timing)
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<< /S /GoTo /D (subsection.3.8) >>
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(3.8 Choose Write Mode)
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<< /S /GoTo /D (subsection.3.9) >>
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(3.9 Choose Refresh interval)
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<< /S /GoTo /D (subsection.3.10) >>
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(3.10 Timing for other memory and peripherals)
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<< /S /GoTo /D (subsection.3.11) >>
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(3.11 Conclusion)
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<< /S /GoTo /D (subsection.3.12) >>
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(3.12 Summary of steps required)
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<< /S /GoTo /D (section.4) >>
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(4 Further examples)
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<< /S /GoTo /D (subsection.4.1) >>
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(4.1 Minimum component, 256kbyte memory)
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<< /S /GoTo /D (subsection.4.2) >>
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(4.2 DRAM only: 1 Mbyte)
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<< /S /GoTo /D (section.5) >>
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(5 Debugging memory Systems)
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<< /S /GoTo /D (subsection.5.1) >>
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(5.1 Peeking and Poking)
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<< /S /GoTo /D (subsection.5.2) >>
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(5.2 Investigation of memory timing)
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<< /S /GoTo /D (section.6) >>
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(6 Summary)
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<< /S /GoTo /D [130 0 R /Fit ] >>
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