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<< /S /GoTo /D (section.1) >>
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(1 Introduction)
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<< /S /GoTo /D (section.2) >>
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(2 The transputer: basic architecture and concepts)
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<< /S /GoTo /D (subsection.2.1) >>
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(2.1 A programmable device)
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<< /S /GoTo /D (subsection.2.2) >>
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(2.2 Processor and memory on a single chip)
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<< /S /GoTo /D (subsection.2.3) >>
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(2.3 Serial communication between transputers)
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<< /S /GoTo /D (subsection.2.4) >>
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(2.4 Simplified processor with micro-coded scheduler)
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<< /S /GoTo /D (subsection.2.5) >>
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(2.5 Transputer products)
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<< /S /GoTo /D (section.3) >>
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(3 IMS T800 Architecture)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Instruction encoding)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 Floating point instructions)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 Optimising use of the stack)
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Concurrent operation of FPU and CPU)
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<< /S /GoTo /D (section.4) >>
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(4 Floating point unit design)
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<< /S /GoTo /D (section.5) >>
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(5 Floating point performance)
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<< /S /GoTo /D (section.6) >>
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(6 Formal methods ensure correctness and quick design)
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<< /S /GoTo /D (subsection.6.1) >>
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(6.1 Z specification)
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<< /S /GoTo /D (subsection.6.2) >>
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(6.2 High level occam implementation)
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<< /S /GoTo /D (subsection.6.3) >>
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(6.3 Low level occam Implementation)
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<< /S /GoTo /D (subsection.6.4) >>
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(6.4 Flattened low level implementation)
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<< /S /GoTo /D (subsection.6.5) >>
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(6.5 Microcode)
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<< /S /GoTo /D (subsection.6.6) >>
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(6.6 Summary)
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<< /S /GoTo /D (section.7) >>
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(7 Communication links)
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<< /S /GoTo /D (section.8) >>
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(8 Graphics capability)
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<< /S /GoTo /D (subsection.8.1) >>
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(8.1 Instruction description)
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<< /S /GoTo /D (subsection.8.2) >>
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(8.2 Drawing coloured text)
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<< /S /GoTo /D (section.9) >>
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(9 Conclusion)
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<< /S /GoTo /D (appendix.A) >>
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(A References)
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<< /S /GoTo /D (appendix.B) >>
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(B Occam)
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<< /S /GoTo /D (appendix.C) >>
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(C The "Livermore Loops")
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<< /S /GoTo /D (appendix.D) >>
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(D The formal specification language Z)
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