The ADC was running at different frequencies, depending on which timer was used
(e.g. TIM1 is on high speed APB2, TIM2 on low speed APB1).

And seems it was running a LOT slower on F4.
TRGO is used to trigger ADC conversion, which generated upon reaching period reload value.
That was 0xFFFF on F4 and 0xFF on F1.

So it seems that before this commit we had:

• F1:
  • All timers normally all run with 72MHz as we have set it up...
  • with prescaler of 8: we get 72MHz/9 = 8MHz timer freq
  • with period of 0xFF: ADC conversions at 8MHz / 255 = ~31kHz
• F4:
  • TIM1 is on ABP2 witch means twice as fast as e.g. TIM2 on APB1: timers run at 2xAPB frew: on high speed bus 168MHZ and on low speed with 84MHz
  • with prescaler of 0x53: 168MHz/84 = 2MHz timer freq for TIM1 (1MHz for TIM2)
  • with period of 0xFFFF: 2MHZ / 0xFFFF = ~30Hz (15Hz for TIM2)

That is a difference of factor 1000 between F1 and F4!!

Now it will run at same freq regarless of wich TIM is used (and same on F1/F4):
default ADC update freq: ADC_TIMER_FREQUENCY / ADC_TIMER_PERIOD = 2MHz / 1000 = 2kHz

@gautierhattenberger could you also check/test this on apogee with adc watchdog for chibios/sdcard writing?
Seems to me that the check for shouldAccumulateValue if we actually did that at 30kHz before on F1...
Which seems really high, can someone confirm this?

I will do some tests next week

closing files with chibios still work but the code doesn't compile straight:

• remove TIM9 to TIM14 (not supported by libopencm3)
• include mcu_arch.h to adc_arch.c

Since we need/use TIM9 and TIM12 for some pwm channels, I added them to mcu_arch.h...

compiling and working with chibios/sdlog now