A CHISEL Framework that provides Plug n Play API for connecting Caches in any of your CHISEL designs.
This Framework works in sync with Jigsaw Framework which provides memory devices in CHISEL designs, with which caches can be connected on.
This is not a standalone repository. It is a part of SoC-Now-Generator .
| Module | Purpose |
|---|---|
| DMCacheWrapper | Direct Mapped Cache that will communicate with Jigsaw Data Mem automatically on misses |
| DMCache | Tilelink Cached Compatible Direct Mapped Cache which will respond only Hits and Misses, TL-C shall do the rest " |
We recommend LTS releases Java 8 and Java 11. You can install the JDK as recommended by your operating system, or use the prebuilt binaries from AdoptOpenJDK.
SBT is the most common built tool in the Scala community. You can download it here.
Fork this repository on your own individual profiles. After forking clone the repository and run:
sbt testYou should see a whole bunch of output that ends with something like the following lines
[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[success] Total time: 5 s, completed Dec 16, 2020 12:18:44 PM
If you see the above then...
If you quickly want to see what verilog is being generated, go to this link https://bit.ly/3u3zr0e and write Chisel here.