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update tcl
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@ibeckermayer
ibeckermayer committed Jan 14, 2024
1 parent 677a559 commit dd135be
Showing 1 changed file with 120 additions and 37 deletions.
157 changes: 120 additions & 37 deletions Nand2TetrisVivado.tcl
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
#*****************************************************************************************
# Vivado (TM) v2020.1 (64-bit)
# Vivado (TM) v2023.2 (64-bit)
#
# Nand2TetrisVivado.tcl: Tcl script for re-creating project 'Nand2TetrisVivado'
#
# Generated by Vivado on Sun Oct 04 19:25:01 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
# Generated by Vivado on Sat Jan 13 20:09:25 PST 2024
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
Expand All @@ -23,35 +23,81 @@
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# <none>
# "/home/ubuntu/Nand2TetrisFPGA/Nand2TetrisVivado/Nand2TetrisVivado.srcs/utils_1/imports/synth_1/Hack.dcp"
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/CPU.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/VGA/Pixelclk.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/VGA/Screen_Memory_Counter.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/VGA/VGA320x240_Controller.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/VGA/VGA640x480Synch.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/Hack.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/constraints.xdc"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/test/PC_tb.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/test/ALU_tb.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/test/ROM_tb.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/test/RAM_tb.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/CPU.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ibeckermayer/Nand2TetrisFPGA/Hack/test/CPU_tb.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/CPU.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/VGA/Pixelclk.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/VGA/Screen_Memory_Counter.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/VGA/VGA320x240_Controller.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/VGA/VGA640x480Synch.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/Hack.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/constraints.xdc"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/test/PC_tb.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/test/ALU_tb.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/test/ROM_tb.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/RAMROM.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/test/RAM_tb.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/ALU.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/CPU.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/src/PC.v"
# "/home/ubuntu/Nand2TetrisFPGA/Hack/test/CPU_tb.v"
#
#*****************************************************************************************

# Check file required for this script exists
proc checkRequiredFiles { origin_dir} {
set status true
set files [list \
"[file normalize "$origin_dir/Nand2TetrisVivado/Nand2TetrisVivado.srcs/utils_1/imports/synth_1/Hack.dcp"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
puts " Could not find local file $ifile "
set status false
}
}

set files [list \
"[file normalize "$origin_dir/Hack/src/ALU.v"]"\
"[file normalize "$origin_dir/Hack/src/CPU.v"]"\
"[file normalize "$origin_dir/Hack/src/PC.v"]"\
"[file normalize "$origin_dir/Hack/src/VGA/Pixelclk.v"]"\
"[file normalize "$origin_dir/Hack/src/RAMROM.v"]"\
"[file normalize "$origin_dir/Hack/src/VGA/Screen_Memory_Counter.v"]"\
"[file normalize "$origin_dir/Hack/src/VGA/VGA320x240_Controller.v"]"\
"[file normalize "$origin_dir/Hack/src/VGA/VGA640x480Synch.v"]"\
"[file normalize "$origin_dir/Hack/src/Hack.v"]"\
"[file normalize "$origin_dir/Hack/src/constraints.xdc"]"\
"[file normalize "$origin_dir/Hack/src/PC.v"]"\
"[file normalize "$origin_dir/Hack/test/PC_tb.v"]"\
"[file normalize "$origin_dir/Hack/src/ALU.v"]"\
"[file normalize "$origin_dir/Hack/test/ALU_tb.v"]"\
"[file normalize "$origin_dir/Hack/src/RAMROM.v"]"\
"[file normalize "$origin_dir/Hack/test/ROM_tb.v"]"\
"[file normalize "$origin_dir/Hack/src/RAMROM.v"]"\
"[file normalize "$origin_dir/Hack/test/RAM_tb.v"]"\
"[file normalize "$origin_dir/Hack/src/ALU.v"]"\
"[file normalize "$origin_dir/Hack/src/CPU.v"]"\
"[file normalize "$origin_dir/Hack/src/PC.v"]"\
"[file normalize "$origin_dir/Hack/test/CPU_tb.v"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
puts " Could not find remote file $ifile "
set status false
}
}

return $status
}
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

Expand Down Expand Up @@ -119,25 +165,42 @@ if { $::argc > 0 } {
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/Nand2TetrisVivado"]"

# Check for paths and files needed for project creation
set validate_required 0
if { $validate_required } {
if { [checkRequiredFiles $origin_dir] } {
puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
} else {
puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
return
}
}

# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35tcpg236-1

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Reconstruct message rules
# None

# Set project properties
set obj [current_project]
set_property -name "board_part" -value "digilentinc.com:basys3:part0:1.1" -objects $obj
set_property -name "board_part_repo_paths" -value "[file normalize "$origin_dir/../.Xilinx/Vivado/2020.1/xhub/board_store/xilinx_board_store"]" -objects $obj
set_property -name "board_part" -value "digilentinc.com:basys3:part0:1.2" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_resource_estimation" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "feature_set" -value "FeatureSet_Classic" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "platform.board_id" -value "basys3" -objects $obj
set_property -name "revised_directory_structure" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "sim_compile_state" -value "1" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "24" -objects $obj
set_property -name "xsim.array_display_limit" -value "1000000" -objects $obj
set_property -name "xsim.trace_limit" -value "1000000" -objects $obj
Expand Down Expand Up @@ -170,6 +233,7 @@ add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
set_property -name "top" -value "Hack" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj

Expand Down Expand Up @@ -205,8 +269,8 @@ set obj [get_filesets sim_1]

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "top" -value "Hack" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Create 'PC_sim' fileset (if not found)
Expand All @@ -230,7 +294,6 @@ add_files -norecurse -fileset $obj $files

# Set 'PC_sim' fileset properties
set obj [get_filesets PC_sim]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "source_set" -value "" -objects $obj
set_property -name "top" -value "PC_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
Expand All @@ -257,7 +320,6 @@ add_files -norecurse -fileset $obj $files

# Set 'ALU_sim' fileset properties
set obj [get_filesets ALU_sim]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "source_set" -value "" -objects $obj
set_property -name "top" -value "ALU_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
Expand All @@ -284,7 +346,6 @@ add_files -norecurse -fileset $obj $files

# Set 'ROM_sim' fileset properties
set obj [get_filesets ROM_sim]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "source_set" -value "" -objects $obj
set_property -name "top" -value "ROM_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
Expand All @@ -311,7 +372,6 @@ add_files -norecurse -fileset $obj $files

# Set 'RAM_sim' fileset properties
set obj [get_filesets RAM_sim]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "source_set" -value "" -objects $obj
set_property -name "top" -value "RAM_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
Expand Down Expand Up @@ -340,19 +400,37 @@ add_files -norecurse -fileset $obj $files

# Set 'CPU_sim' fileset properties
set obj [get_filesets CPU_sim]
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "source_set" -value "" -objects $obj
set_property -name "top" -value "CPU_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Empty (no sources present)
# Add local files from the original project (-no_copy_sources specified)
set files [list \
[file normalize "${origin_dir}/Nand2TetrisVivado/Nand2TetrisVivado.srcs/utils_1/imports/synth_1/Hack.dcp" ]\
]
set added_files [add_files -fileset utils_1 $files]

# Set 'utils_1' fileset file properties for remote files
# None

# Set 'utils_1' fileset file properties for local files
set file "synth_1/Hack.dcp"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "netlist_only" -value "0" -objects $file_obj


# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]

set idrFlowPropertiesConstraints ""
catch {
set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
set_param runs.disableIDRFlowPropertyConstraints 1
}

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7a35tcpg236-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
Expand All @@ -373,7 +451,8 @@ if { $obj != "" } {

}
set obj [get_runs synth_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "incremental_checkpoint" -value "$proj_dir/Nand2TetrisVivado.srcs/utils_1/imports/synth_1/Hack.dcp" -objects $obj
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj

# set the current synth run
Expand Down Expand Up @@ -587,13 +666,17 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
set obj [get_runs impl_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj

# set the current impl run
current_run -implementation [get_runs impl_1]
catch {
if { $idrFlowPropertiesConstraints != {} } {
set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
}
}

puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
Expand Down

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