To objectively evaluate and compare software and design automation tools for the physical design of FCN, diverse benchmark sets with function descriptions are needed.
MNT Bench provides functions from the following benchmark sets in Verilog (.v) format:
For convenience, they are also part of fiction to be directly used in experiments or the development of new physical design algorithms, optimizations, and simulators.
Gate-level layouts generated with any of the physical design methods implemented in fiction can be stored in a human-readable file format (.fgl) with the
correponding write function.
MNT Bench offers gate-level layouts spanning various gate libraries, clocking schemes, physical design algorithms, and optimizations. These layouts can be read with fiction and used for testing new post-layout optimization algorithms, creating cell-level layouts, or any other use case.