This is a sample testbench for a Tiny Tapeout project. It uses cocotb to drive the DUT and check the outputs. See below to get started or for more information, check the website.

1. Edit Makefile and modify PROJECT_SOURCES to point to your Verilog files.
2. Edit tb.v and replace tt_um_example with your module name.

To run the RTL simulation:

make -B

To run gatelevel simulation, first harden your project and copy ../runs/wokwi/results/final/verilog/gl/{your_module_name}.v to gate_level_netlist.v.

Then run:

make -B GATES=yes

gtkwave tb.vcd tb.gtkw