Skip to content

Instantly share code, notes, and snippets.

@davidlohr
Last active December 11, 2023 02:09
Show Gist options
  • Save davidlohr/fd33cbd2f38a23a9aff7e5cdbf1bf835 to your computer and use it in GitHub Desktop.
Save davidlohr/fd33cbd2f38a23a9aff7e5cdbf1bf835 to your computer and use it in GitHub Desktop.
syzkaller config - qemu deployment emulating a 4 devices setup below a switch suitable for 1, 2 or 4 way interleave
{
"target": "linux/amd64",
"http": "127.0.0.1:56741",
"workdir": "workdir",
"kernel_obj": "/home/dave/code/linux/",
"image": "/img/bullseye.img",
"sshkey": "/img/bullseye.id_rsa",
"syzkaller": "/home/dave/code/syzkaller",
"procs": 8,
"type": "qemu",
"enable_syscalls": [ "openat$cxl*", "write$cxl*", "ioctl$CXL*","syz_open_dev$cxlmem*" ],
"vm": {
"qemu": "/home/dave/git/qemu-vanilla/build/qemu-system-x86_64",
"count": 1,
"qemu_args": "-machine q35,accel=kvm,cxl=on -object memory-backend-file,id=cxl-mem0,share=on,mem-path=/tmp/cxltest.raw,size=256M -object memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest1.raw,size=256M -object memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M -object memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa0.raw,size=256M -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa1.raw,size=256M -object memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M -object memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 -device cxl-rp,port=0,bus=cxl.1,id=root_port0,chassis=0,slot=0 -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 -device cxl-upstream,bus=root_port0,id=us0 -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k",
"kernel": "/home/dave/code/linux/arch/x86/boot/bzImage",
"cmdline": "net.ifnames=0 cxl_acpi.dyndbg=+fplm cxl_pci.dyndbg=+fplm cxl_core.dyndbg=+fplm cxl_mem.dyndbg=+fplm cxl_pmem.dyndbg=+fplm cxl_port.dyndbg=+fplm cxl_region.dyndbg=+fplm cxl_test.dyndbg=+fplm",
"cpu": 4,
"mem": 2048
}
}
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment