#define SYSC_NREG % rax #define SYSC_AGQ0 % rdi #define SYSC_AGQ1 % rsi #define SYSC_AGQ2 % rdx #define SYSC_AGQ3 % r10 #define SYSC_AGQ4 % r8 #define SYSC_AGQ5 % r9 #define SYSC_RETQ % rax #define SYSC_AGD0 % edi #define SYSC_AGD1 % esi #define SYSC_AGD2 % edx #define SYSC_AGD3 % r10d #define SYSC_AGD4 % r8d #define SYSC_AGD5 % r9d #define SYSC_RETD % eax #define SYSC_AGW0 % di #define SYSC_AGW1 % si #define SYSC_AGW2 % dx #define SYSC_AGW3 % r10w #define SYSC_AGW4 % r8w #define SYSC_AGW5 % r9w #define SYSC_RETW % ax #define SYSC_AGL0 % dl #define SYSC_AGL1 % sil #define SYSC_AGL2 % dl #define SYSC_AGL3 % r10b #define SYSC_AGL4 % r8b #define SYSC_AGL5 % r9b #define SYSC_RETL % al #define SYSC_AGH0 % dh #define SYSC_AGH1 % sil #define SYSC_AGH2 % dh #define SYSC_AGH3 % r10b #define SYSC_AGH4 % r8b #define SYSC_AGH5 % r9b #define SYSC_RETH % ah #define CABI_AGQ0 % rdi #define CABI_AGQ1 % rsi #define CABI_AGQ2 % rdx #define CABI_AGQ3 % rcx #define CABI_AGQ4 % r8 #define CABI_AGQ5 % r9 #define CABI_RETQ % rax #define CABI_AGD0 % edi #define CABI_AGD1 % esi #define CABI_AGD2 % edx #define CABI_AGD3 % ecx #define CABI_AGD4 % r8d #define CABI_AGD5 % r9d #define CABI_RETD % eax #define CABI_AGW0 % di #define CABI_AGW1 % si #define CABI_AGW2 % dx #define CABI_AGW3 % cx #define CABI_AGW4 % r8w #define CABI_AGW5 % r9w #define CABI_RETW % ax #define CABI_AGL0 % dl #define CABI_AGL1 % sil #define CABI_AGL2 % dl #define CABI_AGL3 % cl #define CABI_AGL4 % r8b #define CABI_AGL5 % r9b #define CABI_RETL % al #define CABI_AGH0 % dh #define CABI_AGH1 % sil #define CABI_AGH2 % dh #define CABI_AGH3 % ch #define CABI_AGH4 % r8b #define CABI_AGH5 % r9b #define CABI_RETH % ah #define CNTR_QWRD % rcx #define CNTR_DWRD % ecx #define CNTR_WORD % cx #define CNTR_LOWB % cl #define CNTR_HIIB % ch #define ACCM_QWRD % rax #define ACCM_DWRD % eax #define ACCM_WORD % ax #define ACCM_LOWB % al #define ACCM_HIIB % ah #define STPT_QWRD % rsp #define STPT_DWRD % esp #define STPT_WORD % sp #define STPT_LOWB % spl #define FPPT_QWRD % rbp #define FPPT_DWRD % ebp #define FPPT_WORD % bp #define FPPT_LOWB % bpl #define CLB1_QWRD % r10 #define CLB1_DWRD % r10d #define CLB1_WORD % r10w #define CLB1_LOWB % r10b #define CLB2_QWRD % r11 #define CLB2_DWRD % r11d #define CLB2_WORD % r11w #define CLB2_LOWB % r11b #define CSV1_QWRD % r8 #define CSV1_DWRD % r8d #define CSV1_WORD % r8w #define CSV1_LOWB % r8b #define CSV2_QWRD % r9 #define CSV2_DWRD % r9d #define CSV2_WORD % r9w #define CSV2_LOWB % r9b #define CSV3_QWRD % r12 #define CSV3_DWRD % r12d #define CSV3_WORD % r12w #define CSV3_LOWB % r12b #define CSV4_QWRD % r13 #define CSV4_DWRD % r13d #define CSV4_WORD % r13w #define CSV4_LOWB % r13b #define CSV5_QWRD % r14 #define CSV5_DWRD % r14d #define CSV5_WORD % r14w #define CSV5_LOWB % r14b #define CSV6_QWRD % r15 #define CSV6_DWRD % r15d #define CSV6_WORD % r15w #define CSV6_LOWB % r15b #define SRCR_QWRD % rsi #define SRCR_DWRD % esi #define SRCR_WORD % si #define SRCR_LOWB % sil #define DATA_QWRD % rdx #define DATA_DWRD % edx #define DATA_WORD % dx #define DATA_LOWB % dl #define DATA_HIIB % dh #define DEST_QWRD % rdi #define DEST_DWRD % edi #define DEST_WORD % di #define DEST_LOWB % dl #define DEST_HIIB % dh #define BASE_QWRD % rbx #define BASE_DWRD % ebx #define BASE_WORD % bx #define BASE_LOWB % bl #define BASE_HIIB % bh #define V512_RG00 %zmm0 #define V512_RG01 %zmm1 #define V512_RG02 %zmm2 #define V512_RG03 %zmm3 #define V512_RG04 %zmm4 #define V512_RG05 %zmm5 #define V512_RG06 %zmm6 #define V512_RG07 %zmm7 #define V512_RG08 %zmm8 #define V512_RG09 %zmm9 #define V512_RG10 %zmm10 #define V512_RG11 %zmm11 #define V512_RG12 %zmm12 #define V512_RG13 %zmm13 #define V512_RG14 %zmm14 #define V512_RG15 %zmm15 #define V256_RG00 %ymm0 #define V256_RG01 %ymm1 #define V256_RG02 %ymm2 #define V256_RG03 %ymm3 #define V256_RG04 %ymm4 #define V256_RG05 %ymm5 #define V256_RG06 %ymm6 #define V256_RG07 %ymm7 #define V256_RG08 %ymm8 #define V256_RG09 %ymm9 #define V256_RG10 %ymm10 #define V256_RG11 %ymm11 #define V256_RG12 %ymm12 #define V256_RG13 %ymm13 #define V256_RG14 %ymm14 #define V256_RG15 %ymm15 #define V128_RG00 %xmm0 #define V128_RG01 %xmm1 #define V128_RG02 %xmm2 #define V128_RG03 %xmm3 #define V128_RG04 %xmm4 #define V128_RG05 %xmm5 #define V128_RG06 %xmm6 #define V128_RG07 %xmm7 #define V128_RG08 %xmm8 #define V128_RG09 %xmm9 #define V128_RG10 %xmm10 #define V128_RG11 %xmm11 #define V128_RG12 %xmm12 #define V128_RG13 %xmm13 #define V128_RG14 %xmm14 #define V128_RG15 %xmm15 #define MASK_REG0 %k0 #define MASK_REG1 %k1 #define MASK_REG2 %k2 #define MASK_REG3 %k3 #define MASK_REG4 %k4 #define MASK_REG5 %k5 #define MASK_REG6 %k6 #define MASK_REG7 %k7 #define REGISTER_zero_out(reg) xor reg, reg