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[RFC] Desugar variadics. Codegen for new targets, optimisation for existing
|
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6
|
815
|
July 19, 2024
|
|
some dialects in AMGGPU dialects are equal to ROCDL dialects , Is it redundant?
|
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1
|
123
|
June 20, 2024
|
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Assembling and linking AMD GPU kernel code
|
|
21
|
401
|
May 16, 2024
|
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[RFC] MMRAs - Memory Model Relaxation Annotations
|
|
16
|
855
|
May 14, 2024
|
|
Loop unroller fails to unroll loop
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6
|
689
|
April 23, 2024
|
|
Confused by inconsistencies in GPU magic constants
|
|
19
|
697
|
September 18, 2023
|
|
InferAddrSpace] The operand with non-FLAT-address-space got Undefined when rewriting its user to new address space
|
|
28
|
530
|
September 4, 2023
|
|
The value of a constant global variable is random after linking for AMDGPU
|
|
0
|
204
|
July 18, 2023
|
|
[RFC] Cleaning up the NVIDIA (and potentially AMD) GPU backend
|
|
5
|
531
|
June 29, 2023
|
|
Catching up on uniformity analysis
|
|
5
|
454
|
February 13, 2023
|
|
Convert NVIDIA GPU LLVM IR(NVVM) alloca instruction to AMDGPU's
|
|
7
|
1192
|
September 9, 2022
|
|
[TableGen/RegAlloc] How to use a fixed register in an instruction?
|
|
5
|
724
|
August 16, 2022
|
|
[GISel/DAG] Getting a TableGen pattern to match both `G_ADD` and `G_PTR_ADD` in GISel
|
|
0
|
252
|
August 12, 2022
|
|
Feedback on new flag for AMDGPU
|
|
4
|
382
|
February 22, 2022
|
